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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-759cbc680absm1795568b3a.144.2025.07.18.15.15.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Jul 2025 15:15:57 -0700 (PDT) From: Jessica Zhang Date: Fri, 18 Jul 2025 15:15:51 -0700 Subject: [PATCH] drm/msm/dp: Propagate core clock enable error in runtime resume Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250718-dp-clk-error-v1-1-9bb5f28d4927@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIAJbHemgC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDI1MDcwNj3ZQC3eScbN3UoqL8Il3zZENLM1MDMzNTE0MloJaCotS0zAqwcdG xtbUAe16cUl4AAAA= X-Change-ID: 20250703-dp-clk-error-7c1965066541 To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Sean Paul X-Mailer: b4 0.15-dev-a9b2a X-Developer-Signature: v=1; a=ed25519-sha256; t=1752876956; l=2330; i=jessica.zhang@oss.qualcomm.com; s=20230329; h=from:subject:message-id; bh=+ObMCEP0xXFpmbdqHtBPYDKFpPRzfo7882m39lX89Tg=; b=dgS9lNvWdwfby7lBzTlT1cofoz3lNYpyZ62ENSpTmdID0SgnlzSsj9e0Vdl8ysD9gnJPYJXlP 3o8Eta1eK/GDXhhc3Dbp8FQ1HzTSVUSTi+inNYbjgPWxPp82OplE178 X-Developer-Key: i=jessica.zhang@oss.qualcomm.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Proofpoint-ORIG-GUID: AitJMDuUqK5crk-CZ1mnuIKBsoIlmKM3 X-Authority-Analysis: v=2.4 cv=RtXFLDmK c=1 sm=1 tr=0 ts=687ac79e cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=_9WUdxqi14MbyrDA3vYA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE4MDE4MiBTYWx0ZWRfX/bOZmzvw+RkQ MBlcRBarJBU9rkDvc1dB07S7Nt/tmDdv7Nu3ACHXfmw61RY6JlFuqLf9U8rlyoE8OwaS8PQilmw EJwQ6+k2rVHgjqBKIuchCgnf171B9m0Xf0grTePb6LlIFk68wH/t06Mq2qM3EevU8bjVeZwM1mA P1QxB+JWseXTQ+5Rw/sEhQLc6Oijn3AlAVAuITBF5Y11tkm6Lrtxqzq8VM9xA3WW2SdSzoe2jKN aX4ig20fKrxdjjyFVcHSCBYf1qA8AWxgKTrBH6nPrHPDO1E2mGZODmup3NQvbTF2sm1m3v7cf+X kVzt2WE3HswgiHDCeDHWNzYwtwAoQM/HTMpg0HmInyTVCLSA+QG5FljRZu7KfHAEI+DBP14Qah2 apjzYHiYQMDvrFGcDy85zyDhTsQ/PvSzVGH75z0vwp3fzdV00gWeekZR+La7pWrQibhrrnNR X-Proofpoint-GUID: AitJMDuUqK5crk-CZ1mnuIKBsoIlmKM3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-18_05,2025-07-17_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxscore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 clxscore=1015 mlxlogscore=999 priorityscore=1501 phishscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507180182 Currently, runtime resume will always return success even if the core clock enable fails. Propagate any core clock enable errors during the resume to avoid any crashes later. Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/dp/dp_display.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index d87d47cc7ec3..77d5e89239d2 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -463,17 +463,24 @@ static void msm_dp_display_host_phy_exit(struct msm_dp_display_private *dp) } } -static void msm_dp_display_host_init(struct msm_dp_display_private *dp) +static int msm_dp_display_host_init(struct msm_dp_display_private *dp) { + int rc; + drm_dbg_dp(dp->drm_dev, "type=%d core_init=%d phy_init=%d\n", dp->msm_dp_display.connector_type, dp->core_initialized, dp->phy_initialized); - msm_dp_ctrl_core_clk_enable(dp->ctrl); + rc = msm_dp_ctrl_core_clk_enable(dp->ctrl); + if (rc) + return rc; + msm_dp_ctrl_reset(dp->ctrl); msm_dp_ctrl_enable_irq(dp->ctrl); msm_dp_aux_init(dp->aux); dp->core_initialized = true; + + return 0; } static void msm_dp_display_host_deinit(struct msm_dp_display_private *dp) @@ -1453,6 +1460,7 @@ static int msm_dp_pm_runtime_suspend(struct device *dev) static int msm_dp_pm_runtime_resume(struct device *dev) { struct msm_dp_display_private *dp = dev_get_dp_display_private(dev); + int rc; /* * for eDP, host cotroller, HPD block and PHY are enabled here @@ -1462,14 +1470,14 @@ static int msm_dp_pm_runtime_resume(struct device *dev) * HPD block is enabled at msm_dp_bridge_hpd_enable() * PHY will be enabled at plugin handler later */ - msm_dp_display_host_init(dp); + rc = msm_dp_display_host_init(dp); if (dp->msm_dp_display.is_edp) { msm_dp_aux_hpd_enable(dp->aux); msm_dp_display_host_phy_init(dp); } enable_irq(dp->irq); - return 0; + return rc; } static const struct dev_pm_ops msm_dp_pm_ops = { --- base-commit: d086c886ceb9f59dea6c3a9dae7eb89e780a20c9 change-id: 20250703-dp-clk-error-7c1965066541 Best regards, -- Jessica Zhang