* [PATCH v2 0/2] clk: spacemit: fix sspax_clk
@ 2025-07-22 7:36 Troy Mitchell
2025-07-22 7:36 ` [PATCH v2 1/2] " Troy Mitchell
2025-07-22 7:36 ` [PATCH v2 2/2] dt-bindings: clock: spacemit: CLK_SSPA_I2S_BCLK for SSPA Troy Mitchell
0 siblings, 2 replies; 8+ messages in thread
From: Troy Mitchell @ 2025-07-22 7:36 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Yixun Lan, Alex Elder,
Haylen Chu, Inochi Amaoto, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-clk, linux-riscv, spacemit, linux-kernel, devicetree,
Troy Mitchell, Yao Zi
In the SpacemiT public document, when the FNCLKSEL field of
the APBC_SSPAX_CLK_RST register is 7 (3'b111),
which is a reserved value. And BIT3 of the same register is
a reserved bit.
But the documentation is incorrect. In reality, the value 7 (3'b111)
of FNCLKSEL is not reserved. Instead, it indicates that i2s_bclk is
selected as the parent clock. Similarly, bit 3 is not reserved either.
When FNCLKSEL is set to 7, bit 3 determines whether i2s_bclk is actually
enabled as the parent clock.
In all other cases (i.e., when FNCLKSEL is not 7), bit 3 has no effect.
Importantly, whenever FNCLKSEL is set to 7, bit 3 must also be set to 1,
otherwise the selection of i2s_bclk becomes invalid.
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
---
Change log in v2:
- Use dummy gate instead of new function for sspa
- Add Suggested-by tag: Yao Zi
- Add Fixes tag
- Link to v1: https://lore.kernel.org/all/20250718-k1-clk-i2s-v1-1-e92c10fd0f60@linux.spacemit.com/
---
Troy Mitchell (2):
clk: spacemit: fix sspax_clk
dt-bindings: clock: spacemit: CLK_SSPA_I2S_BCLK for SSPA
drivers/clk/spacemit/ccu-k1.c | 25 +++++-
include/dt-bindings/clock/spacemit,k1-syscon.h | 114 +++++++++++++------------
2 files changed, 79 insertions(+), 60 deletions(-)
---
base-commit: 733923397fd95405a48f165c9b1fbc8c4b0a4681
change-id: 20250717-k1-clk-i2s-e4272f1f915b
Best regards,
--
Troy Mitchell <troy.mitchell@linux.spacemit.com>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 1/2] clk: spacemit: fix sspax_clk
2025-07-22 7:36 [PATCH v2 0/2] clk: spacemit: fix sspax_clk Troy Mitchell
@ 2025-07-22 7:36 ` Troy Mitchell
2025-07-22 7:36 ` [PATCH v2 2/2] dt-bindings: clock: spacemit: CLK_SSPA_I2S_BCLK for SSPA Troy Mitchell
1 sibling, 0 replies; 8+ messages in thread
From: Troy Mitchell @ 2025-07-22 7:36 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Yixun Lan, Alex Elder,
Haylen Chu, Inochi Amaoto, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-clk, linux-riscv, spacemit, linux-kernel, devicetree,
Troy Mitchell, Yao Zi
Hardware Requirement:
When FNCLKSEL in APBC_SSPAX_CLK_RST is set to 7 (3'b111),
BIT3 must be set to 1 for the SSPAx parent clock to be I2S_BCLK.
This patch introduces SSPAx_I2S_BCLK as a dummy gate to enable BIT3.
Fixes: 1b72c59db0add ("clk: spacemit: Add clock support for SpacemiT K1 SoC")
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Suggested-by: Yao Zi <ziyao@disroot.org>
---
drivers/clk/spacemit/ccu-k1.c | 25 +++++++++++++++++++++----
1 file changed, 21 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c
index cdde37a0523537c2f436e481ae8d6ec5a581b87e..3b1a861729c6e7ef64bd42b975688058610d8c1c 100644
--- a/drivers/clk/spacemit/ccu-k1.c
+++ b/drivers/clk/spacemit/ccu-k1.c
@@ -349,7 +349,10 @@ CCU_GATE_DEFINE(aib_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_AIB_CLK_RST, BIT(1),
CCU_GATE_DEFINE(onewire_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_ONEWIRE_CLK_RST, BIT(1), 0);
-static const struct clk_parent_data sspa_parents[] = {
+CCU_GATE_DEFINE(sspa0_i2s_bclk, CCU_PARENT_HW(i2s_bclk), APBC_SSPA0_CLK_RST, BIT(3), 0);
+CCU_GATE_DEFINE(sspa1_i2s_bclk, CCU_PARENT_HW(i2s_bclk), APBC_SSPA1_CLK_RST, BIT(3), 0);
+
+static const struct clk_parent_data sspa0_parents[] = {
CCU_PARENT_HW(pll1_d384_6p4),
CCU_PARENT_HW(pll1_d192_12p8),
CCU_PARENT_HW(pll1_d96_25p6),
@@ -357,10 +360,22 @@ static const struct clk_parent_data sspa_parents[] = {
CCU_PARENT_HW(pll1_d768_3p2),
CCU_PARENT_HW(pll1_d1536_1p6),
CCU_PARENT_HW(pll1_d3072_0p8),
- CCU_PARENT_HW(i2s_bclk),
+ CCU_PARENT_HW(sspa0_i2s_bclk),
};
-CCU_MUX_GATE_DEFINE(sspa0_clk, sspa_parents, APBC_SSPA0_CLK_RST, 4, 3, BIT(1), 0);
-CCU_MUX_GATE_DEFINE(sspa1_clk, sspa_parents, APBC_SSPA1_CLK_RST, 4, 3, BIT(1), 0);
+CCU_MUX_GATE_DEFINE(sspa0_clk, sspa0_parents, APBC_SSPA0_CLK_RST, 4, 3, BIT(1), 0);
+
+static const struct clk_parent_data sspa1_parents[] = {
+ CCU_PARENT_HW(pll1_d384_6p4),
+ CCU_PARENT_HW(pll1_d192_12p8),
+ CCU_PARENT_HW(pll1_d96_25p6),
+ CCU_PARENT_HW(pll1_d48_51p2),
+ CCU_PARENT_HW(pll1_d768_3p2),
+ CCU_PARENT_HW(pll1_d1536_1p6),
+ CCU_PARENT_HW(pll1_d3072_0p8),
+ CCU_PARENT_HW(sspa1_i2s_bclk),
+};
+CCU_MUX_GATE_DEFINE(sspa1_clk, sspa1_parents, APBC_SSPA1_CLK_RST, 4, 3, BIT(1), 0);
+
CCU_GATE_DEFINE(dro_clk, CCU_PARENT_HW(apb_clk), APBC_DRO_CLK_RST, BIT(1), 0);
CCU_GATE_DEFINE(ir_clk, CCU_PARENT_HW(apb_clk), APBC_IR_CLK_RST, BIT(1), 0);
CCU_GATE_DEFINE(tsen_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(1), 0);
@@ -909,6 +924,8 @@ static struct clk_hw *k1_ccu_apbc_hws[] = {
[CLK_TIMERS2] = &timers2_clk.common.hw,
[CLK_AIB] = &aib_clk.common.hw,
[CLK_ONEWIRE] = &onewire_clk.common.hw,
+ [CLK_SSPA0_I2S_BCLK] = &sspa0_i2s_bclk.common.hw,
+ [CLK_SSPA1_I2S_BCLK] = &sspa1_i2s_bclk.common.hw,
[CLK_SSPA0] = &sspa0_clk.common.hw,
[CLK_SSPA1] = &sspa1_clk.common.hw,
[CLK_DRO] = &dro_clk.common.hw,
--
2.50.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 2/2] dt-bindings: clock: spacemit: CLK_SSPA_I2S_BCLK for SSPA
2025-07-22 7:36 [PATCH v2 0/2] clk: spacemit: fix sspax_clk Troy Mitchell
2025-07-22 7:36 ` [PATCH v2 1/2] " Troy Mitchell
@ 2025-07-22 7:36 ` Troy Mitchell
2025-07-22 9:21 ` Yixun Lan
2025-07-23 4:41 ` Rob Herring
1 sibling, 2 replies; 8+ messages in thread
From: Troy Mitchell @ 2025-07-22 7:36 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Yixun Lan, Alex Elder,
Haylen Chu, Inochi Amaoto, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: linux-clk, linux-riscv, spacemit, linux-kernel, devicetree,
Troy Mitchell
This patch adds macro definitions: SSPAx_I2S_BCLK,
to introduce a dummy gate for i2s_bclk.
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
---
include/dt-bindings/clock/spacemit,k1-syscon.h | 114 +++++++++++++------------
1 file changed, 58 insertions(+), 56 deletions(-)
diff --git a/include/dt-bindings/clock/spacemit,k1-syscon.h b/include/dt-bindings/clock/spacemit,k1-syscon.h
index 35968ae98246609c889eb4a7d08b4ff7360de53b..6914ccf5be45a1071d5b6eac354cacb67888e00c 100644
--- a/include/dt-bindings/clock/spacemit,k1-syscon.h
+++ b/include/dt-bindings/clock/spacemit,k1-syscon.h
@@ -123,62 +123,64 @@
#define CLK_TIMERS2 41
#define CLK_AIB 42
#define CLK_ONEWIRE 43
-#define CLK_SSPA0 44
-#define CLK_SSPA1 45
-#define CLK_DRO 46
-#define CLK_IR 47
-#define CLK_TSEN 48
-#define CLK_IPC_AP2AUD 49
-#define CLK_CAN0 50
-#define CLK_CAN0_BUS 51
-#define CLK_UART0_BUS 52
-#define CLK_UART2_BUS 53
-#define CLK_UART3_BUS 54
-#define CLK_UART4_BUS 55
-#define CLK_UART5_BUS 56
-#define CLK_UART6_BUS 57
-#define CLK_UART7_BUS 58
-#define CLK_UART8_BUS 59
-#define CLK_UART9_BUS 60
-#define CLK_GPIO_BUS 61
-#define CLK_PWM0_BUS 62
-#define CLK_PWM1_BUS 63
-#define CLK_PWM2_BUS 64
-#define CLK_PWM3_BUS 65
-#define CLK_PWM4_BUS 66
-#define CLK_PWM5_BUS 67
-#define CLK_PWM6_BUS 68
-#define CLK_PWM7_BUS 69
-#define CLK_PWM8_BUS 70
-#define CLK_PWM9_BUS 71
-#define CLK_PWM10_BUS 72
-#define CLK_PWM11_BUS 73
-#define CLK_PWM12_BUS 74
-#define CLK_PWM13_BUS 75
-#define CLK_PWM14_BUS 76
-#define CLK_PWM15_BUS 77
-#define CLK_PWM16_BUS 78
-#define CLK_PWM17_BUS 79
-#define CLK_PWM18_BUS 80
-#define CLK_PWM19_BUS 81
-#define CLK_SSP3_BUS 82
-#define CLK_RTC_BUS 83
-#define CLK_TWSI0_BUS 84
-#define CLK_TWSI1_BUS 85
-#define CLK_TWSI2_BUS 86
-#define CLK_TWSI4_BUS 87
-#define CLK_TWSI5_BUS 88
-#define CLK_TWSI6_BUS 89
-#define CLK_TWSI7_BUS 90
-#define CLK_TWSI8_BUS 91
-#define CLK_TIMERS1_BUS 92
-#define CLK_TIMERS2_BUS 93
-#define CLK_AIB_BUS 94
-#define CLK_ONEWIRE_BUS 95
-#define CLK_SSPA0_BUS 96
-#define CLK_SSPA1_BUS 97
-#define CLK_TSEN_BUS 98
-#define CLK_IPC_AP2AUD_BUS 99
+#define CLK_SSPA0_I2S_BCLK 44
+#define CLK_SSPA1_I2S_BCLK 45
+#define CLK_SSPA0 46
+#define CLK_SSPA1 47
+#define CLK_DRO 48
+#define CLK_IR 49
+#define CLK_TSEN 50
+#define CLK_IPC_AP2AUD 51
+#define CLK_CAN0 52
+#define CLK_CAN0_BUS 53
+#define CLK_UART0_BUS 54
+#define CLK_UART2_BUS 55
+#define CLK_UART3_BUS 56
+#define CLK_UART4_BUS 57
+#define CLK_UART5_BUS 58
+#define CLK_UART6_BUS 59
+#define CLK_UART7_BUS 60
+#define CLK_UART8_BUS 61
+#define CLK_UART9_BUS 62
+#define CLK_GPIO_BUS 63
+#define CLK_PWM0_BUS 64
+#define CLK_PWM1_BUS 65
+#define CLK_PWM2_BUS 66
+#define CLK_PWM3_BUS 67
+#define CLK_PWM4_BUS 68
+#define CLK_PWM5_BUS 69
+#define CLK_PWM6_BUS 70
+#define CLK_PWM7_BUS 71
+#define CLK_PWM8_BUS 72
+#define CLK_PWM9_BUS 73
+#define CLK_PWM10_BUS 74
+#define CLK_PWM11_BUS 75
+#define CLK_PWM12_BUS 76
+#define CLK_PWM13_BUS 77
+#define CLK_PWM14_BUS 78
+#define CLK_PWM15_BUS 79
+#define CLK_PWM16_BUS 80
+#define CLK_PWM17_BUS 81
+#define CLK_PWM18_BUS 82
+#define CLK_PWM19_BUS 83
+#define CLK_SSP3_BUS 84
+#define CLK_RTC_BUS 85
+#define CLK_TWSI0_BUS 86
+#define CLK_TWSI1_BUS 87
+#define CLK_TWSI2_BUS 88
+#define CLK_TWSI4_BUS 89
+#define CLK_TWSI5_BUS 90
+#define CLK_TWSI6_BUS 91
+#define CLK_TWSI7_BUS 92
+#define CLK_TWSI8_BUS 93
+#define CLK_TIMERS1_BUS 94
+#define CLK_TIMERS2_BUS 95
+#define CLK_AIB_BUS 96
+#define CLK_ONEWIRE_BUS 97
+#define CLK_SSPA0_BUS 98
+#define CLK_SSPA1_BUS 99
+#define CLK_TSEN_BUS 100
+#define CLK_IPC_AP2AUD_BUS 101
/* APMU clocks */
#define CLK_CCI550 0
--
2.50.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 2/2] dt-bindings: clock: spacemit: CLK_SSPA_I2S_BCLK for SSPA
2025-07-22 7:36 ` [PATCH v2 2/2] dt-bindings: clock: spacemit: CLK_SSPA_I2S_BCLK for SSPA Troy Mitchell
@ 2025-07-22 9:21 ` Yixun Lan
2025-07-22 9:27 ` Troy Mitchell
2025-07-23 4:41 ` Rob Herring
1 sibling, 1 reply; 8+ messages in thread
From: Yixun Lan @ 2025-07-22 9:21 UTC (permalink / raw)
To: Troy Mitchell
Cc: Michael Turquette, Stephen Boyd, Alex Elder, Haylen Chu,
Inochi Amaoto, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-clk, linux-riscv, spacemit, linux-kernel, devicetree
Hi Troy,
On 15:36 Tue 22 Jul , Troy Mitchell wrote:
> This patch adds macro definitions: SSPAx_I2S_BCLK,
this is obvious, so no need to repeat, please add something useful
> to introduce a dummy gate for i2s_bclk.
~~~~~~ 'virtual'? if it isn't a real gate clock,
but I'm not sure it's a good approach to introduce such
virtual clock if underlying hw doesn't comply with this
>
> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
> ---
> include/dt-bindings/clock/spacemit,k1-syscon.h | 114 +++++++++++++------------
> 1 file changed, 58 insertions(+), 56 deletions(-)
dt-binding patch should always go first
>
> diff --git a/include/dt-bindings/clock/spacemit,k1-syscon.h b/include/dt-bindings/clock/spacemit,k1-syscon.h
> index 35968ae98246609c889eb4a7d08b4ff7360de53b..6914ccf5be45a1071d5b6eac354cacb67888e00c 100644
> --- a/include/dt-bindings/clock/spacemit,k1-syscon.h
> +++ b/include/dt-bindings/clock/spacemit,k1-syscon.h
> @@ -123,62 +123,64 @@
> #define CLK_TIMERS2 41
> #define CLK_AIB 42
> #define CLK_ONEWIRE 43
> -#define CLK_SSPA0 44
> -#define CLK_SSPA1 45
> -#define CLK_DRO 46
> -#define CLK_IR 47
> -#define CLK_TSEN 48
> -#define CLK_IPC_AP2AUD 49
> -#define CLK_CAN0 50
> -#define CLK_CAN0_BUS 51
> -#define CLK_UART0_BUS 52
> -#define CLK_UART2_BUS 53
> -#define CLK_UART3_BUS 54
> -#define CLK_UART4_BUS 55
> -#define CLK_UART5_BUS 56
> -#define CLK_UART6_BUS 57
> -#define CLK_UART7_BUS 58
> -#define CLK_UART8_BUS 59
> -#define CLK_UART9_BUS 60
> -#define CLK_GPIO_BUS 61
> -#define CLK_PWM0_BUS 62
> -#define CLK_PWM1_BUS 63
> -#define CLK_PWM2_BUS 64
> -#define CLK_PWM3_BUS 65
> -#define CLK_PWM4_BUS 66
> -#define CLK_PWM5_BUS 67
> -#define CLK_PWM6_BUS 68
> -#define CLK_PWM7_BUS 69
> -#define CLK_PWM8_BUS 70
> -#define CLK_PWM9_BUS 71
> -#define CLK_PWM10_BUS 72
> -#define CLK_PWM11_BUS 73
> -#define CLK_PWM12_BUS 74
> -#define CLK_PWM13_BUS 75
> -#define CLK_PWM14_BUS 76
> -#define CLK_PWM15_BUS 77
> -#define CLK_PWM16_BUS 78
> -#define CLK_PWM17_BUS 79
> -#define CLK_PWM18_BUS 80
> -#define CLK_PWM19_BUS 81
> -#define CLK_SSP3_BUS 82
> -#define CLK_RTC_BUS 83
> -#define CLK_TWSI0_BUS 84
> -#define CLK_TWSI1_BUS 85
> -#define CLK_TWSI2_BUS 86
> -#define CLK_TWSI4_BUS 87
> -#define CLK_TWSI5_BUS 88
> -#define CLK_TWSI6_BUS 89
> -#define CLK_TWSI7_BUS 90
> -#define CLK_TWSI8_BUS 91
> -#define CLK_TIMERS1_BUS 92
> -#define CLK_TIMERS2_BUS 93
> -#define CLK_AIB_BUS 94
> -#define CLK_ONEWIRE_BUS 95
> -#define CLK_SSPA0_BUS 96
> -#define CLK_SSPA1_BUS 97
> -#define CLK_TSEN_BUS 98
> -#define CLK_IPC_AP2AUD_BUS 99
> +#define CLK_SSPA0_I2S_BCLK 44
> +#define CLK_SSPA1_I2S_BCLK 45
just append the clock at the end, instead of doing massive renaming
> +#define CLK_SSPA0 46
> +#define CLK_SSPA1 47
> +#define CLK_DRO 48
> +#define CLK_IR 49
> +#define CLK_TSEN 50
> +#define CLK_IPC_AP2AUD 51
> +#define CLK_CAN0 52
> +#define CLK_CAN0_BUS 53
> +#define CLK_UART0_BUS 54
> +#define CLK_UART2_BUS 55
> +#define CLK_UART3_BUS 56
> +#define CLK_UART4_BUS 57
> +#define CLK_UART5_BUS 58
> +#define CLK_UART6_BUS 59
> +#define CLK_UART7_BUS 60
> +#define CLK_UART8_BUS 61
> +#define CLK_UART9_BUS 62
> +#define CLK_GPIO_BUS 63
> +#define CLK_PWM0_BUS 64
> +#define CLK_PWM1_BUS 65
> +#define CLK_PWM2_BUS 66
> +#define CLK_PWM3_BUS 67
> +#define CLK_PWM4_BUS 68
> +#define CLK_PWM5_BUS 69
> +#define CLK_PWM6_BUS 70
> +#define CLK_PWM7_BUS 71
> +#define CLK_PWM8_BUS 72
> +#define CLK_PWM9_BUS 73
> +#define CLK_PWM10_BUS 74
> +#define CLK_PWM11_BUS 75
> +#define CLK_PWM12_BUS 76
> +#define CLK_PWM13_BUS 77
> +#define CLK_PWM14_BUS 78
> +#define CLK_PWM15_BUS 79
> +#define CLK_PWM16_BUS 80
> +#define CLK_PWM17_BUS 81
> +#define CLK_PWM18_BUS 82
> +#define CLK_PWM19_BUS 83
> +#define CLK_SSP3_BUS 84
> +#define CLK_RTC_BUS 85
> +#define CLK_TWSI0_BUS 86
> +#define CLK_TWSI1_BUS 87
> +#define CLK_TWSI2_BUS 88
> +#define CLK_TWSI4_BUS 89
> +#define CLK_TWSI5_BUS 90
> +#define CLK_TWSI6_BUS 91
> +#define CLK_TWSI7_BUS 92
> +#define CLK_TWSI8_BUS 93
> +#define CLK_TIMERS1_BUS 94
> +#define CLK_TIMERS2_BUS 95
> +#define CLK_AIB_BUS 96
> +#define CLK_ONEWIRE_BUS 97
> +#define CLK_SSPA0_BUS 98
> +#define CLK_SSPA1_BUS 99
> +#define CLK_TSEN_BUS 100
> +#define CLK_IPC_AP2AUD_BUS 101
>
> /* APMU clocks */
> #define CLK_CCI550 0
>
> --
> 2.50.1
>
--
Yixun Lan (dlan)
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 2/2] dt-bindings: clock: spacemit: CLK_SSPA_I2S_BCLK for SSPA
2025-07-22 9:21 ` Yixun Lan
@ 2025-07-22 9:27 ` Troy Mitchell
2025-07-22 10:09 ` Yao Zi
0 siblings, 1 reply; 8+ messages in thread
From: Troy Mitchell @ 2025-07-22 9:27 UTC (permalink / raw)
To: Yixun Lan
Cc: Troy Mitchell, Michael Turquette, Stephen Boyd, Alex Elder,
Haylen Chu, Inochi Amaoto, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-clk, linux-riscv, spacemit, linux-kernel,
devicetree
On Tue, Jul 22, 2025 at 05:21:01PM +0800, Yixun Lan wrote:
> Hi Troy,
>
> On 15:36 Tue 22 Jul , Troy Mitchell wrote:
> > This patch adds macro definitions: SSPAx_I2S_BCLK,
> this is obvious, so no need to repeat, please add something useful
>
> > to introduce a dummy gate for i2s_bclk.
> ~~~~~~ 'virtual'? if it isn't a real gate clock,
> but I'm not sure it's a good approach to introduce such
> virtual clock if underlying hw doesn't comply with this
I'll leave this question to others.
>
> >
> > Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
> > ---
> > include/dt-bindings/clock/spacemit,k1-syscon.h | 114 +++++++++++++------------
> > 1 file changed, 58 insertions(+), 56 deletions(-)
> dt-binding patch should always go first
get it
>
> >
> > diff --git a/include/dt-bindings/clock/spacemit,k1-syscon.h b/include/dt-bindings/clock/spacemit,k1-syscon.h
> > index 35968ae98246609c889eb4a7d08b4ff7360de53b..6914ccf5be45a1071d5b6eac354cacb67888e00c 100644
> > --- a/include/dt-bindings/clock/spacemit,k1-syscon.h
> > +++ b/include/dt-bindings/clock/spacemit,k1-syscon.h
> > @@ -123,62 +123,64 @@
> > #define CLK_TIMERS2 41
> > #define CLK_AIB 42
> > #define CLK_ONEWIRE 43
> > -#define CLK_SSPA0 44
> > -#define CLK_SSPA1 45
> > -#define CLK_DRO 46
> > -#define CLK_IR 47
> > -#define CLK_TSEN 48
> > -#define CLK_IPC_AP2AUD 49
> > -#define CLK_CAN0 50
> > -#define CLK_CAN0_BUS 51
> > -#define CLK_UART0_BUS 52
> > -#define CLK_UART2_BUS 53
> > -#define CLK_UART3_BUS 54
> > -#define CLK_UART4_BUS 55
> > -#define CLK_UART5_BUS 56
> > -#define CLK_UART6_BUS 57
> > -#define CLK_UART7_BUS 58
> > -#define CLK_UART8_BUS 59
> > -#define CLK_UART9_BUS 60
> > -#define CLK_GPIO_BUS 61
> > -#define CLK_PWM0_BUS 62
> > -#define CLK_PWM1_BUS 63
> > -#define CLK_PWM2_BUS 64
> > -#define CLK_PWM3_BUS 65
> > -#define CLK_PWM4_BUS 66
> > -#define CLK_PWM5_BUS 67
> > -#define CLK_PWM6_BUS 68
> > -#define CLK_PWM7_BUS 69
> > -#define CLK_PWM8_BUS 70
> > -#define CLK_PWM9_BUS 71
> > -#define CLK_PWM10_BUS 72
> > -#define CLK_PWM11_BUS 73
> > -#define CLK_PWM12_BUS 74
> > -#define CLK_PWM13_BUS 75
> > -#define CLK_PWM14_BUS 76
> > -#define CLK_PWM15_BUS 77
> > -#define CLK_PWM16_BUS 78
> > -#define CLK_PWM17_BUS 79
> > -#define CLK_PWM18_BUS 80
> > -#define CLK_PWM19_BUS 81
> > -#define CLK_SSP3_BUS 82
> > -#define CLK_RTC_BUS 83
> > -#define CLK_TWSI0_BUS 84
> > -#define CLK_TWSI1_BUS 85
> > -#define CLK_TWSI2_BUS 86
> > -#define CLK_TWSI4_BUS 87
> > -#define CLK_TWSI5_BUS 88
> > -#define CLK_TWSI6_BUS 89
> > -#define CLK_TWSI7_BUS 90
> > -#define CLK_TWSI8_BUS 91
> > -#define CLK_TIMERS1_BUS 92
> > -#define CLK_TIMERS2_BUS 93
> > -#define CLK_AIB_BUS 94
> > -#define CLK_ONEWIRE_BUS 95
> > -#define CLK_SSPA0_BUS 96
> > -#define CLK_SSPA1_BUS 97
> > -#define CLK_TSEN_BUS 98
> > -#define CLK_IPC_AP2AUD_BUS 99
> > +#define CLK_SSPA0_I2S_BCLK 44
> > +#define CLK_SSPA1_I2S_BCLK 45
> just append the clock at the end, instead of doing massive renaming
The c file is written in the same order as the h file,
and I don't want to disrupt this order..
So should I keep this style or just append at the end?
- Troy
>
> > +#define CLK_SSPA0 46
> > +#define CLK_SSPA1 47
> > +#define CLK_DRO 48
> > +#define CLK_IR 49
> > +#define CLK_TSEN 50
> > +#define CLK_IPC_AP2AUD 51
> > +#define CLK_CAN0 52
> > +#define CLK_CAN0_BUS 53
> > +#define CLK_UART0_BUS 54
> > +#define CLK_UART2_BUS 55
> > +#define CLK_UART3_BUS 56
> > +#define CLK_UART4_BUS 57
> > +#define CLK_UART5_BUS 58
> > +#define CLK_UART6_BUS 59
> > +#define CLK_UART7_BUS 60
> > +#define CLK_UART8_BUS 61
> > +#define CLK_UART9_BUS 62
> > +#define CLK_GPIO_BUS 63
> > +#define CLK_PWM0_BUS 64
> > +#define CLK_PWM1_BUS 65
> > +#define CLK_PWM2_BUS 66
> > +#define CLK_PWM3_BUS 67
> > +#define CLK_PWM4_BUS 68
> > +#define CLK_PWM5_BUS 69
> > +#define CLK_PWM6_BUS 70
> > +#define CLK_PWM7_BUS 71
> > +#define CLK_PWM8_BUS 72
> > +#define CLK_PWM9_BUS 73
> > +#define CLK_PWM10_BUS 74
> > +#define CLK_PWM11_BUS 75
> > +#define CLK_PWM12_BUS 76
> > +#define CLK_PWM13_BUS 77
> > +#define CLK_PWM14_BUS 78
> > +#define CLK_PWM15_BUS 79
> > +#define CLK_PWM16_BUS 80
> > +#define CLK_PWM17_BUS 81
> > +#define CLK_PWM18_BUS 82
> > +#define CLK_PWM19_BUS 83
> > +#define CLK_SSP3_BUS 84
> > +#define CLK_RTC_BUS 85
> > +#define CLK_TWSI0_BUS 86
> > +#define CLK_TWSI1_BUS 87
> > +#define CLK_TWSI2_BUS 88
> > +#define CLK_TWSI4_BUS 89
> > +#define CLK_TWSI5_BUS 90
> > +#define CLK_TWSI6_BUS 91
> > +#define CLK_TWSI7_BUS 92
> > +#define CLK_TWSI8_BUS 93
> > +#define CLK_TIMERS1_BUS 94
> > +#define CLK_TIMERS2_BUS 95
> > +#define CLK_AIB_BUS 96
> > +#define CLK_ONEWIRE_BUS 97
> > +#define CLK_SSPA0_BUS 98
> > +#define CLK_SSPA1_BUS 99
> > +#define CLK_TSEN_BUS 100
> > +#define CLK_IPC_AP2AUD_BUS 101
> >
> > /* APMU clocks */
> > #define CLK_CCI550 0
> >
> > --
> > 2.50.1
> >
>
> --
> Yixun Lan (dlan)
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 2/2] dt-bindings: clock: spacemit: CLK_SSPA_I2S_BCLK for SSPA
2025-07-22 9:27 ` Troy Mitchell
@ 2025-07-22 10:09 ` Yao Zi
2025-07-23 2:31 ` Troy Mitchell
0 siblings, 1 reply; 8+ messages in thread
From: Yao Zi @ 2025-07-22 10:09 UTC (permalink / raw)
To: Troy Mitchell, Yixun Lan
Cc: Michael Turquette, Stephen Boyd, Alex Elder, Haylen Chu,
Inochi Amaoto, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-clk, linux-riscv, spacemit, linux-kernel, devicetree
On Tue, Jul 22, 2025 at 05:27:11PM +0800, Troy Mitchell wrote:
> On Tue, Jul 22, 2025 at 05:21:01PM +0800, Yixun Lan wrote:
> > Hi Troy,
> >
> > On 15:36 Tue 22 Jul , Troy Mitchell wrote:
> > > This patch adds macro definitions: SSPAx_I2S_BCLK,
> > this is obvious, so no need to repeat, please add something useful
> >
> > > to introduce a dummy gate for i2s_bclk.
> > ~~~~~~ 'virtual'? if it isn't a real gate clock,
> > but I'm not sure it's a good approach to introduce such
> > virtual clock if underlying hw doesn't comply with this
> I'll leave this question to others.
>
> >
> > >
> > > Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
> > > ---
> > > include/dt-bindings/clock/spacemit,k1-syscon.h | 114 +++++++++++++------------
> > > 1 file changed, 58 insertions(+), 56 deletions(-)
> > dt-binding patch should always go first
> get it
>
> >
> > >
> > > diff --git a/include/dt-bindings/clock/spacemit,k1-syscon.h b/include/dt-bindings/clock/spacemit,k1-syscon.h
> > > index 35968ae98246609c889eb4a7d08b4ff7360de53b..6914ccf5be45a1071d5b6eac354cacb67888e00c 100644
> > > --- a/include/dt-bindings/clock/spacemit,k1-syscon.h
> > > +++ b/include/dt-bindings/clock/spacemit,k1-syscon.h
> > > @@ -123,62 +123,64 @@
> > > #define CLK_TIMERS2 41
> > > #define CLK_AIB 42
> > > #define CLK_ONEWIRE 43
> > > -#define CLK_SSPA0 44
> > > -#define CLK_SSPA1 45
> > > -#define CLK_DRO 46
> > > -#define CLK_IR 47
> > > -#define CLK_TSEN 48
> > > -#define CLK_IPC_AP2AUD 49
> > > -#define CLK_CAN0 50
> > > -#define CLK_CAN0_BUS 51
> > > -#define CLK_UART0_BUS 52
> > > -#define CLK_UART2_BUS 53
> > > -#define CLK_UART3_BUS 54
> > > -#define CLK_UART4_BUS 55
> > > -#define CLK_UART5_BUS 56
> > > -#define CLK_UART6_BUS 57
> > > -#define CLK_UART7_BUS 58
> > > -#define CLK_UART8_BUS 59
> > > -#define CLK_UART9_BUS 60
> > > -#define CLK_GPIO_BUS 61
> > > -#define CLK_PWM0_BUS 62
> > > -#define CLK_PWM1_BUS 63
> > > -#define CLK_PWM2_BUS 64
> > > -#define CLK_PWM3_BUS 65
> > > -#define CLK_PWM4_BUS 66
> > > -#define CLK_PWM5_BUS 67
> > > -#define CLK_PWM6_BUS 68
> > > -#define CLK_PWM7_BUS 69
> > > -#define CLK_PWM8_BUS 70
> > > -#define CLK_PWM9_BUS 71
> > > -#define CLK_PWM10_BUS 72
> > > -#define CLK_PWM11_BUS 73
> > > -#define CLK_PWM12_BUS 74
> > > -#define CLK_PWM13_BUS 75
> > > -#define CLK_PWM14_BUS 76
> > > -#define CLK_PWM15_BUS 77
> > > -#define CLK_PWM16_BUS 78
> > > -#define CLK_PWM17_BUS 79
> > > -#define CLK_PWM18_BUS 80
> > > -#define CLK_PWM19_BUS 81
> > > -#define CLK_SSP3_BUS 82
> > > -#define CLK_RTC_BUS 83
> > > -#define CLK_TWSI0_BUS 84
> > > -#define CLK_TWSI1_BUS 85
> > > -#define CLK_TWSI2_BUS 86
> > > -#define CLK_TWSI4_BUS 87
> > > -#define CLK_TWSI5_BUS 88
> > > -#define CLK_TWSI6_BUS 89
> > > -#define CLK_TWSI7_BUS 90
> > > -#define CLK_TWSI8_BUS 91
> > > -#define CLK_TIMERS1_BUS 92
> > > -#define CLK_TIMERS2_BUS 93
> > > -#define CLK_AIB_BUS 94
> > > -#define CLK_ONEWIRE_BUS 95
> > > -#define CLK_SSPA0_BUS 96
> > > -#define CLK_SSPA1_BUS 97
> > > -#define CLK_TSEN_BUS 98
> > > -#define CLK_IPC_AP2AUD_BUS 99
> > > +#define CLK_SSPA0_I2S_BCLK 44
> > > +#define CLK_SSPA1_I2S_BCLK 45
> > just append the clock at the end, instead of doing massive renaming
> The c file is written in the same order as the h file,
> and I don't want to disrupt this order..
>
> So should I keep this style or just append at the end?
This isn't only a style issue. This patch breaks devicetree ABI, old
devicetree won't work with the change. Please don't modify existing
definitions but only add new ones.
> - Troy
> >
> > > +#define CLK_SSPA0 46
> > > +#define CLK_SSPA1 47
> > > +#define CLK_DRO 48
Regards,
Yao Zi
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 2/2] dt-bindings: clock: spacemit: CLK_SSPA_I2S_BCLK for SSPA
2025-07-22 10:09 ` Yao Zi
@ 2025-07-23 2:31 ` Troy Mitchell
0 siblings, 0 replies; 8+ messages in thread
From: Troy Mitchell @ 2025-07-23 2:31 UTC (permalink / raw)
To: Yao Zi
Cc: Troy Mitchell, Yixun Lan, Michael Turquette, Stephen Boyd,
Alex Elder, Haylen Chu, Inochi Amaoto, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-clk, linux-riscv,
spacemit, linux-kernel, devicetree
On Tue, Jul 22, 2025 at 10:09:23AM +0000, Yao Zi wrote:
> On Tue, Jul 22, 2025 at 05:27:11PM +0800, Troy Mitchell wrote:
> > On Tue, Jul 22, 2025 at 05:21:01PM +0800, Yixun Lan wrote:
> > > Hi Troy,
> > >
> > > On 15:36 Tue 22 Jul , Troy Mitchell wrote:
> > > > This patch adds macro definitions: SSPAx_I2S_BCLK,
> > > this is obvious, so no need to repeat, please add something useful
> > >
> > > > to introduce a dummy gate for i2s_bclk.
> > > ~~~~~~ 'virtual'? if it isn't a real gate clock,
> > > but I'm not sure it's a good approach to introduce such
> > > virtual clock if underlying hw doesn't comply with this
> > I'll leave this question to others.
> >
> > >
> > > >
> > > > Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
> > > > ---
> > > > include/dt-bindings/clock/spacemit,k1-syscon.h | 114 +++++++++++++------------
> > > > 1 file changed, 58 insertions(+), 56 deletions(-)
> > > dt-binding patch should always go first
> > get it
> >
> > >
> > > >
> > > > diff --git a/include/dt-bindings/clock/spacemit,k1-syscon.h b/include/dt-bindings/clock/spacemit,k1-syscon.h
> > > > index 35968ae98246609c889eb4a7d08b4ff7360de53b..6914ccf5be45a1071d5b6eac354cacb67888e00c 100644
> > > > --- a/include/dt-bindings/clock/spacemit,k1-syscon.h
> > > > +++ b/include/dt-bindings/clock/spacemit,k1-syscon.h
> > > > @@ -123,62 +123,64 @@
> > > > #define CLK_TIMERS2 41
> > > > #define CLK_AIB 42
> > > > #define CLK_ONEWIRE 43
> > > > -#define CLK_SSPA0 44
> > > > -#define CLK_SSPA1 45
> > > > -#define CLK_DRO 46
> > > > -#define CLK_IR 47
> > > > -#define CLK_TSEN 48
> > > > -#define CLK_IPC_AP2AUD 49
> > > > -#define CLK_CAN0 50
> > > > -#define CLK_CAN0_BUS 51
> > > > -#define CLK_UART0_BUS 52
> > > > -#define CLK_UART2_BUS 53
> > > > -#define CLK_UART3_BUS 54
> > > > -#define CLK_UART4_BUS 55
> > > > -#define CLK_UART5_BUS 56
> > > > -#define CLK_UART6_BUS 57
> > > > -#define CLK_UART7_BUS 58
> > > > -#define CLK_UART8_BUS 59
> > > > -#define CLK_UART9_BUS 60
> > > > -#define CLK_GPIO_BUS 61
> > > > -#define CLK_PWM0_BUS 62
> > > > -#define CLK_PWM1_BUS 63
> > > > -#define CLK_PWM2_BUS 64
> > > > -#define CLK_PWM3_BUS 65
> > > > -#define CLK_PWM4_BUS 66
> > > > -#define CLK_PWM5_BUS 67
> > > > -#define CLK_PWM6_BUS 68
> > > > -#define CLK_PWM7_BUS 69
> > > > -#define CLK_PWM8_BUS 70
> > > > -#define CLK_PWM9_BUS 71
> > > > -#define CLK_PWM10_BUS 72
> > > > -#define CLK_PWM11_BUS 73
> > > > -#define CLK_PWM12_BUS 74
> > > > -#define CLK_PWM13_BUS 75
> > > > -#define CLK_PWM14_BUS 76
> > > > -#define CLK_PWM15_BUS 77
> > > > -#define CLK_PWM16_BUS 78
> > > > -#define CLK_PWM17_BUS 79
> > > > -#define CLK_PWM18_BUS 80
> > > > -#define CLK_PWM19_BUS 81
> > > > -#define CLK_SSP3_BUS 82
> > > > -#define CLK_RTC_BUS 83
> > > > -#define CLK_TWSI0_BUS 84
> > > > -#define CLK_TWSI1_BUS 85
> > > > -#define CLK_TWSI2_BUS 86
> > > > -#define CLK_TWSI4_BUS 87
> > > > -#define CLK_TWSI5_BUS 88
> > > > -#define CLK_TWSI6_BUS 89
> > > > -#define CLK_TWSI7_BUS 90
> > > > -#define CLK_TWSI8_BUS 91
> > > > -#define CLK_TIMERS1_BUS 92
> > > > -#define CLK_TIMERS2_BUS 93
> > > > -#define CLK_AIB_BUS 94
> > > > -#define CLK_ONEWIRE_BUS 95
> > > > -#define CLK_SSPA0_BUS 96
> > > > -#define CLK_SSPA1_BUS 97
> > > > -#define CLK_TSEN_BUS 98
> > > > -#define CLK_IPC_AP2AUD_BUS 99
> > > > +#define CLK_SSPA0_I2S_BCLK 44
> > > > +#define CLK_SSPA1_I2S_BCLK 45
> > > just append the clock at the end, instead of doing massive renaming
> > The c file is written in the same order as the h file,
> > and I don't want to disrupt this order..
> >
> > So should I keep this style or just append at the end?
>
> This isn't only a style issue. This patch breaks devicetree ABI, old
> devicetree won't work with the change. Please don't modify existing
> definitions but only add new ones.
Tnx!
And if I append it at the end, should I also need to change the current c file?
>
> > - Troy
> > >
> > > > +#define CLK_SSPA0 46
> > > > +#define CLK_SSPA1 47
> > > > +#define CLK_DRO 48
>
> Regards,
> Yao Zi
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 2/2] dt-bindings: clock: spacemit: CLK_SSPA_I2S_BCLK for SSPA
2025-07-22 7:36 ` [PATCH v2 2/2] dt-bindings: clock: spacemit: CLK_SSPA_I2S_BCLK for SSPA Troy Mitchell
2025-07-22 9:21 ` Yixun Lan
@ 2025-07-23 4:41 ` Rob Herring
1 sibling, 0 replies; 8+ messages in thread
From: Rob Herring @ 2025-07-23 4:41 UTC (permalink / raw)
To: Troy Mitchell
Cc: Michael Turquette, Stephen Boyd, Yixun Lan, Alex Elder,
Haylen Chu, Inochi Amaoto, Krzysztof Kozlowski, Conor Dooley,
linux-clk, linux-riscv, spacemit, linux-kernel, devicetree
On Tue, Jul 22, 2025 at 03:36:31PM +0800, Troy Mitchell wrote:
> This patch adds macro definitions: SSPAx_I2S_BCLK,
> to introduce a dummy gate for i2s_bclk.
>
> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
> ---
> include/dt-bindings/clock/spacemit,k1-syscon.h | 114 +++++++++++++------------
> 1 file changed, 58 insertions(+), 56 deletions(-)
>
> diff --git a/include/dt-bindings/clock/spacemit,k1-syscon.h b/include/dt-bindings/clock/spacemit,k1-syscon.h
> index 35968ae98246609c889eb4a7d08b4ff7360de53b..6914ccf5be45a1071d5b6eac354cacb67888e00c 100644
> --- a/include/dt-bindings/clock/spacemit,k1-syscon.h
> +++ b/include/dt-bindings/clock/spacemit,k1-syscon.h
> @@ -123,62 +123,64 @@
> #define CLK_TIMERS2 41
> #define CLK_AIB 42
> #define CLK_ONEWIRE 43
> -#define CLK_SSPA0 44
> -#define CLK_SSPA1 45
> +#define CLK_SSPA0 46
> +#define CLK_SSPA1 47
Uh, no. You can't re-number things. This is an ABI and you just broke
it.
Rob
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2025-07-23 4:41 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-07-22 7:36 [PATCH v2 0/2] clk: spacemit: fix sspax_clk Troy Mitchell
2025-07-22 7:36 ` [PATCH v2 1/2] " Troy Mitchell
2025-07-22 7:36 ` [PATCH v2 2/2] dt-bindings: clock: spacemit: CLK_SSPA_I2S_BCLK for SSPA Troy Mitchell
2025-07-22 9:21 ` Yixun Lan
2025-07-22 9:27 ` Troy Mitchell
2025-07-22 10:09 ` Yao Zi
2025-07-23 2:31 ` Troy Mitchell
2025-07-23 4:41 ` Rob Herring
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).