From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5A7C2E5414; Fri, 25 Jul 2025 10:07:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753438047; cv=none; b=WDFk+dl1BdzU4mjlnVtM3j9+V6b5//KpO7O8GMWTl8yQtRcRV6dB3jaNS0ZFqLaDoZddTeq/ICxn36PRCsosrY5MWGEfZ99FgleoxZHBjZhWdraDt7I6BT+YgSW68Zi8KZpKaTVf5S4O94T7Z0zG4w6XqnmE7Bo2OZlAjveU058= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753438047; c=relaxed/simple; bh=q/3aULXkGU6hhZbuLWZNXXcuWu9GN4L9i3k2rru9NjA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=rbCD+w7HqSREyehtLFPOsVZl+Hwm0DcuR8y8lyQBLK9Sz/VTB2WSRnKYzZoQpKIfMf7FM/wUV9cg8jKPw7bKZG1joIKEPBZsSle+iGZ29u9MIeHh1sV/dHwLvon0vszIg8Fg9Zra4iVmhxoVJ10oFQSZkLaIyiAJ/QxOFmmOZqw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=OSoXrK0i; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="OSoXrK0i" Received: from pps.filterd (m0369458.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56P9cSdh007814; Fri, 25 Jul 2025 12:07:08 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= a5/bUBAcTHA5SdieGqpRNiqi2E15Aab+zmlB1Dy9Q40=; b=OSoXrK0idm941G5W sOIF943zL9Je+mlt2Rzt6vLREo7pe+cb+voOcLPSn0cyQ2+y69MFAeTlECBZ8AWE s26OraJ3Iqu6QIzSGvepRou/VGNAGYbtT4neEWeizSlStoKFH/QNRxtizKyTIYbX tXL5yieJwK718P03oNsGoWCOFuLQCRA+u9J1T2gJcyTKEkvXSopsvZ2w8j/s8iXV +rTaiGRQenJPUn6hQjkqTS5CqIEjLIT9WsLis06GMWb3ASBt+ais//iKBZfrWy9G ZQQNIXBsTzSvHSgR2ugSatSzUnMBwObS5J9anTw2yPi6zT6TmBuYQf6Aa333N9m4 YP3FUA== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 483w3m2hdp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Jul 2025 12:07:08 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 4561540058; Fri, 25 Jul 2025 12:05:37 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id D32BA7A19C6; Fri, 25 Jul 2025 12:04:32 +0200 (CEST) Received: from localhost (10.252.19.90) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 25 Jul 2025 12:04:32 +0200 From: Raphael Gallais-Pou Date: Fri, 25 Jul 2025 12:03:59 +0200 Subject: [PATCH 07/12] drm/stm: ltdc: handle lvds pixel clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20250725-drm-misc-next-v1-7-a59848e62cf9@foss.st.com> References: <20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com> In-Reply-To: <20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 From: Yannick Fertre Handle LVDS pixel clock. The LTDC operates with multiple clock domains for register access, requiring all clocks to be provided during read/write operations. This imposes a dependency between the LVDS and LTDC to access correctly all LTDC registers. And because both IPs' pixel rates must be synchronized, the LTDC has to handle the LVDS clock. Signed-off-by: Yannick Fertre Signed-off-by: Raphael Gallais-Pou --- drivers/gpu/drm/stm/ltdc.c | 22 +++++++++++++++++++++- drivers/gpu/drm/stm/ltdc.h | 1 + 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index 2bcdef76af2e8cbe3b6030deccefa097f28adc3a..031c561b8e780a55b77f4a4c8338e74b52bbbb48 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -837,6 +837,12 @@ ltdc_crtc_mode_valid(struct drm_crtc *crtc, int target_max = target + CLK_TOLERANCE_HZ; int result; + if (ldev->lvds_clk) { + result = clk_round_rate(ldev->lvds_clk, target); + drm_dbg_driver(crtc->dev, "lvds pixclk rate target %d, available %d\n", + target, result); + } + result = clk_round_rate(ldev->pixel_clk, target); DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result); @@ -1878,6 +1884,8 @@ void ltdc_suspend(struct drm_device *ddev) clk_disable_unprepare(ldev->pixel_clk); if (ldev->bus_clk) clk_disable_unprepare(ldev->bus_clk); + if (ldev->lvds_clk) + clk_disable_unprepare(ldev->lvds_clk); } int ltdc_resume(struct drm_device *ddev) @@ -1895,8 +1903,16 @@ int ltdc_resume(struct drm_device *ddev) if (ldev->bus_clk) { ret = clk_prepare_enable(ldev->bus_clk); - if (ret) + if (ret) { drm_err(ddev, "failed to enable bus clock (%d)\n", ret); + return ret; + } + } + + if (ldev->lvds_clk) { + ret = clk_prepare_enable(ldev->lvds_clk); + if (ret) + drm_err(ddev, "failed to prepare lvds clock\n"); } return ret; @@ -1980,6 +1996,10 @@ int ltdc_load(struct drm_device *ddev) } } + ldev->lvds_clk = devm_clk_get(dev, "lvds"); + if (IS_ERR(ldev->lvds_clk)) + ldev->lvds_clk = NULL; + rstc = devm_reset_control_get_exclusive(dev, NULL); mutex_init(&ldev->err_lock); diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h index ddfa8ae61a7ba5dc446fae647562d0ec8e6953e1..17b51a7ce28eee5de6d24ca943ca3b1f48695dfd 100644 --- a/drivers/gpu/drm/stm/ltdc.h +++ b/drivers/gpu/drm/stm/ltdc.h @@ -48,6 +48,7 @@ struct ltdc_device { void __iomem *regs; struct regmap *regmap; struct clk *pixel_clk; /* lcd pixel clock */ + struct clk *lvds_clk; /* lvds pixel clock */ struct clk *bus_clk; /* bus clock */ struct mutex err_lock; /* protecting error_status */ struct ltdc_caps caps; -- 2.25.1