From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A4932E5B3F; Fri, 25 Jul 2025 10:07:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753438052; cv=none; b=IqXv7RdwSgcMkFkhm4q9RlwDgNnNKNco7exa1m6zSHErA6uqRC48fnlVJ1qkQUkJA+ZXDV69vpsiFlBHAZVjhZ5j8fffqBWfreiL3WVXWQ4LB4sWQsKz4bhr67SUME6SNNGRO64uZzZ5jDC8hFgXwiAXeAx2DzLPO15ZQdowNsc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753438052; c=relaxed/simple; bh=gMxr6Ge/SNR6QhDQ96+1JrZCqTWI7fRZ6tSHO7GQ8FE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=DinshFIlL8nBSD3f9YNFYZiJQvXkpYprP/Kzsl/bLM5jvruJRWG4VT4eUdoVISeSx+Q6pJsZA3H7j8UriDtidjfqsomeW3feqCs/T4pHSJpj2YFjK+nGWVuJwvqhV0sV/oteHd8z0GNvwAvTdpkQOrm9TkLlepwH0+iMHKBI8qQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=cGEBDXBo; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="cGEBDXBo" Received: from pps.filterd (m0369458.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56P8Rxmg010432; Fri, 25 Jul 2025 12:07:13 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= OeQA3LfMAAXViAVsAHZjFk5rcaqSif2z15EtCoo6Cew=; b=cGEBDXBowdU1fgTW jjnfqPnkqHWA52Gv1UoLm0iyRqmRywA1nXfCpjxmAfAYe/vNgMB15GbTooewVR/F ZzBS1+S/R9+Vd0MwaLnd8x+OUuaP7SQVU9yzFrcC8uvbDcOYIaLBUECONvyFJK+d uf/3uNp2mRAFFSKTQJaA4/rfZLYFcQNhOLAzOgtNYb80CKzc8WFJXdX20qf2uYKk tCsIFH48bS3Tdpnq3n9y8yM5j8HRQC1g1RIQIIzgEROf+SPLtW4aoeuuD9ilqgzV c+kvzuqntR5r0/nTiJhn94lbU8huNMvxryw5g+CoDtPBEtAbkwp7D7TCkgR+YneV I6R/Uw== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 483w3m2he0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 25 Jul 2025 12:07:13 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 4828040059; Fri, 25 Jul 2025 12:05:37 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id CF8377A19CA; Fri, 25 Jul 2025 12:04:33 +0200 (CEST) Received: from localhost (10.252.19.90) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 25 Jul 2025 12:04:33 +0200 From: Raphael Gallais-Pou Date: Fri, 25 Jul 2025 12:04:00 +0200 Subject: [PATCH 08/12] arm64: dts: st: add ltdc support on stm32mp251 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20250725-drm-misc-next-v1-8-a59848e62cf9@foss.st.com> References: <20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com> In-Reply-To: <20250725-drm-misc-next-v1-0-a59848e62cf9@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-25_02,2025-07-24_01,2025-03-28_01 The LCD-TFT Display Controller (LTDC) handles display composition, scaling and rotation. It provides a parallel digital RGB flow to be used by display interfaces. Add the LTDC node. Signed-off-by: Raphael Gallais-Pou --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 8d87865850a7a6e8095c36acdef83c8e3a73ae54..9698170547c13ca17f032dd714dd4d7290a9b0e2 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1052,6 +1052,18 @@ dcmipp: dcmipp@48030000 { status = "disabled"; }; + ltdc: display-controller@48010000 { + compatible = "st,stm32mp25-ltdc"; + reg = <0x48010000 0x400>; + interrupts = , + ; + clocks = <&rcc CK_BUS_LTDC>, <&rcc CK_KER_LTDC>; + clock-names = "bus", "lcd"; + resets = <&rcc LTDC_R>; + access-controllers = <&rifsc 80>; + status = "disabled"; + }; + combophy: phy@480c0000 { compatible = "st,stm32mp25-combophy"; reg = <0x480c0000 0x1000>; -- 2.25.1