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From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: <linux-coco@lists.linux.dev>, <linux-pci@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <bhelgaas@google.com>,
	<aik@amd.com>, <lukas@wunner.de>
Subject: Re: [PATCH v4 09/10] PCI/TSM: Report active IDE streams
Date: Tue, 29 Jul 2025 16:58:53 +0100	[thread overview]
Message-ID: <20250729165853.00007b3d@huawei.com> (raw)
In-Reply-To: <20250717183358.1332417-10-dan.j.williams@intel.com>

On Thu, 17 Jul 2025 11:33:57 -0700
Dan Williams <dan.j.williams@intel.com> wrote:

> Given that the platform TSM owns IDE Stream ID allocation, report the
> active streams via the TSM class device. Establish a symlink from the
> class device to the PCI endpoint device consuming the stream, named by
> the Stream ID.
> 
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Trivial stuff only
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>

> ---
>  Documentation/ABI/testing/sysfs-class-tsm | 10 ++++++++
>  drivers/pci/ide.c                         |  4 ++++
>  drivers/virt/coco/tsm-core.c              | 28 +++++++++++++++++++++++
>  include/linux/pci-ide.h                   |  2 ++
>  include/linux/tsm.h                       |  4 ++++
>  5 files changed, 48 insertions(+)
> 
> diff --git a/Documentation/ABI/testing/sysfs-class-tsm b/Documentation/ABI/testing/sysfs-class-tsm
> index 2949468deaf7..6fc1a5ac6da1 100644
> --- a/Documentation/ABI/testing/sysfs-class-tsm
> +++ b/Documentation/ABI/testing/sysfs-class-tsm
> @@ -7,3 +7,13 @@ Description:
>  		signals when the PCI layer is able to support establishment of
>  		link encryption and other device-security features coordinated
>  		through a platform tsm.
> +
> +What:		/sys/class/tsm/tsmN/streamH.R.E
> +Contact:	linux-pci@vger.kernel.org
> +Description:
> +		(RO) When a host bridge has established a secure connection via
> +		the platform TSM, symlink appears. The primary function of this
> +		is have a system global review of TSM resource consumption
> +		across host bridges. The link points to the endpoint PCI device
> +		and matches the same link published by the host bridge. See
> +		Documentation/ABI/testing/sysfs-devices-pci-host-bridge.

> diff --git a/drivers/virt/coco/tsm-core.c b/drivers/virt/coco/tsm-core.c
> index 093824dc68dd..b0ef9089e0f2 100644
> --- a/drivers/virt/coco/tsm-core.c
> +++ b/drivers/virt/coco/tsm-core.c

> +/* must be invoked between tsm_register / tsm_unregister */
> +int tsm_ide_stream_register(struct pci_ide *ide)
> +{
> +	struct pci_dev *pdev = ide->pdev;
> +	struct pci_tsm *tsm = pdev->tsm;
> +	struct tsm_dev *tsm_dev = tsm->ops->owner;
> +	int rc;
> +
> +	rc = sysfs_create_link(&tsm_dev->dev.kobj, &pdev->dev.kobj,
> +			       ide->name);

Fits on one line under 80 chars (just)

> +	if (rc == 0)
> +		ide->tsm_dev = tsm_dev;

I'd prefer 

	if (rc)
		return rc;

	ide->tsm_dev = tsm_dev;

	return 0;

but don't care that much.

> +	return rc;
> +}
> +EXPORT_SYMBOL_GPL(tsm_ide_stream_register);
> +
> +void tsm_ide_stream_unregister(struct pci_ide *ide)
> +{
> +	struct tsm_dev *tsm_dev = ide->tsm_dev;
> +
> +	sysfs_remove_link(&tsm_dev->dev.kobj, ide->name);
> +	ide->tsm_dev = NULL;
> +}
> +EXPORT_SYMBOL_GPL(tsm_ide_stream_unregister);

> diff --git a/include/linux/tsm.h b/include/linux/tsm.h
> index ce95589a5d5b..4eba45a754ec 100644
> --- a/include/linux/tsm.h
> +++ b/include/linux/tsm.h
> @@ -120,4 +120,8 @@ const char *tsm_name(const struct tsm_dev *tsm_dev);
>  struct tsm_dev *find_tsm_dev(int id);
>  const struct pci_tsm_ops *tsm_pci_ops(const struct tsm_dev *tsm_dev);
>  const struct attribute_group *tsm_pci_group(const struct tsm_dev *tsm_dev);
> +struct pci_dev;

Not used.

> +struct pci_ide;
> +int tsm_ide_stream_register(struct pci_ide *ide);
> +void tsm_ide_stream_unregister(struct pci_ide *ide);
>  #endif /* __TSM_H */


  reply	other threads:[~2025-07-29 15:58 UTC|newest]

Thread overview: 70+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-17 18:33 [PATCH v4 00/10] PCI/TSM: Core infrastructure for PCI device security (TDISP) Dan Williams
2025-07-17 18:33 ` [PATCH v4 01/10] coco/tsm: Introduce a core device for TEE Security Managers Dan Williams
2025-07-29 11:28   ` Jonathan Cameron
2025-07-17 18:33 ` [PATCH v4 02/10] PCI/IDE: Enumerate Selective Stream IDE capabilities Dan Williams
2025-07-29 12:03   ` Jonathan Cameron
2025-08-05 20:59     ` dan.j.williams
2025-08-07 20:12   ` Bjorn Helgaas
2025-08-07 22:37     ` dan.j.williams
2025-08-07 22:53       ` Bjorn Helgaas
2025-08-08  2:17         ` dan.j.williams
2025-08-08 15:59           ` Bjorn Helgaas
2025-08-07 22:43   ` Bjorn Helgaas
2025-07-17 18:33 ` [PATCH v4 03/10] PCI: Introduce pci_walk_bus_reverse(), for_each_pci_dev_reverse() Dan Williams
2025-07-29 13:06   ` Jonathan Cameron
2025-08-05 23:52     ` dan.j.williams
2025-08-06 10:54       ` Jonathan Cameron
2025-08-07 20:24   ` Bjorn Helgaas
2025-08-07 23:17     ` dan.j.williams
2025-08-07 23:26       ` Bjorn Helgaas
2025-07-17 18:33 ` [PATCH v4 04/10] PCI/TSM: Authenticate devices via platform TSM Dan Williams
2025-07-29 14:56   ` Jonathan Cameron
2025-08-06  1:35     ` dan.j.williams
2025-08-06 11:10       ` Jonathan Cameron
2025-08-06 23:16         ` dan.j.williams
2025-08-07 10:42           ` Jonathan Cameron
2025-08-07  2:35         ` dan.j.williams
2025-08-05 15:53   ` Xu Yilun
2025-08-06 22:30     ` dan.j.williams
2025-08-07 21:27   ` Bjorn Helgaas
2025-08-08 22:51     ` dan.j.williams
2025-08-13  2:57   ` Alexey Kardashevskiy
2025-08-14  1:40     ` dan.j.williams
2025-08-14 14:52       ` Alexey Kardashevskiy
2025-08-18 21:08         ` dan.j.williams
2025-07-17 18:33 ` [PATCH v4 05/10] samples/devsec: Introduce a PCI device-security bus + endpoint sample Dan Williams
2025-07-29 15:16   ` Jonathan Cameron
2025-08-06  3:20     ` dan.j.williams
2025-08-06 11:16       ` Jonathan Cameron
2025-08-06 18:33         ` dan.j.williams
2025-08-11 13:18           ` Gerd Hoffmann
2025-08-11 20:47             ` dan.j.williams
2025-08-07 21:45   ` Bjorn Helgaas
2025-08-08 23:45     ` dan.j.williams
2025-07-17 18:33 ` [PATCH v4 06/10] PCI: Add PCIe Device 3 Extended Capability enumeration Dan Williams
2025-07-29 15:23   ` Jonathan Cameron
2025-08-06 21:00     ` dan.j.williams
2025-08-06 21:02     ` dan.j.williams
2025-08-07 22:06   ` Bjorn Helgaas
2025-08-09  0:05     ` dan.j.williams
2025-08-07 22:46   ` Bjorn Helgaas
2025-07-17 18:33 ` [PATCH v4 07/10] PCI/IDE: Add IDE establishment helpers Dan Williams
2025-07-29 15:45   ` Jonathan Cameron
2025-08-06 21:40     ` dan.j.williams
2025-08-07 22:38   ` Bjorn Helgaas
2025-08-09  1:52     ` dan.j.williams
2025-08-07 22:47   ` Bjorn Helgaas
2025-08-08 10:21   ` Arto Merilainen
2025-08-08 17:26     ` dan.j.williams
2025-08-11  8:02       ` Arto Merilainen
2025-08-28  8:19         ` Aneesh Kumar K.V
2025-07-17 18:33 ` [PATCH v4 08/10] PCI/IDE: Report available IDE streams Dan Williams
2025-07-29 15:47   ` Jonathan Cameron
2025-08-07 22:48   ` Bjorn Helgaas
2025-07-17 18:33 ` [PATCH v4 09/10] PCI/TSM: Report active " Dan Williams
2025-07-29 15:58   ` Jonathan Cameron [this message]
2025-08-06 21:55     ` dan.j.williams
2025-08-07 22:49   ` Bjorn Helgaas
2025-07-17 18:33 ` [PATCH v4 10/10] samples/devsec: Add sample IDE establishment Dan Williams
2025-07-29 16:06   ` Jonathan Cameron
2025-07-18 10:57 ` [PATCH v4 00/10] PCI/TSM: Core infrastructure for PCI device security (TDISP) Aneesh Kumar K.V

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