[PATCH v2 1/2] dt-bindings: usb: Add Eswin EIC7700 USB controller

[zhangsenchuan@eswincomputing.com]

From: Senchuan Zhang <zhangsenchuan@eswincomputing.com>

Add Device Tree binding documentation for the ESWIN EIC7700
USB controller module.

Co-developed-by: Wei Yang <yangwei1@eswincomputing.com>
Signed-off-by: Wei Yang <yangwei1@eswincomputing.com>
Signed-off-by: Senchuan Zhang <zhangsenchuan@eswincomputing.com>
---
 .../bindings/usb/eswin,eic7700-usb.yaml       | 123 ++++++++++++++++++
 1 file changed, 123 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/eswin,eic7700-usb.yaml

diff --git a/Documentation/devicetree/bindings/usb/eswin,eic7700-usb.yaml b/Documentation/devicetree/bindings/usb/eswin,eic7700-usb.yaml
new file mode 100644
index 000000000000..c5a545d0ef49
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/eswin,eic7700-usb.yaml
@@ -0,0 +1,123 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/eswin,eic7700-usb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Eswin EIC7700 SoC Usb Controller
+
+maintainers:
+  - Wei Yang <yangwei1@eswincomputing.com>
+  - Senchuan Zhang <zhangsenchuan@eswincomputing.com>
+
+description:
+  The Usb controller on EIC7700 SoC.
+
+properties:
+  compatible:
+    const: eswin,eic7700-usb
+
+  reg:
+    maxItems: 1
+
+  '#address-cells':
+    const: 2
+
+  '#size-cells':
+    const: 2
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-names:
+    items:
+      - const: peripheral
+
+  clocks:
+    maxItems: 3
+
+  clock-names:
+    items:
+      - const: suspend
+      - const: aclk
+      - const: cfg
+
+  resets:
+    maxItems: 1
+
+  reset-names:
+    items:
+      - const: vaux
+
+  ranges: true
+
+  eswin,hsp-sp-csr:
+    description:
+      The phandle to HSP(High-Speed Peripheral) Register Controller hsp_sp_csr node
+      and the offset of HSP register for USB.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      - items:
+          - description: phandle to HSP Register Controller hsp_sp_csr node.
+          - description: usb bus register offset.
+          - description: axi low power register offset.
+          - description: vbus frequency register offset.
+          - description: mpll register offset.
+
+patternProperties:
+  "^usb@[0-9a-f]+$":
+    $ref: snps,dwc3.yaml#
+    description: Required child node
+
+required:
+  - compatible
+  - reg
+  - "#address-cells"
+  - "#size-cells"
+  - interrupts
+  - interrupt-names
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - ranges
+  - eswin,hsp-sp-csr
+
+additionalProperties: false
+
+examples:
+  - |
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        usb {
+            compatible = "eswin,eic7700-dwc3";
+            clocks = <&fixed_factor_u_clk_1m_div24>,
+                     <&gate_clk_hsp_aclk>,
+                     <&gate_clk_hsp_cfgclk>;
+            clock-names = "suspend","aclk", "cfg";
+            eswin,hsp-sp-csr = <&hsp_sp_csr 0x800 0x808 0x83c 0x840>;
+            resets = <&reset 84>;
+            reset-names = "vaux";
+            ranges;
+            #address-cells = <2>;
+            #size-cells = <2>;
+
+            usb@50480000 {
+                compatible = "snps,dwc3";
+                reg = <0x0 0x50480000 0x0 0x10000>;
+                interrupt-parent = <&plic>;
+                interrupts = <85>;
+                interrupt-names = "peripheral";
+                dr_mode = "peripheral";
+                phy_type = "utmi";
+                maximum-speed = "high-speed";
+                snps,dis_enblslpm_quirk;
+                snps,dis-u2-freeclk-exists-quirk;
+                snps,dis_u2_susphy_quirk;
+                snps,dis-del-phy-power-chg-quirk;
+                snps,parkmode-disable-ss-quirk;
+            };
+        };
+    };
--
2.25.1