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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4588d873f80sm41992125e9.0.2025.07.30.01.28.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Jul 2025 01:28:27 -0700 (PDT) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: S32@nxp.com, linux-kernel@vger.kernel.org, ghennadi.procopciuc@oss.nxp.com Subject: [PATCH v2 10/20] clocksource/drivers/vf-pit: Encapsulate the macros Date: Wed, 30 Jul 2025 10:27:12 +0200 Message-ID: <20250730082725.183133-11-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250730082725.183133-1-daniel.lezcano@linaro.org> References: <20250730082725.183133-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Pass the base address to the macro, so we can use the macro with multiple instances of the timer because we deal with different base address. At the same time, change writes to the register to the existing corresponding functions. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-vf-pit.c | 35 ++++++++++++++++-------------- 1 file changed, 19 insertions(+), 16 deletions(-) diff --git a/drivers/clocksource/timer-vf-pit.c b/drivers/clocksource/timer-vf-pit.c index 6a4043801eeb..8f0e26c0512d 100644 --- a/drivers/clocksource/timer-vf-pit.c +++ b/drivers/clocksource/timer-vf-pit.c @@ -16,18 +16,21 @@ #define PITMCR 0x00 #define PIT0_OFFSET 0x100 #define PIT_CH(n) (PIT0_OFFSET + 0x10 * (n)) -#define PITLDVAL 0x00 + #define PITCVAL 0x04 -#define PITTCTRL 0x08 -#define PITTFLG 0x0c #define PITMCR_MDIS BIT(1) -#define PITTCTRL_TEN BIT(0) -#define PITTCTRL_TIE BIT(1) -#define PITCTRL_CHN BIT(2) +#define PITLDVAL(__base) (__base) +#define PITTCTRL(__base) ((__base) + 0x08) + + +#define PITTCTRL_TEN BIT(0) +#define PITTCTRL_TIE BIT(1) + +#define PITTFLG(__base) ((__base) + 0x0c) -#define PITTFLG_TIF 0x1 +#define PITTFLG_TIF BIT(0) struct pit_timer { void __iomem *clksrc_base; @@ -51,17 +54,17 @@ static inline struct pit_timer *cs_to_pit(struct clocksource *cs) static inline void pit_timer_enable(struct pit_timer *pit) { - writel(PITTCTRL_TEN | PITTCTRL_TIE, pit->clkevt_base + PITTCTRL); + writel(PITTCTRL_TEN | PITTCTRL_TIE, PITTCTRL(pit->clkevt_base)); } static inline void pit_timer_disable(struct pit_timer *pit) { - writel(0, pit->clkevt_base + PITTCTRL); + writel(0, PITTCTRL(pit->clkevt_base)); } static inline void pit_irq_acknowledge(struct pit_timer *pit) { - writel(PITTFLG_TIF, pit->clkevt_base + PITTFLG); + writel(PITTFLG_TIF, PITTFLG(pit->clkevt_base)); } static u64 notrace pit_read_sched_clock(void) @@ -92,9 +95,9 @@ static int __init pit_clocksource_init(struct pit_timer *pit, void __iomem *base pit->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; /* set the max load value and start the clock source counter */ - writel(0, pit->clksrc_base + PITTCTRL); - writel(~0, pit->clksrc_base + PITLDVAL); - writel(PITTCTRL_TEN, pit->clksrc_base + PITTCTRL); + pit_timer_disable(pit); + writel(~0, PITLDVAL(pit->clksrc_base)); + writel(PITTCTRL_TEN, PITTCTRL(pit->clksrc_base)); clksrc_base = pit->clksrc_base; @@ -115,7 +118,7 @@ static int pit_set_next_event(unsigned long delta, struct clock_event_device *ce * hardware requirement. */ pit_timer_disable(pit); - writel(delta - 1, pit->clkevt_base + PITLDVAL); + writel(delta - 1, PITLDVAL(pit->clkevt_base)); pit_timer_enable(pit); return 0; @@ -171,9 +174,9 @@ static int __init pit_clockevent_init(struct pit_timer *pit, void __iomem *base, pit->clkevt_base = base + PIT_CH(3); pit->cycle_per_jiffy = rate / (HZ); - writel(0, pit->clkevt_base + PITTCTRL); + pit_timer_disable(pit); - writel(PITTFLG_TIF, pit->clkevt_base + PITTFLG); + pit_irq_acknowledge(pit); BUG_ON(request_irq(irq, pit_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, "VF pit timer", &pit->ced)); -- 2.43.0