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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4588d873f80sm41992125e9.0.2025.07.30.01.28.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Jul 2025 01:28:22 -0700 (PDT) From: Daniel Lezcano To: daniel.lezcano@linaro.org, tglx@linutronix.de Cc: S32@nxp.com, linux-kernel@vger.kernel.org, ghennadi.procopciuc@oss.nxp.com Subject: [PATCH v2 04/20] clocksource/drivers/vf-pit: Rework the base address usage Date: Wed, 30 Jul 2025 10:27:06 +0200 Message-ID: <20250730082725.183133-5-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250730082725.183133-1-daniel.lezcano@linaro.org> References: <20250730082725.183133-1-daniel.lezcano@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This change passes the base address to the clockevent and clocksource initialization functions in order to use different base address in the next changes. No functional changes intended. Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-vf-pit.c | 35 +++++++++++++++++++----------- 1 file changed, 22 insertions(+), 13 deletions(-) diff --git a/drivers/clocksource/timer-vf-pit.c b/drivers/clocksource/timer-vf-pit.c index e4a8b32fff75..6a5f940ad0bc 100644 --- a/drivers/clocksource/timer-vf-pit.c +++ b/drivers/clocksource/timer-vf-pit.c @@ -66,8 +66,16 @@ static u64 notrace pit_read_sched_clock(void) return ~readl(clksrc_base + PITCVAL); } -static int __init pit_clocksource_init(struct pit_timer *pit, unsigned long rate) +static int __init pit_clocksource_init(struct pit_timer *pit, void __iomem *base, + unsigned long rate) { + /* + * The channels 0 and 1 can be chained to build a 64-bit + * timer. Let's use the channel 2 as a clocksource and leave + * the channels 0 and 1 unused for anyone else who needs them + */ + pit->clksrc_base = base + PIT_CH(2); + /* set the max load value and start the clock source counter */ writel(0, pit->clksrc_base + PITTCTRL); writel(~0, pit->clksrc_base + PITLDVAL); @@ -76,8 +84,9 @@ static int __init pit_clocksource_init(struct pit_timer *pit, unsigned long rate clksrc_base = pit->clksrc_base; sched_clock_register(pit_read_sched_clock, 32, rate); + return clocksource_mmio_init(pit->clksrc_base + PITCVAL, "vf-pit", rate, - 300, 32, clocksource_mmio_readl_down); + 300, 32, clocksource_mmio_readl_down); } static int pit_set_next_event(unsigned long delta, struct clock_event_device *ced) @@ -137,8 +146,16 @@ static irqreturn_t pit_timer_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static int __init pit_clockevent_init(struct pit_timer *pit, unsigned long rate, int irq) +static int __init pit_clockevent_init(struct pit_timer *pit, void __iomem *base, + unsigned long rate, int irq) { + /* + * The channels 0 and 1 can be chained to build a 64-bit + * timer. Let's use the channel 3 as a clockevent and leave + * the channels 0 and 1 unused for anyone else who needs them + */ + pit->clkevt_base = base + PIT_CH(3); + writel(0, pit->clkevt_base + PITTCTRL); writel(PITTFLG_TIF, pit->clkevt_base + PITTFLG); @@ -182,14 +199,6 @@ static int __init pit_timer_init(struct device_node *np) return -ENXIO; } - /* - * PIT0 and PIT1 can be chained to build a 64-bit timer, - * so choose PIT2 as clocksource, PIT3 as clockevent device, - * and leave PIT0 and PIT1 unused for anyone else who needs them. - */ - pit_timer.clksrc_base = timer_base + PIT_CH(2); - pit_timer.clkevt_base = timer_base + PIT_CH(3); - irq = irq_of_parse_and_map(np, 0); if (irq <= 0) return -EINVAL; @@ -208,10 +217,10 @@ static int __init pit_timer_init(struct device_node *np) /* enable the pit module */ writel(~PITMCR_MDIS, timer_base + PITMCR); - ret = pit_clocksource_init(&pit_timer, clk_rate); + ret = pit_clocksource_init(&pit_timer, timer_base, clk_rate); if (ret) return ret; - return pit_clockevent_init(&pit_timer, clk_rate, irq); + return pit_clockevent_init(&pit_timer, timer_base, clk_rate, irq); } TIMER_OF_DECLARE(vf610, "fsl,vf610-pit", pit_timer_init); -- 2.43.0