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From: Brian Masney <bmasney@redhat.com>
To: Michael Turquette <mturquette@baylibre.com>,
	 Stephen Boyd <sboyd@kernel.org>,
	Maxime Ripard <mripard@kernel.org>
Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
	 Brian Masney <bmasney@redhat.com>
Subject: [PATCH v3 1/9] clk: add kernel docs for struct clk_core
Date: Tue, 12 Aug 2025 10:40:31 -0400	[thread overview]
Message-ID: <20250812-clk-tests-docs-v3-1-054aed58dcd3@redhat.com> (raw)
In-Reply-To: <20250812-clk-tests-docs-v3-0-054aed58dcd3@redhat.com>

Document all of the members of struct clk_core.

Signed-off-by: Brian Masney <bmasney@redhat.com>
---
 drivers/clk/clk.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 55 insertions(+)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index b821b2cdb155331c85fafbd2fac8ab3703a08e4d..41690448ce9ada8eaa30221950da4a3b1c4552d2 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -57,6 +57,61 @@ struct clk_parent_map {
 	int			index;
 };
 
+/**
+ * struct clk_core - This structure represents the internal state of a clk
+ * within the kernel's clock tree. Drivers do not interact with this structure
+ * directly. The clk_core is manipulated by the framework to manage clock
+ * operations, parent/child relationships, rate, and other properties.
+ *
+ * @name:              Unique name of the clk for identification.
+ * @ops:               Pointer to hardware-specific operations for this clk.
+ * @hw:                Pointer for traversing from a struct clk to its
+ *                     corresponding hardware-specific structure.
+ * @owner:             Kernel module owning this clk (for reference counting).
+ * @dev:               Device associated with this clk (optional)
+ * @rpm_node:          Node for runtime power management list management.
+ * @of_node:           Device tree node associated with this clk (if applicable)
+ * @parent:            Pointer to the current parent in the clock tree.
+ * @parents:           Array of possible parents (for muxes/selectable parents).
+ * @num_parents:       Number of possible parents
+ * @new_parent_index:  Index of the new parent during parent change.
+ * @rate:              Current clock rate (Hz). This is effectively a cached
+ *                     value of what the hardware has been programmed with. It's
+ *                     initialized by reading the value at boot time, and will
+ *                     be updated every time an operation affects the rate.
+ *                     Clocks with the CLK_GET_RATE_NOCACHE flag should not use
+ *                     this value, as its rate is expected to change behind the
+ *                     kernel's back (because the firmware might change it, for
+ *                     example). Also, if the clock is orphan, it's set to 0
+ *                     and updated when (and if) its parent is later loaded, so
+ *                     its content is only ever valid if clk_core->orphan is
+ *                     false.
+ * @req_rate:          The last rate requested by a call to clk_set_rate. It's
+ *                     initialized to clk_core->rate. It's also updated to
+ *                     clk_core->rate every time the clock is reparented, and
+ *                     when we're doing the orphan -> !orphan transition.
+ * @new_rate:          New rate to be set during a rate change operation.
+ * @new_parent:        Pointer to new parent during parent change.
+ * @new_child:         Pointer to new child during reparenting.
+ * @flags:             Clock property and capability flags.
+ * @orphan:            True if this clk is currently orphaned.
+ * @rpm_enabled:       True if runtime power management is enabled for this clk.
+ * @enable_count:      Reference count of enables.
+ * @prepare_count:     Reference count of prepares.
+ * @protect_count:     Protection reference count against disable.
+ * @min_rate:          Minimum supported clock rate (Hz).
+ * @max_rate:          Maximum supported clock rate (Hz).
+ * @accuracy:          Accuracy of the clock rate (parts per billion).
+ * @phase:             Current phase (degrees).
+ * @duty:              Current duty cycle configuration.
+ * @children:          All of the children of this clk.
+ * @child_node:        Node for linking as a child in the parent's list.
+ * @clks:              All of the clk consumers registered.
+ * @notifier_count:    Number of notifiers registered for this clk.
+ * @dentry:            DebugFS entry for this clk.
+ * @debug_node:        DebugFS node for this clk.
+ * @ref:               Reference count for structure lifetime management.
+ */
 struct clk_core {
 	const char		*name;
 	const struct clk_ops	*ops;

-- 
2.50.1


  reply	other threads:[~2025-08-12 14:40 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-12 14:40 [PATCH v3 0/9] clk: add kunit tests and some documentation Brian Masney
2025-08-12 14:40 ` Brian Masney [this message]
2025-08-19  9:27   ` [PATCH v3 1/9] clk: add kernel docs for struct clk_core Maxime Ripard
2025-08-12 14:40 ` [PATCH v3 2/9] clk: test: introduce clk_dummy_rate_mhz() Brian Masney
2025-08-19 14:00   ` Maxime Ripard
2025-08-12 14:40 ` [PATCH v3 3/9] clk: test: introduce clk_dummy_div for a mock divider Brian Masney
2025-08-18 20:01   ` Brian Masney
2025-08-12 14:40 ` [PATCH v3 4/9] clk: test: introduce test suite for sibling rate changes on a divider Brian Masney
2025-08-12 14:40 ` [PATCH v3 5/9] clk: test: introduce clk_dummy_gate for a mock gate Brian Masney
2025-08-12 14:40 ` [PATCH v3 6/9] clk: test: introduce test suite for sibling rate changes on a gate Brian Masney
2025-08-12 14:40 ` [PATCH v3 7/9] clk: test: introduce helper to create a mock mux Brian Masney
2025-08-12 14:40 ` [PATCH v3 8/9] clk: test: introduce test variation for sibling rate changes on a mux Brian Masney
2025-08-12 14:40 ` [PATCH v3 9/9] clk: test: introduce test variation for sibling rate changes on a gate/mux Brian Masney

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