From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02C402EE608; Tue, 12 Aug 2025 10:08:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754993321; cv=none; b=IqVwgfA1WIYH98K/PUnErzNKHjnjOqAtxwfhl6FCKYIALsgGTuEuUfdbYZobcVrX5UpQ4A6jGDbiJo87egnM1F2PHNz9sOfIxL6aHDkLhrIQ9ZZoOuUVYPQydht1HISMCHQySgx2qdEkoCyx7VRJ82dziSAw6quppqY3QOMFmp0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1754993321; c=relaxed/simple; bh=kL6bGYM0ZMSLMScq+M/UzqNWj+xf+642H3cPtoz0nAk=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; b=f9uYtk7va0tHXKQUduK9OJimyfXaZMI9UWUTVmci7JFnprRcv/ClCNiWK9206HKcU+nEF9DGx/xSJdBYBQDsaEl6gn/aBqOiZ1/0VxFKZXUZvcLowoyn+ONPWupi2DM4ASnAJvX/JLs19C6LjzmaqTxBmDVukdSujzBfTBy0SME= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 12 Aug 2025 18:08:30 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 12 Aug 2025 18:08:30 +0800 From: Ryan Chen To: ryan_chen , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Kevin Chen , , , , Subject: [PATCH v4 0/2] irqchip/ast2700-intc: Add AST2700 INTC debugfs support and yaml update Date: Tue, 12 Aug 2025 18:08:28 +0800 Message-ID: <20250812100830.145578-1-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain This patch series adds device tree bindings and driver support for the AST2700 SoC!|s two interrupt controllers (INTC0 and INTC1), along with debugfs entries for runtime inspection of routing and register protection status, and bindings example refine. v4: - aspeed,ast2700-intc.yaml - Clarify the relationship between INTC0/INTC1 parent nodes, the aspeed,ast2700-intc-ic child nodes, and the GIC. - Add a block diagram and DT examples showing the cascaded wiring (GIC <- INTC0 <- INTC1 children). - Mirrors the datasheet-described topology and register map, including the separation of INTC0/INTC1 regions. - Lets DT unambiguously express first-level (GIC parent) and cascaded second-level (INTC0 parent) interrupt controllers via examples that use `interrupts` for INTC0 children and `interrupts-extended` for INTC1 children routed into INTC0. - irq-ast2700-intc.c - Drop all string decoding and human readable tables. Debugfs now dumps raw routing/protection registers only. - Split into a separate source file and made it modular - If the compatible not match ast2700-intc0/1, bail out return -ENODEV. v3: - aspeed,ast2700-intc.yaml - Clarify the relationship between INTC0/INTC1 parent nodes, the aspeed,ast2700-intc-ic child nodes, and the GIC. - Add a block diagram and DT examples showing the cascaded wiring (GIC <- INTC0 <- INTC1 children). - Mirrors the datasheet-described topology and register map, including the separation of INTC0/INTC1 regions and their routing/protection registers. - Lets DT unambiguously express first-level (GIC parent) and cascaded second-level (INTC0 parent) interrupt controllers via examples that use `interrupts` for INTC0 children and `interrupts-extended` for INTC1 children routed into INTC0. - irq-aspeed-intc.c - separate c file from irq-aspeed-intc.c - make m v2: - fix dt bindingcheck Ryan Chen (2): dt-bindings: interrupt-controller: aspeed: Add parent compatibles and refine documentation Irqchip/ast2700-intc: add debugfs support and AST2700 INTC0/INTC1 routing/protection display .../aspeed,ast2700-intc.yaml | 158 +++++++++++----- drivers/irqchip/Kconfig | 6 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-ast2700-intc.c | 174 ++++++++++++++++++ 4 files changed, 296 insertions(+), 43 deletions(-) create mode 100644 drivers/irqchip/irq-ast2700-intc.c -- 2.34.1