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Peter Anvin" , "x86@kernel.org" , "linux-kernel@vger.kernel.org" Cc: oe-kbuild-all@lists.linux.dev, Stephen Horvath Subject: Re: [PATCH] x86/tsc: Read AMD CPU frequency from Core::X86::Msr::PStateDef Message-ID: <202508141439.JO8YA6fq-lkp@intel.com> References: <20250813112020.345622-1-s.horvath@outlook.com.au> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250813112020.345622-1-s.horvath@outlook.com.au> Hi Stephen, kernel test robot noticed the following build errors: [auto build test ERROR on tip/x86/core] [also build test ERROR on tip/master linus/master v6.17-rc1 next-20250814] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Stephen-Horvath/x86-tsc-Read-AMD-CPU-frequency-from-Core-X86-Msr-PStateDef/20250813-192644 base: tip/x86/core patch link: https://lore.kernel.org/r/20250813112020.345622-1-s.horvath%40outlook.com.au patch subject: [PATCH] x86/tsc: Read AMD CPU frequency from Core::X86::Msr::PStateDef config: i386-randconfig-007-20250814 (https://download.01.org/0day-ci/archive/20250814/202508141439.JO8YA6fq-lkp@intel.com/config) compiler: gcc-12 (Debian 12.2.0-14+deb12u1) 12.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250814/202508141439.JO8YA6fq-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202508141439.JO8YA6fq-lkp@intel.com/ All errors (new ones prefixed by >>): ld: arch/x86/kernel/tsc_msr.o: in function `cpu_khz_from_msr_amd': >> arch/x86/kernel/tsc_msr.c:307: undefined reference to `__udivdi3' vim +307 arch/x86/kernel/tsc_msr.c 237 238 /* 239 * MSR-based CPU/TSC frequency discovery for AMD Zen CPUs. 240 * 241 * Return processor base frequency in KHz, or 0 on failure. 242 */ 243 unsigned long cpu_khz_from_msr_amd(void) 244 { 245 u64 hwcr, pstatedef; 246 unsigned long cpufid, cpudfsid, p0_freq; 247 248 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) 249 return 0; 250 251 /* 252 * This register mapping is only valid for Zen and later CPUs. 253 * X86_FEATURE_ZEN is not set yet, so we just check the cpuid. 254 */ 255 if (boot_cpu_data.x86 < 0x17) 256 return 0; 257 258 /* 259 * PPR states for MSR0000_0010: 260 * The TSC increments at the P0 frequency. The TSC counts at the 261 * same rate in all P-states, all C states, S0, or S1. 262 */ 263 264 /* Read the Hardware Configuration MSR (MSRC001_0015) */ 265 if (rdmsrq_safe(MSR_K7_HWCR, &hwcr)) 266 return 0; 267 268 /* 269 * Check TscFreqSel (bit 24) is set. 270 * This verifies the TSC does actually increment at P0 frequency. 271 * E.g. VMs may be configured to increment at a different rate. 272 */ 273 if (!(hwcr & BIT_64(24))) 274 return 0; 275 276 /* Read the zeroth PStateDef MSR (MSRC001_0064) */ 277 if (rdmsrq_safe(MSR_AMD_PSTATE_DEF_BASE, &pstatedef)) 278 return 0; 279 280 /* Check PstateEn is set (bit 63) */ 281 if (!(pstatedef & BIT_64(63))) 282 return 0; 283 284 /* CpuFid is the first 8 bits (7:0) */ 285 cpufid = pstatedef & 0xff; 286 287 /* Values between 0Fh-00h are reserved */ 288 if (cpufid < 0x0F) 289 return 0; 290 291 /* The PPR defines the core multiplier as CpuFid * 25MHz */ 292 p0_freq = cpufid * 25; 293 294 /* Convert from MHz to KHz before dividing */ 295 p0_freq *= 1000; 296 297 /* CpuDfsId is the next 6 bits (13:8) */ 298 cpudfsid = (pstatedef >> 8) & 0x3f; 299 300 /* Calculate the core divisor */ 301 switch (cpudfsid) { 302 case 0x08: 303 /* VCO/1 */ 304 break; 305 case 0x09: 306 /* VCO/1.125 */ > 307 p0_freq = (unsigned long)(p0_freq * 1125ull / 1000); -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki