[PATCH v2 0/3] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110

[PATCH v2 0/3] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110

[E Shattow]

Bring in additional downstream U-Boot boot loader changes for StarFive
VisionFive2 board target (and related JH7110 common boards). Create a
basic dt-binding (and not any Linux driver) in support of the
memory-controller dts node used in mainline U-Boot. Also add
bootph-pre-ram hinting to jh7110.dtsi needed at SPL boot phase.

Changes since v1:

- patch 1/3 "add StarFive JH7110 SoC DMC": Rephrase commit message and
  description, drop min/max items and list with description instead, drop
  legacy clock-frequency property.

- patch 2/3 "add memory controller node": Rephrase commit message and
  drop clock-frequency property.

E Shattow (3):
  dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC
  riscv: dts: starfive: jh7110: add DMC memory controller
  riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot
    loader

 .../starfive,jh7110-dmc.yaml                  | 73 +++++++++++++++++++
 arch/riscv/boot/dts/starfive/jh7110.dtsi      | 21 ++++++
 2 files changed, 94 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml


base-commit: cb69daf085b5974fef2df9789f8c1b35e78e7913
-- 
2.50.0

[PATCH v2 1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC

[E Shattow]

Describe JH7110 SoC DDR external memory interface.

Signed-off-by: E Shattow <e@freeshell.de>
---
 .../starfive,jh7110-dmc.yaml                  | 73 +++++++++++++++++++
 1 file changed, 73 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml

diff --git a/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml
new file mode 100644
index 000000000000..be31d76f01ca
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/starfive,jh7110-dmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 DMC
+
+maintainers:
+  - E Shattow <e@freeshell.de>
+
+description:
+  JH7110 DDR external memory interface LPDDR4/DDR4/DDR3/LPDDR3 32-bit at 2133Mbps (up to 2800Mbps).
+
+properties:
+  compatible:
+    items:
+      - const: starfive,jh7110-dmc
+
+  reg:
+    items:
+      - description: controller registers
+      - description: phy registers
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: pll1_out
+
+  resets:
+    items:
+      - description: axi
+      - description: osc
+      - description: apb
+
+  reset-names:
+    items:
+      - const: axi
+      - const: osc
+      - const: apb
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/starfive,jh7110-crg.h>
+    #include <dt-bindings/reset/starfive,jh7110-crg.h>
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      memory-controller@15700000 {
+        compatible = "starfive,jh7110-dmc";
+        reg = <0x0 0x15700000 0x0 0x10000>,
+              <0x0 0x13000000 0x0 0x10000>;
+        clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
+        clock-names = "pll1_out";
+        resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
+                 <&syscrg JH7110_SYSRST_DDR_OSC>,
+                 <&syscrg JH7110_SYSRST_DDR_APB>;
+        reset-names = "axi", "osc", "apb";
+      };
+    };
-- 
2.50.0

[PATCH v2 2/3] riscv: dts: starfive: jh7110: add DMC memory controller

[E Shattow]

Add JH7110 SoC DDR external memory controller.

Signed-off-by: E Shattow <e@freeshell.de>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 0ba74ef04679..14df3d062a45 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -372,6 +372,18 @@ ccache: cache-controller@2010000 {
 			cache-unified;
 		};
 
+		memory-controller@15700000 {
+			compatible = "starfive,jh7110-dmc";
+			reg = <0x0 0x15700000 0x0 0x10000>,
+			      <0x0 0x13000000 0x0 0x10000>;
+			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
+			clock-names = "pll1_out";
+			resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
+				 <&syscrg JH7110_SYSRST_DDR_OSC>,
+				 <&syscrg JH7110_SYSRST_DDR_APB>;
+			reset-names = "axi", "osc", "apb";
+		};
+
 		plic: interrupt-controller@c000000 {
 			compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
 			reg = <0x0 0xc000000 0x0 0x4000000>;
-- 
2.50.0

[PATCH v2 3/3] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader

[E Shattow]

Add bootph-pre-ram hinting to jh7110.dtsi:
  - CPU interrupt controller(s)
  - core local interrupt timer
  - DDR memory controller
  - oscillator
  - syscrg clock-controller

Signed-off-by: E Shattow <e@freeshell.de>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 14df3d062a45..884a3526cb0f 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -35,6 +35,7 @@ S7_0: cpu@0 {
 
 			cpu0_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
+				bootph-pre-ram;
 				interrupt-controller;
 				#interrupt-cells = <1>;
 			};
@@ -68,6 +69,7 @@ U74_1: cpu@1 {
 
 			cpu1_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
+				bootph-pre-ram;
 				interrupt-controller;
 				#interrupt-cells = <1>;
 			};
@@ -101,6 +103,7 @@ U74_2: cpu@2 {
 
 			cpu2_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
+				bootph-pre-ram;
 				interrupt-controller;
 				#interrupt-cells = <1>;
 			};
@@ -134,6 +137,7 @@ U74_3: cpu@3 {
 
 			cpu3_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
+				bootph-pre-ram;
 				interrupt-controller;
 				#interrupt-cells = <1>;
 			};
@@ -167,6 +171,7 @@ U74_4: cpu@4 {
 
 			cpu4_intc: interrupt-controller {
 				compatible = "riscv,cpu-intc";
+				bootph-pre-ram;
 				interrupt-controller;
 				#interrupt-cells = <1>;
 			};
@@ -321,6 +326,7 @@ mclk_ext: mclk-ext-clock {
 
 	osc: oscillator {
 		compatible = "fixed-clock";
+		bootph-pre-ram;
 		clock-output-names = "osc";
 		#clock-cells = <0>;
 	};
@@ -354,6 +360,7 @@ soc {
 		clint: timer@2000000 {
 			compatible = "starfive,jh7110-clint", "sifive,clint0";
 			reg = <0x0 0x2000000 0x0 0x10000>;
+			bootph-pre-ram;
 			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
 					      <&cpu1_intc 3>, <&cpu1_intc 7>,
 					      <&cpu2_intc 3>, <&cpu2_intc 7>,
@@ -376,6 +383,7 @@ memory-controller@15700000 {
 			compatible = "starfive,jh7110-dmc";
 			reg = <0x0 0x15700000 0x0 0x10000>,
 			      <0x0 0x13000000 0x0 0x10000>;
+			bootph-pre-ram;
 			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
 			clock-names = "pll1_out";
 			resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
@@ -892,6 +900,7 @@ qspi: spi@13010000 {
 		syscrg: clock-controller@13020000 {
 			compatible = "starfive,jh7110-syscrg";
 			reg = <0x0 0x13020000 0x0 0x10000>;
+			bootph-pre-ram;
 			clocks = <&osc>, <&gmac1_rmii_refin>,
 				 <&gmac1_rgmii_rxin>,
 				 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
-- 
2.50.0

RE: [PATCH v2 3/3] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader

[Hal Feng]

> On 15.08.25 15:37, E Shattow wrote:
> Add bootph-pre-ram hinting to jh7110.dtsi:
>   - CPU interrupt controller(s)
>   - core local interrupt timer
>   - DDR memory controller
>   - oscillator
>   - syscrg clock-controller
> 
> Signed-off-by: E Shattow <e@freeshell.de>
> ---
>  arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index 14df3d062a45..884a3526cb0f 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -35,6 +35,7 @@ S7_0: cpu@0 {
> 
>  			cpu0_intc: interrupt-controller {
>  				compatible = "riscv,cpu-intc";
> +				bootph-pre-ram;
>  				interrupt-controller;
>  				#interrupt-cells = <1>;
>  			};
> @@ -68,6 +69,7 @@ U74_1: cpu@1 {
> 
>  			cpu1_intc: interrupt-controller {
>  				compatible = "riscv,cpu-intc";
> +				bootph-pre-ram;
>  				interrupt-controller;
>  				#interrupt-cells = <1>;
>  			};
> @@ -101,6 +103,7 @@ U74_2: cpu@2 {
> 
>  			cpu2_intc: interrupt-controller {
>  				compatible = "riscv,cpu-intc";
> +				bootph-pre-ram;
>  				interrupt-controller;
>  				#interrupt-cells = <1>;
>  			};
> @@ -134,6 +137,7 @@ U74_3: cpu@3 {
> 
>  			cpu3_intc: interrupt-controller {
>  				compatible = "riscv,cpu-intc";
> +				bootph-pre-ram;
>  				interrupt-controller;
>  				#interrupt-cells = <1>;
>  			};
> @@ -167,6 +171,7 @@ U74_4: cpu@4 {
> 
>  			cpu4_intc: interrupt-controller {
>  				compatible = "riscv,cpu-intc";
> +				bootph-pre-ram;
>  				interrupt-controller;
>  				#interrupt-cells = <1>;
>  			};
> @@ -321,6 +326,7 @@ mclk_ext: mclk-ext-clock {
> 
>  	osc: oscillator {
>  		compatible = "fixed-clock";
> +		bootph-pre-ram;
>  		clock-output-names = "osc";
>  		#clock-cells = <0>;
>  	};
> @@ -354,6 +360,7 @@ soc {
>  		clint: timer@2000000 {
>  			compatible = "starfive,jh7110-clint", "sifive,clint0";
>  			reg = <0x0 0x2000000 0x0 0x10000>;
> +			bootph-pre-ram;
>  			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc
> 7>,
>  					      <&cpu1_intc 3>, <&cpu1_intc 7>,
>  					      <&cpu2_intc 3>, <&cpu2_intc 7>,
> @@ -376,6 +383,7 @@ memory-controller@15700000 {
>  			compatible = "starfive,jh7110-dmc";
>  			reg = <0x0 0x15700000 0x0 0x10000>,
>  			      <0x0 0x13000000 0x0 0x10000>;
> +			bootph-pre-ram;
>  			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
>  			clock-names = "pll1_out";
>  			resets = <&syscrg JH7110_SYSRST_DDR_AXI>, @@ -
> 892,6 +900,7 @@ qspi: spi@13010000 {
>  		syscrg: clock-controller@13020000 {
>  			compatible = "starfive,jh7110-syscrg";
>  			reg = <0x0 0x13020000 0x0 0x10000>;
> +			bootph-pre-ram;
>  			clocks = <&osc>, <&gmac1_rmii_refin>,
>  				 <&gmac1_rgmii_rxin>,
>  				 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,

pllclk also needs to add bootph-pre-ram. Because it is the dependency of syscrg.

		pllclk: clock-controller {
			compatible = "starfive,jh7110-pll";
+			bootph-pre-ram;
			clocks = <&osc>;
			#clock-cells = <1>;
		};

Best regards,
Hal

RE: [PATCH v2 2/3] riscv: dts: starfive: jh7110: add DMC memory controller

[Hal Feng]

> On 15.08.25 15:37, E Shattow wrote:
> Add JH7110 SoC DDR external memory controller.
> 
> Signed-off-by: E Shattow <e@freeshell.de>
> ---
>  arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index 0ba74ef04679..14df3d062a45 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -372,6 +372,18 @@ ccache: cache-controller@2010000 {
>  			cache-unified;
>  		};
> 
> +		memory-controller@15700000 {
> +			compatible = "starfive,jh7110-dmc";
> +			reg = <0x0 0x15700000 0x0 0x10000>,
> +			      <0x0 0x13000000 0x0 0x10000>;
> +			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
> +			clock-names = "pll1_out";
> +			resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
> +				 <&syscrg JH7110_SYSRST_DDR_OSC>,
> +				 <&syscrg JH7110_SYSRST_DDR_APB>;
> +			reset-names = "axi", "osc", "apb";
> +		};
> +
>  		plic: interrupt-controller@c000000 {
>  			compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
>  			reg = <0x0 0xc000000 0x0 0x4000000>;

Nodes are sorted by reg address. So please place memory-controller@15700000
between watchdog@13070000 and crypto@16000000. Thanks.

Best regards,
Hal

Re: [PATCH v2 1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC

[Krzysztof Kozlowski]

On Fri, Aug 15, 2025 at 12:37:21AM -0700, E Shattow wrote:
> +
> +title: StarFive JH7110 DMC
> +
> +maintainers:
> +  - E Shattow <e@freeshell.de>
> +
> +description:
> +  JH7110 DDR external memory interface LPDDR4/DDR4/DDR3/LPDDR3 32-bit at 2133Mbps (up to 2800Mbps).

Please wrap at 80 (see Linux Coding style)

> +
> +properties:
> +  compatible:
> +    items:
> +      - const: starfive,jh7110-dmc
> +
> +  reg:
> +    items:
> +      - description: controller registers
> +      - description: phy registers
> +
> +  clocks:
> +    maxItems: 1
> +
> +  clock-names:
> +    items:
> +      - const: pll1_out

pll

(this is name of input, not name of clock)

Best regards,
Krzysztof

Re: [PATCH v2 3/3] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader

[E Shattow]

On 8/17/25 23:05, Hal Feng wrote:
>> On 15.08.25 15:37, E Shattow wrote:
>> Add bootph-pre-ram hinting to jh7110.dtsi:
>>   - CPU interrupt controller(s)
>>   - core local interrupt timer
>>   - DDR memory controller
>>   - oscillator
>>   - syscrg clock-controller
>>
>> Signed-off-by: E Shattow <e@freeshell.de>
>> ---
>>  arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 +++++++++
>>  1 file changed, 9 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> index 14df3d062a45..884a3526cb0f 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> @@ -35,6 +35,7 @@ S7_0: cpu@0 {
>>
>>  			cpu0_intc: interrupt-controller {
>>  				compatible = "riscv,cpu-intc";
>> +				bootph-pre-ram;
>>  				interrupt-controller;
>>  				#interrupt-cells = <1>;
>>  			};
>> @@ -68,6 +69,7 @@ U74_1: cpu@1 {
>>
>>  			cpu1_intc: interrupt-controller {
>>  				compatible = "riscv,cpu-intc";
>> +				bootph-pre-ram;
>>  				interrupt-controller;
>>  				#interrupt-cells = <1>;
>>  			};
>> @@ -101,6 +103,7 @@ U74_2: cpu@2 {
>>
>>  			cpu2_intc: interrupt-controller {
>>  				compatible = "riscv,cpu-intc";
>> +				bootph-pre-ram;
>>  				interrupt-controller;
>>  				#interrupt-cells = <1>;
>>  			};
>> @@ -134,6 +137,7 @@ U74_3: cpu@3 {
>>
>>  			cpu3_intc: interrupt-controller {
>>  				compatible = "riscv,cpu-intc";
>> +				bootph-pre-ram;
>>  				interrupt-controller;
>>  				#interrupt-cells = <1>;
>>  			};
>> @@ -167,6 +171,7 @@ U74_4: cpu@4 {
>>
>>  			cpu4_intc: interrupt-controller {
>>  				compatible = "riscv,cpu-intc";
>> +				bootph-pre-ram;
>>  				interrupt-controller;
>>  				#interrupt-cells = <1>;
>>  			};
>> @@ -321,6 +326,7 @@ mclk_ext: mclk-ext-clock {
>>
>>  	osc: oscillator {
>>  		compatible = "fixed-clock";
>> +		bootph-pre-ram;
>>  		clock-output-names = "osc";
>>  		#clock-cells = <0>;
>>  	};
>> @@ -354,6 +360,7 @@ soc {
>>  		clint: timer@2000000 {
>>  			compatible = "starfive,jh7110-clint", "sifive,clint0";
>>  			reg = <0x0 0x2000000 0x0 0x10000>;
>> +			bootph-pre-ram;
>>  			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc
>> 7>,
>>  					      <&cpu1_intc 3>, <&cpu1_intc 7>,
>>  					      <&cpu2_intc 3>, <&cpu2_intc 7>,
>> @@ -376,6 +383,7 @@ memory-controller@15700000 {
>>  			compatible = "starfive,jh7110-dmc";
>>  			reg = <0x0 0x15700000 0x0 0x10000>,
>>  			      <0x0 0x13000000 0x0 0x10000>;
>> +			bootph-pre-ram;
>>  			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
>>  			clock-names = "pll1_out";
>>  			resets = <&syscrg JH7110_SYSRST_DDR_AXI>, @@ -
>> 892,6 +900,7 @@ qspi: spi@13010000 {
>>  		syscrg: clock-controller@13020000 {
>>  			compatible = "starfive,jh7110-syscrg";
>>  			reg = <0x0 0x13020000 0x0 0x10000>;
>> +			bootph-pre-ram;
>>  			clocks = <&osc>, <&gmac1_rmii_refin>,
>>  				 <&gmac1_rgmii_rxin>,
>>  				 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
> 
> pllclk also needs to add bootph-pre-ram. Because it is the dependency of syscrg.
> 
> 		pllclk: clock-controller {
> 			compatible = "starfive,jh7110-pll";
> +			bootph-pre-ram;
> 			clocks = <&osc>;
> 			#clock-cells = <1>;
> 		};
> 
> Best regards,
> Hal

What users are there for 'pllclk' at U-Boot SPL phase? There does not
seem to be any difference in testing U-Boot and Linux with or without
this hint for 'pllclk'.

Thanks,

-E

RE: [PATCH v2 3/3] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader

[Hal Feng]

> -----Original Message-----
> From: E Shattow <e@freeshell.de>
> Sent: 2025年8月20日 11:49
> To: Hal Feng <hal.feng@starfivetech.com>; Conor Dooley <conor@kernel.org>;
> Emil Renner Berthing <kernel@esmil.dk>; Rob Herring <robh@kernel.org>;
> Krzysztof Kozlowski <krzk+dt@kernel.org>; Paul Walmsley
> <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; Albert
> Ou <aou@eecs.berkeley.edu>; Alexandre Ghiti <alex@ghiti.fr>
> Cc: devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-
> riscv@lists.infradead.org
> Subject: Re: [PATCH v2 3/3] riscv: dts: starfive: jh7110: bootph-pre-ram
> hinting needed by boot loader
> 
> 
> 
> On 8/17/25 23:05, Hal Feng wrote:
> >> On 15.08.25 15:37, E Shattow wrote:
> >> Add bootph-pre-ram hinting to jh7110.dtsi:
> >>   - CPU interrupt controller(s)
> >>   - core local interrupt timer
> >>   - DDR memory controller
> >>   - oscillator
> >>   - syscrg clock-controller
> >>
> >> Signed-off-by: E Shattow <e@freeshell.de>
> >> ---
> >>  arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 +++++++++
> >>  1 file changed, 9 insertions(+)
> >>
> >> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> >> b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> >> index 14df3d062a45..884a3526cb0f 100644
> >> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> >> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> >> @@ -35,6 +35,7 @@ S7_0: cpu@0 {
> >>
> >>  			cpu0_intc: interrupt-controller {
> >>  				compatible = "riscv,cpu-intc";
> >> +				bootph-pre-ram;
> >>  				interrupt-controller;
> >>  				#interrupt-cells = <1>;
> >>  			};
> >> @@ -68,6 +69,7 @@ U74_1: cpu@1 {
> >>
> >>  			cpu1_intc: interrupt-controller {
> >>  				compatible = "riscv,cpu-intc";
> >> +				bootph-pre-ram;
> >>  				interrupt-controller;
> >>  				#interrupt-cells = <1>;
> >>  			};
> >> @@ -101,6 +103,7 @@ U74_2: cpu@2 {
> >>
> >>  			cpu2_intc: interrupt-controller {
> >>  				compatible = "riscv,cpu-intc";
> >> +				bootph-pre-ram;
> >>  				interrupt-controller;
> >>  				#interrupt-cells = <1>;
> >>  			};
> >> @@ -134,6 +137,7 @@ U74_3: cpu@3 {
> >>
> >>  			cpu3_intc: interrupt-controller {
> >>  				compatible = "riscv,cpu-intc";
> >> +				bootph-pre-ram;
> >>  				interrupt-controller;
> >>  				#interrupt-cells = <1>;
> >>  			};
> >> @@ -167,6 +171,7 @@ U74_4: cpu@4 {
> >>
> >>  			cpu4_intc: interrupt-controller {
> >>  				compatible = "riscv,cpu-intc";
> >> +				bootph-pre-ram;
> >>  				interrupt-controller;
> >>  				#interrupt-cells = <1>;
> >>  			};
> >> @@ -321,6 +326,7 @@ mclk_ext: mclk-ext-clock {
> >>
> >>  	osc: oscillator {
> >>  		compatible = "fixed-clock";
> >> +		bootph-pre-ram;
> >>  		clock-output-names = "osc";
> >>  		#clock-cells = <0>;
> >>  	};
> >> @@ -354,6 +360,7 @@ soc {
> >>  		clint: timer@2000000 {
> >>  			compatible = "starfive,jh7110-clint", "sifive,clint0";
> >>  			reg = <0x0 0x2000000 0x0 0x10000>;
> >> +			bootph-pre-ram;
> >>  			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc
> >> 7>,
> >>  					      <&cpu1_intc 3>, <&cpu1_intc 7>,
> >>  					      <&cpu2_intc 3>, <&cpu2_intc 7>,
> @@ -376,6 +383,7 @@
> >> memory-controller@15700000 {
> >>  			compatible = "starfive,jh7110-dmc";
> >>  			reg = <0x0 0x15700000 0x0 0x10000>,
> >>  			      <0x0 0x13000000 0x0 0x10000>;
> >> +			bootph-pre-ram;
> >>  			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
> >>  			clock-names = "pll1_out";
> >>  			resets = <&syscrg JH7110_SYSRST_DDR_AXI>, @@ -
> >> 892,6 +900,7 @@ qspi: spi@13010000 {
> >>  		syscrg: clock-controller@13020000 {
> >>  			compatible = "starfive,jh7110-syscrg";
> >>  			reg = <0x0 0x13020000 0x0 0x10000>;
> >> +			bootph-pre-ram;
> >>  			clocks = <&osc>, <&gmac1_rmii_refin>,
> >>  				 <&gmac1_rgmii_rxin>,
> >>  				 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
> >
> > pllclk also needs to add bootph-pre-ram. Because it is the dependency of
> syscrg.
> >
> > 		pllclk: clock-controller {
> > 			compatible = "starfive,jh7110-pll";
> > +			bootph-pre-ram;
> > 			clocks = <&osc>;
> > 			#clock-cells = <1>;
> > 		};
> >
> > Best regards,
> > Hal
> 
> What users are there for 'pllclk' at U-Boot SPL phase? There does not seem to
> be any difference in testing U-Boot and Linux with or without this hint for
> 'pllclk'.

I see commit 8b3f2eb7d8912204bda2d914b8a9a1ce1c31bb5c adding this line to
solve some problems.

https://lore.kernel.org/all/20250330162421.238483-1-heinrich.schuchardt@canonical.com/

Best regards,
Hal

Re: [PATCH v2 3/3] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader

[E Shattow]

On 8/22/25 02:27, Hal Feng wrote:
> 
> 
>> -----Original Message-----
>> From: E Shattow <e@freeshell.de>
>> Sent: 2025年8月20日 11:49
>> To: Hal Feng <hal.feng@starfivetech.com>; Conor Dooley <conor@kernel.org>;
>> Emil Renner Berthing <kernel@esmil.dk>; Rob Herring <robh@kernel.org>;
>> Krzysztof Kozlowski <krzk+dt@kernel.org>; Paul Walmsley
>> <paul.walmsley@sifive.com>; Palmer Dabbelt <palmer@dabbelt.com>; Albert
>> Ou <aou@eecs.berkeley.edu>; Alexandre Ghiti <alex@ghiti.fr>
>> Cc: devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-
>> riscv@lists.infradead.org
>> Subject: Re: [PATCH v2 3/3] riscv: dts: starfive: jh7110: bootph-pre-ram
>> hinting needed by boot loader
>>
>>
>>
>> On 8/17/25 23:05, Hal Feng wrote:
>>>> On 15.08.25 15:37, E Shattow wrote:
>>>> Add bootph-pre-ram hinting to jh7110.dtsi:
>>>>   - CPU interrupt controller(s)
>>>>   - core local interrupt timer
>>>>   - DDR memory controller
>>>>   - oscillator
>>>>   - syscrg clock-controller
>>>>
>>>> Signed-off-by: E Shattow <e@freeshell.de>
>>>> ---
>>>>  arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 +++++++++
>>>>  1 file changed, 9 insertions(+)
>>>>
>>>> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>>>> b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>>>> index 14df3d062a45..884a3526cb0f 100644
>>>> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>>>> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>>>> @@ -35,6 +35,7 @@ S7_0: cpu@0 {
>>>>
>>>>  			cpu0_intc: interrupt-controller {
>>>>  				compatible = "riscv,cpu-intc";
>>>> +				bootph-pre-ram;
>>>>  				interrupt-controller;
>>>>  				#interrupt-cells = <1>;
>>>>  			};
>>>> @@ -68,6 +69,7 @@ U74_1: cpu@1 {
>>>>
>>>>  			cpu1_intc: interrupt-controller {
>>>>  				compatible = "riscv,cpu-intc";
>>>> +				bootph-pre-ram;
>>>>  				interrupt-controller;
>>>>  				#interrupt-cells = <1>;
>>>>  			};
>>>> @@ -101,6 +103,7 @@ U74_2: cpu@2 {
>>>>
>>>>  			cpu2_intc: interrupt-controller {
>>>>  				compatible = "riscv,cpu-intc";
>>>> +				bootph-pre-ram;
>>>>  				interrupt-controller;
>>>>  				#interrupt-cells = <1>;
>>>>  			};
>>>> @@ -134,6 +137,7 @@ U74_3: cpu@3 {
>>>>
>>>>  			cpu3_intc: interrupt-controller {
>>>>  				compatible = "riscv,cpu-intc";
>>>> +				bootph-pre-ram;
>>>>  				interrupt-controller;
>>>>  				#interrupt-cells = <1>;
>>>>  			};
>>>> @@ -167,6 +171,7 @@ U74_4: cpu@4 {
>>>>
>>>>  			cpu4_intc: interrupt-controller {
>>>>  				compatible = "riscv,cpu-intc";
>>>> +				bootph-pre-ram;
>>>>  				interrupt-controller;
>>>>  				#interrupt-cells = <1>;
>>>>  			};
>>>> @@ -321,6 +326,7 @@ mclk_ext: mclk-ext-clock {
>>>>
>>>>  	osc: oscillator {
>>>>  		compatible = "fixed-clock";
>>>> +		bootph-pre-ram;
>>>>  		clock-output-names = "osc";
>>>>  		#clock-cells = <0>;
>>>>  	};
>>>> @@ -354,6 +360,7 @@ soc {
>>>>  		clint: timer@2000000 {
>>>>  			compatible = "starfive,jh7110-clint", "sifive,clint0";
>>>>  			reg = <0x0 0x2000000 0x0 0x10000>;
>>>> +			bootph-pre-ram;
>>>>  			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc
>>>> 7>,
>>>>  					      <&cpu1_intc 3>, <&cpu1_intc 7>,
>>>>  					      <&cpu2_intc 3>, <&cpu2_intc 7>,
>> @@ -376,6 +383,7 @@
>>>> memory-controller@15700000 {
>>>>  			compatible = "starfive,jh7110-dmc";
>>>>  			reg = <0x0 0x15700000 0x0 0x10000>,
>>>>  			      <0x0 0x13000000 0x0 0x10000>;
>>>> +			bootph-pre-ram;
>>>>  			clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
>>>>  			clock-names = "pll1_out";
>>>>  			resets = <&syscrg JH7110_SYSRST_DDR_AXI>, @@ -
>>>> 892,6 +900,7 @@ qspi: spi@13010000 {
>>>>  		syscrg: clock-controller@13020000 {
>>>>  			compatible = "starfive,jh7110-syscrg";
>>>>  			reg = <0x0 0x13020000 0x0 0x10000>;
>>>> +			bootph-pre-ram;
>>>>  			clocks = <&osc>, <&gmac1_rmii_refin>,
>>>>  				 <&gmac1_rgmii_rxin>,
>>>>  				 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
>>>
>>> pllclk also needs to add bootph-pre-ram. Because it is the dependency of
>> syscrg.
>>>
>>> 		pllclk: clock-controller {
>>> 			compatible = "starfive,jh7110-pll";
>>> +			bootph-pre-ram;
>>> 			clocks = <&osc>;
>>> 			#clock-cells = <1>;
>>> 		};
>>>
>>> Best regards,
>>> Hal
>>
>> What users are there for 'pllclk' at U-Boot SPL phase? There does not seem to
>> be any difference in testing U-Boot and Linux with or without this hint for
>> 'pllclk'.
> 
> I see commit 8b3f2eb7d8912204bda2d914b8a9a1ce1c31bb5c adding this line to
> solve some problems.
> 
> https://lore.kernel.org/all/20250330162421.238483-1-heinrich.schuchardt@canonical.com/

Yes, there was some mistake in how I am testing U-Boot SPL. Given that
(U-Boot code base) jh7110-u-boot.dtsi override is replaced with contents:

/ {
        soc {
                memory-controller@15700000 {
                        clock-frequency = <2133>; /* starfive_ddr.c
driver needs update to use common clocks */
                };
        };
};

&syscrg {
        assigned-clock-rates = <0>; /* cpufreq not implemented, use
defaults */
};

I am now able to reproduce this boot failure in U-Boot SPL on Star64.

Additionally, U-Boot SPL fails to boot if 'gmac1_rgmii_rxin' or
'gmac1_rmii_refin' are missing bootph-pre-ram hint, as a dependency of
syscrg. It is okay to omit hints for 'gmac0_rgmii_rxin' and
'gmac0_rmii_refin' as the dependency of aoncrg not used at U-Boot SPL.

In the next version of this series will be added bootph-pre-ram hints
for syscrg dependencies: 'pllclk', 'gmac1_rgmii_rxin', and
'gmac1_rmii_refin'

Thank you, Hal.

-E

> 
> Best regards,
> Hal
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