From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A72F272803; Wed, 20 Aug 2025 08:34:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755678861; cv=none; b=HdxO1A1Yze1y/d1dtFPcVRgQ5KMoeUR5o2P1Ql5yga8h/LEJ4K5Vk3xHZIruqreHSm91ospdi3a7Tu8gCOoxojNJJ8rBqpeKqz+FSSHChQvvFSYoVSa4SWxShKn+ndWWam6iHiN0Xj4ScJcVYy3Q7ykRs0BgUn+XZ2szg738O18= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755678861; c=relaxed/simple; bh=IQRVkcCITSm3szIByAT9qLys24vtINUmw91Mle4w8K0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Py86f5dUhjGHRaLD+T/XJ1YdqT/HTAz5AWaLfCRj1Gjm+wbqX1NMRALqtTexW74/I4cmqtwZY1Si33ddVjYHg8Ybc3O+xNQfvF2iLjHdx01t9wZ1NnCvcOY4kzxWQoHtQnY+yy0h/ETMFiQxVkKjQZfZq8xMHGfc14KbmMuTspQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=x8jhm7mD; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="x8jhm7mD" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 57K8YC90210348; Wed, 20 Aug 2025 03:34:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1755678852; bh=weQAueA4hmHDZvKZ3RiNTiHK/0dkmQeiIX+hZC1f8hY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=x8jhm7mDmimU1mlTp2Nk/m8SdzpGf+9VjE6zf+vjM+FSNzTONMA1yIuPchUrcERbo xAruAkqfB5anHtK2512UsZDW1L82XPXxsMV8iRQQjXEwiOwsjhAWEMD7fGJivsyaMx fNcZeIwmEPv7BB3RCrkY8XbB0EJjRSBKJVxbJnHM= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 57K8YC2P1223587 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Wed, 20 Aug 2025 03:34:12 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Wed, 20 Aug 2025 03:34:11 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Wed, 20 Aug 2025 03:34:11 -0500 Received: from localhost (ula0502350.dhcp.ti.com [172.24.233.249]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57K8YABb228442; Wed, 20 Aug 2025 03:34:11 -0500 From: Paresh Bhagat To: , , CC: , , , , , , , , , , , , , , Subject: [PATCH 2/4] arm64: dts: ti: k3-am62d2-evm: Enable USB support Date: Wed, 20 Aug 2025 14:03:29 +0530 Message-ID: <20250820083331.3412378-3-p-bhagat@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250820083331.3412378-1-p-bhagat@ti.com> References: <20250820083331.3412378-1-p-bhagat@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Add pinmux configuration for USB1 interface and enable the node for functionality. Also enable data transfer on USB0, on existing power delivery configuration. Signed-off-by: Paresh Bhagat Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-am62d2-evm.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts index daea18b0bc61..9704c2d97f43 100644 --- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts @@ -367,6 +367,12 @@ usr_led_pins_default: usr-led-default-pins { AM62DX_IOPAD(0x0244, PIN_INPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */ >; }; + + main_usb1_pins_default: main-usb1-default-pins { + pinctrl-single,pins = < + AM62DX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (D19) USB1_DRVVBUS */ + >; + }; }; &mcu_gpio0 { @@ -499,6 +505,11 @@ &main_uart0 { status = "okay"; }; +&usbss0 { + status = "okay"; + ti,vbus-divider; +}; + &usb0 { usb-role-switch; @@ -509,6 +520,16 @@ usb0_hs_ep: endpoint { }; }; +&usbss1 { + status = "okay"; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usb1_pins_default>; +}; + &cpsw3g { pinctrl-names = "default"; pinctrl-0 = <&main_rgmii1_pins_default>, -- 2.34.1