[PATCH v4 0/4] Add CMDQ driver support for 8189

[PATCH v4 0/4] Add CMDQ driver support for 8189

[Xiandong Wang]

The patches are based on the series:
https://lore.kernel.org/all/20250601173355.1731140-3-jason-jh.lin@mediatek.com/
https://lore.kernel.org/all/20250601173355.1731140-4-jason-jh.lin@mediatek.com/
https://lore.kernel.org/all/20250601173355.1731140-7-jason-jh.lin@mediatek.com/
https://lore.kernel.org/all/20250601173355.1731140-8-jason-jh.lin@mediatek.com/

Changes in v4:
-Modify the order of driver data for 8189.
-All uppercase characters in the GCE header have been converted to lowercase characters.
-Link to v3: https://lore.kernel.org/all/20250819033746.16405-2-xiandong.wang@mediatek.com/

Changes in v3:
-Modify unused property of 8189 driver data
-Link to v3: https://lore.kernel.org/all/20250819033746.16405-4-xiandong.wang@mediatek.com/ 

Changes in v2:
-Modify the title for series.
-Link to v2: https://lore.kernel.org/all/20250819015948.15450-2-xiandong.wang@mediatek.com/

Changes in v1:
-Add GCE driver data for 8189.
-Modify the clk api for 8189 gce suspend/resume.
-Link to v1: https://lore.kernel.org/all/20250814070401.13432-1-xiandong.wang@mediatek.com/

Xiandong Wang (4):
[v4,01/04] dt-bindings: mailbox: add cmdq yaml for MT8189
[v4,02/04] arm64: dts: mediatek: Add GCE header for mt8189
[v4,03/04] mailbox: mtk-cmdq: Add CMDQ driver support for mt8189
[v4,04/04] mailbox: mtk-cmdq: Fix clock handling using clk_bulk_prepare_enable

 .../mailbox/mediatek,gce-mailbox.yaml         |   1 +
 arch/arm64/boot/dts/mediatek/mt8189-gce.h     | 870 ++++++++++++++++++
 drivers/mailbox/mtk-cmdq-mailbox.c            |  24 +-
 3 files changed, 885 insertions(+), 10 deletions(-)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-gce.h

-- 
2.46.0

[PATCH v4 1/4] dt-bindings: mailbox: add cmdq yaml for MT8189

[Xiandong Wang]

Add compatible string to support cmdq for MT8189.

Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.com>
---
 .../devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml        | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
index 73d6db34d64a..f9718b90d36a 100644
--- a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
+++ b/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
@@ -23,6 +23,7 @@ properties:
           - mediatek,mt8183-gce
           - mediatek,mt8186-gce
           - mediatek,mt8188-gce
+          - mediatek,mt8189-gce
           - mediatek,mt8192-gce
           - mediatek,mt8195-gce
           - mediatek,mt8196-gce
-- 
2.46.0

[PATCH v4 2/4] arm64: dts: mediatek: Add GCE header for mt8189

[Xiandong Wang]

Add CGE header define for GCE Thread Priority and GCE Event IDs
that used in MT8189 dtsi.

Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8189-gce.h | 870 ++++++++++++++++++++++
 1 file changed, 870 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt8189-gce.h

diff --git a/arch/arm64/boot/dts/mediatek/mt8189-gce.h b/arch/arm64/boot/dts/mediatek/mt8189-gce.h
new file mode 100644
index 000000000000..a270013b3455
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8189-gce.h
@@ -0,0 +1,870 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ *
+ */
+
+#ifndef _DT_GCE_MT8189_H
+#define _DT_GCE_MT8189_H
+
+/* assign timeout 0 also means default */
+#define CMDQ_NO_TIMEOUT		0xffffffff
+#define CMDQ_TIMEOUT_DEFAULT	1000
+
+/* GCE thread priority */
+#define CMDQ_THR_PRIO_LOWEST	0
+#define CMDQ_THR_PRIO_1		1
+#define CMDQ_THR_PRIO_2		2
+#define CMDQ_THR_PRIO_3		3
+#define CMDQ_THR_PRIO_4		4
+#define CMDQ_THR_PRIO_5		5
+#define CMDQ_THR_PRIO_6		6
+#define CMDQ_THR_PRIO_HIGHEST	7
+
+/* CPR count in 32bit register */
+#define GCE_CPR_COUNT		1312
+
+/* GCE subsys table */
+//#define SUBSYS_1300XXXX		0
+#define SUBSYS_1400XXXX		0	//MMSYS
+#define SUBSYS_1401XXXX		1	//MMSYS
+#define SUBSYS_1402XXXX		2	//MMSYS
+#define SUBSYS_1F80XXXX		3	//MDP
+#define SUBSYS_1F81XXXX		4	//MDP
+#define SUBSYS_1600XXXX		5
+#define SUBSYS_1601XXXX		6
+#define SUBSYS_1602XXXX		7
+#define SUBSYS_1E80XXXX		8
+#define SUBSYS_1E90XXXX		9
+#define SUBSYS_1E98XXXX		10
+#define SUBSYS_1E99XXXX		11
+#define SUBSYS_1EA0XXXX		12
+#define SUBSYS_1501XXXX		13
+#define SUBSYS_1502XXXX		14
+#define SUBSYS_1581XXXX		15
+#define SUBSYS_1582XXXX		16
+#define SUBSYS_1700XXXX		17
+#define SUBSYS_1701XXXX		18
+#define SUBSYS_1702XXXX		19
+#define SUBSYS_1703XXXX		20
+#define SUBSYS_1706XXXX		21
+#define SUBSYS_1A00XXXX		22
+#define SUBSYS_1A01XXXX		23
+#define SUBSYS_1A03XXXX		24
+#define SUBSYS_1A04XXXX		25
+#define SUBSYS_1A05XXXX		26
+#define SUBSYS_1A06XXXX		27
+#define SUBSYS_1A09XXXX		28
+#define SUBSYS_1A0AXXXX		29
+#define SUBSYS_NO_SUPPORT	99
+
+/* GCE General Purpose Register (GPR) support
+ * Leave note for scenario usage here
+ */
+/* GCE: write mask */
+#define GCE_GPR_R00		0x00
+#define GCE_GPR_R01		0x01
+/* MDP: P1: JPEG dest */
+#define GCE_GPR_R02		0x02
+#define GCE_GPR_R03		0x03
+/* MDP: PQ color */
+#define GCE_GPR_R04		0x04
+/* MDP: 2D sharpness */
+#define GCE_GPR_R05		0x05
+/* DISP: poll esd */
+#define GCE_GPR_R06		0x06
+#define GCE_GPR_R07		0x07
+/* MDP: P4: 2D sharpness dst */
+#define GCE_GPR_R08		0x08
+#define GCE_GPR_R09		0x09
+/* VCU: poll with timeout for GPR timer */
+#define GCE_GPR_R10		0x0a
+#define GCE_GPR_R11		0x0b
+/* CMDQ: debug */
+#define GCE_GPR_R12		0x0c
+#define GCE_GPR_R13		0x0d
+/* CMDQ: P7: debug */
+#define GCE_GPR_R14		0x0e
+#define GCE_GPR_R15		0x0f
+
+/* GCE-D hardware events */
+#define CMDQ_EVENT_MMLSYS_MDP_RDMA0_SOF	0
+#define CMDQ_EVENT_MMLSYS_MDP_RDMA1_SOF	1
+#define CMDQ_EVENT_MMLSYS_MDP_WROT0_SOF	2
+#define CMDQ_EVENT_MMLSYS_MDP_WROT1_SOF	3
+#define CMDQ_EVENT_MMLSYS_MDP_RDMA2_SOF	4
+#define CMDQ_EVENT_MMLSYS_MDP_RDMA3_SOF	5
+#define CMDQ_EVENT_MMLSYS_MDP_DLI_ASYNC0_SOF	6
+#define CMDQ_EVENT_MMLSYS_MDP_DLI_ASYNC1_SOF	7
+#define CMDQ_EVENT_MMLSYS_MDP_DLO_ASYNC0_SOF	8
+#define CMDQ_EVENT_MMLSYS_MDP_DLO_ASYNC1_SOF	9
+#define CMDQ_EVENT_MMLSYS_MDP_WROT2_SOF	10
+#define CMDQ_EVENT_MMLSYS_MDP_WROT3_SOF	11
+#define CMDQ_EVENT_MMLSYS_MDP_DLI_ASYNC3_SOF	12
+#define CMDQ_EVENT_MMLSYS_MDP_DLO_ASYNC2_SOF	13
+#define CMDQ_EVENT_MMLSYS_MDP_DLO_ASYNC3_SOF	14
+#define CMDQ_EVENT_MMLSYS_MDP_WROT3_FRAME_DONE	15
+#define CMDQ_EVENT_MMLSYS_MDP_WROT2_FRAME_DONE	16
+#define CMDQ_EVENT_MMLSYS_MDP_WROT1_FRAME_DONE	17
+#define CMDQ_EVENT_MMLSYS_MDP_WROT0_FRAME_DONE	18
+#define CMDQ_EVENT_MMLSYS_MDP_TDSHP1_FRAME_DONE	19
+#define CMDQ_EVENT_MMLSYS_MDP_TDSHP0_FRAME_DONE	20
+#define CMDQ_EVENT_MMLSYS_MDP_RSZ3_FRAME_DONE	21
+#define CMDQ_EVENT_MMLSYS_MDP_RSZ2_FRAME_DONE	22
+#define CMDQ_EVENT_MMLSYS_MDP_RSZ1_FRAME_DONE	23
+#define CMDQ_EVENT_MMLSYS_MDP_RSZ0_FRAME_DONE	24
+#define CMDQ_EVENT_MMLSYS_MDP_RDMA3_FRAME_DONE	25
+#define CMDQ_EVENT_MMLSYS_MDP_RDMA2_FRAME_DONE	26
+#define CMDQ_EVENT_MMLSYS_MDP_RDMA1_FRAME_DONE	27
+#define CMDQ_EVENT_MMLSYS_MDP_RDMA0_FRAME_DONE	28
+#define CMDQ_EVENT_MMLSYS_MDP_HDR1_FRAME_DONE	29
+#define CMDQ_EVENT_MMLSYS_MDP_HDR0_FRAME_DONE	30
+#define CMDQ_EVENT_MMLSYS_MDP_FG1_FRAME_DONE	31
+#define CMDQ_EVENT_MMLSYS_MDP_FG0_FRAME_DONE	32
+#define CMDQ_EVENT_MMLSYS_MDP_COLOR1_FRAME_DONE	33
+#define CMDQ_EVENT_MMLSYS_MDP_COLOR0_FRAME_DONE	34
+#define CMDQ_EVENT_MMLSYS_MDP_BIRSZ1_FRAME_DONE	35
+#define CMDQ_EVENT_MMLSYS_MDP_BIRSZ0_FRAME_DONE	36
+#define CMDQ_EVENT_MMLSYS_MDP_AAL1_FRAME_DONE	37
+#define CMDQ_EVENT_MMLSYS_MDP_AAL0_FRAME_DONE	38
+#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_0	39
+#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_1	40
+#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_2	41
+#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_3	42
+#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_4	43
+#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_5	44
+#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_6	45
+#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_7	46
+#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_8	47
+#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_9	48
+#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_10	49
+#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_11	50
+#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_12	51
+#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_13	52
+#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_14	53
+#define CMDQ_EVENT_MMLSYS_STREAM_DONE_ENG_EVENT_15	54
+#define CMDQ_EVENT_MMLSYS_MDP_WROT3_SW_RST_DONE_ENG_EVENT	55
+#define CMDQ_EVENT_MMLSYS_MDP_WROT2_SW_RST_DONE_ENG_EVENT	56
+#define CMDQ_EVENT_MMLSYS_MDP_WROT1_SW_RST_DONE_ENG_EVENT	57
+#define CMDQ_EVENT_MMLSYS_MDP_WROT0_SW_RST_DONE_ENG_EVENT	58
+#define CMDQ_EVENT_MMLSYS_MDP_RDMA3_SW_RST_DONE_ENG_EVENT	59
+#define CMDQ_EVENT_MMLSYS_MDP_RDMA2_SW_RST_DONE_ENG_EVENT	60
+#define CMDQ_EVENT_MMLSYS_MDP_RDMA1_SW_RST_DONE_ENG_EVENT	61
+#define CMDQ_EVENT_MMLSYS_MDP_RDMA0_SW_RST_DONE_ENG_EVENT	62
+#define CMDQ_EVENT_MMLSYS_BUF_UNDERRUN_ENG_EVENT_0	63
+#define CMDQ_EVENT_MMLSYS_BUF_UNDERRUN_ENG_EVENT_1	64
+#define CMDQ_EVENT_MMLSYS_BUF_UNDERRUN_ENG_EVENT_2	65
+#define CMDQ_EVENT_DISPSYS_DISP_OVL0_4L_SOF	256
+#define CMDQ_EVENT_DISPSYS_DISP_OVL1_4L_SOF	257
+#define CMDQ_EVENT_DISPSYS_VPP_RSZ0_SOF	258
+#define CMDQ_EVENT_DISPSYS_VPP_RSZ1_SOF	259
+#define CMDQ_EVENT_DISPSYS_DISP_RDMA0_SOF	260
+#define CMDQ_EVENT_DISPSYS_DISP_RDMA1_SOF	261
+#define CMDQ_EVENT_DISPSYS_DISP_COLOR0_SOF	262
+#define CMDQ_EVENT_DISPSYS_DISP_COLOR1_SOF	263
+#define CMDQ_EVENT_DISPSYS_DISP_CCORR0_SOF	264
+#define CMDQ_EVENT_DISPSYS_DISP_CCORR1_SOF	265
+#define CMDQ_EVENT_DISPSYS_DISP_CCORR2_SOF	266
+#define CMDQ_EVENT_DISPSYS_DISP_CCORR3_SOF	267
+#define CMDQ_EVENT_DISPSYS_DISP_AAL0_SOF	268
+#define CMDQ_EVENT_DISPSYS_DISP_AAL1_SOF	269
+#define CMDQ_EVENT_DISPSYS_DISP_GAMMA0_SOF	270
+#define CMDQ_EVENT_DISPSYS_DISP_GAMMA1_SOF	271
+#define CMDQ_EVENT_DISPSYS_DISP_DITHER0_SOF	272
+#define CMDQ_EVENT_DISPSYS_DISP_DITHER1_SOF	273
+#define CMDQ_EVENT_DISPSYS_VPP_MERGE0_SOF	274
+#define CMDQ_EVENT_DISPSYS_DISP_DSC_WRAP0_CORE0_SOF	275
+#define CMDQ_EVENT_DISPSYS_DISP_DSC_WRAP0_CORE1_SOF	276
+#define CMDQ_EVENT_DISPSYS_DISP_DVO0_SOF	277
+#define CMDQ_EVENT_DISPSYS_DISP_DSI0_SOF	278
+#define CMDQ_EVENT_DISPSYS_DP_INTF0_SOF	279
+#define CMDQ_EVENT_DISPSYS_DPI0_SOF	280
+#define CMDQ_EVENT_DISPSYS_DISP_WDMA0_SOF	281
+#define CMDQ_EVENT_DISPSYS_DISP_WDMA1_SOF	282
+#define CMDQ_EVENT_DISPSYS_DISP_PWM0_SOF	283
+#define CMDQ_EVENT_DISPSYS_DISP_PWM1_SOF	284
+#define CMDQ_EVENT_DISPSYS_DISP_OVL0_4L_FRAME_DONE	285
+#define CMDQ_EVENT_DISPSYS_DISP_OVL1_4L_FRAME_DONE	286
+#define CMDQ_EVENT_DISPSYS_VPP_RSZ0_FRAME_DONE	287
+#define CMDQ_EVENT_DISPSYS_VPP_RSZ1_FRAME_DONE	288
+#define CMDQ_EVENT_DISPSYS_DISP_RDMA0_FRAME_DONE	289
+#define CMDQ_EVENT_DISPSYS_DISP_RDMA1_FRAME_DONE	290
+#define CMDQ_EVENT_DISPSYS_DISP_COLOR0_FRAME_DONE	291
+#define CMDQ_EVENT_DISPSYS_DISP_COLOR1_FRAME_DONE	292
+#define CMDQ_EVENT_DISPSYS_DISP_CCORR0_FRAME_DONE	293
+#define CMDQ_EVENT_DISPSYS_DISP_CCORR1_FRAME_DONE	294
+#define CMDQ_EVENT_DISPSYS_DISP_CCORR2_FRAME_DONE	295
+#define CMDQ_EVENT_DISPSYS_DISP_CCORR3_FRAME_DONE	296
+#define CMDQ_EVENT_DISPSYS_DISP_AAL0_FRAME_DONE	297
+#define CMDQ_EVENT_DISPSYS_DISP_AAL1_FRAME_DONE	298
+#define CMDQ_EVENT_DISPSYS_DISP_GAMMA0_FRAME_DONE	299
+#define CMDQ_EVENT_DISPSYS_DISP_GAMMA1_FRAME_DONE	300
+#define CMDQ_EVENT_DISPSYS_DISP_DITHER0_FRAME_DONE	301
+#define CMDQ_EVENT_DISPSYS_DISP_DITHER1_FRAME_DONE	302
+#define CMDQ_EVENT_DISPSYS_VPP_MERGE0_FRAME_DONE	303
+#define CMDQ_EVENT_DISPSYS_DISP_DSC_WRAP0_CORE0_FRAME_DONE	304
+#define CMDQ_EVENT_DISPSYS_DISP_DSC_WRAP0_CORE1_FRAME_DONE	305
+#define CMDQ_EVENT_DISPSYS_DISP_DVO0_FRAME_DONE	306
+#define CMDQ_EVENT_DISPSYS_DISP_DSI0_FRAME_DONE	307
+#define CMDQ_EVENT_DISPSYS_DP_INTF0_FRAME_DONE	308
+#define CMDQ_EVENT_DISPSYS_DPI0_FRAME_DONE	309
+#define CMDQ_EVENT_DISPSYS_DISP_WDMA0_FRAME_DONE	310
+#define CMDQ_EVENT_DISPSYS_DISP_WDMA1_FRAME_DONE	311
+#define CMDQ_EVENT_DISPSYS_MUTEX0_BUF_UNDERRUN_EVENT0	326
+#define CMDQ_EVENT_DISPSYS_MUTEX0_BUF_UNDERRUN_EVENT1	327
+#define CMDQ_EVENT_DISPSYS_MUTEX0_BUF_UNDERRUN_EVENT2	328
+#define CMDQ_EVENT_DISPSYS_MUTEX0_BUF_UNDERRUN_EVENT3	329
+#define CMDQ_EVENT_DISPSYS_MUTEX0_BUF_UNDERRUN_EVENT4	330
+#define CMDQ_EVENT_DISPSYS_MUTEX0_BUF_UNDERRUN_EVENT5	331
+#define CMDQ_EVENT_DISPSYS_MUTEX0_BUF_UNDERRUN_EVENT6	332
+#define CMDQ_EVENT_DISPSYS_MUTEX0_BUF_UNDERRUN_EVENT7	333
+#define CMDQ_EVENT_VPP_MERGE0_ENG_EVENT	334
+#define CMDQ_EVENT_DISPSYS_DVO0_SEL_ENG_EVENT4	335
+#define CMDQ_EVENT_DISPSYS_DVO0_SEL_ENG_EVENT3	336
+#define CMDQ_EVENT_DISPSYS_DVO0_SEL_ENG_EVENT2	337
+#define CMDQ_EVENT_DISPSYS_DVO0_SEL_ENG_EVENT1	338
+#define CMDQ_EVENT_DISPSYS_DVO0_SEL_ENG_EVENT0	339
+#define CMDQ_EVENT_DISPSYS_DVO0_EXTERNAL_TARGET_VDE_END_EVENT	340
+#define CMDQ_EVENT_DISPSYS_DVO0_EXTERNAL_TARGET_VSYNC_START_EVENT	341
+#define CMDQ_EVENT_DISPSYS_DVO0_INTERNAL_TARGET_LINE0_EVENT	342
+#define CMDQ_EVENT_DISPSYS_DSI_TE_EVENT	343 /*DSI0*/
+#define CMDQ_EVENT_DISPSYS_DSI_DONE_EVENT	344 /*DSI0*/
+#define CMDQ_EVENT_DISPSYS_DSI_TARGET_LINE_EVENT	345 /*DSI0*/
+#define CMDQ_EVENT_DISPSYS_INTF0_SEL_ENG_EVENT4	346
+#define CMDQ_EVENT_DISPSYS_INTF0_SEL_ENG_EVENT3	347
+#define CMDQ_EVENT_DISPSYS_INTF0_SEL_ENG_EVENT2	348
+#define CMDQ_EVENT_DISPSYS_INTF0_SEL_ENG_EVENT1	349
+#define CMDQ_EVENT_DISPSYS_INTF0_SEL_ENG_EVENT0	350
+#define CMDQ_EVENT_DISPSYS_INTF0_EXTERNAL_TARGET_VDE_END_EVENT	351
+#define CMDQ_EVENT_DISPSYS_INTF0_EXTERNAL_TARGET_VSYNC_START_EVENT	352
+#define CMDQ_EVENT_DISPSYS_INTF0_INTERNAL_TARGET_LINE0_EVENT	353
+#define CMDQ_EVENT_DPI0_SEL_ENG_EVENT4	354
+#define CMDQ_EVENT_DPI0_SEL_ENG_EVENT3	355
+#define CMDQ_EVENT_DPI0_SEL_ENG_EVENT2	356
+#define CMDQ_EVENT_DPI0_SEL_ENG_EVENT1	357
+#define CMDQ_EVENT_DPI0_SEL_ENG_EVENT0	358
+#define CMDQ_EVENT_DPI0_EXTERNAL_TARGET_VDE_END_EVENT	359
+#define CMDQ_EVENT_DPI0_EXTERNAL_TARGET_VSYNC_START_EVENT	360
+#define CMDQ_EVENT_DPI0_INTERNAL_TARGET_LINE0_EVENT	361
+#define CMDQ_EVENT_DISPSYS_WDMA0_TARGET_LINE_EVENT	362
+#define CMDQ_EVENT_DISPSYS_WDMA0_SW_RESET_EVENT	363
+#define CMDQ_EVENT_DISPSYS_WDMA1_TARGET_LINE_EVENT	364
+#define CMDQ_EVENT_DISPSYS_WDMA1_SW_RESET_EVENT	365
+#define CMDQ_EVENT_DISPSYS_OVL0_4L_TARGET_LINE_EVENT0	366
+#define CMDQ_EVENT_DISPSYS_OVL0_4L_TARGET_LINE_EVENT1	367
+#define CMDQ_EVENT_DISPSYS_OVL0_4L_TARGET_LINE_EVENT2	368
+#define CMDQ_EVENT_DISPSYS_OVL0_4L_TARGET_LINE_EVENT3	369
+#define CMDQ_EVENT_DISPSYS_OVL0_4L_TARGET_LINE_EVENT4	370
+#define CMDQ_EVENT_DISPSYS_OVL0_4L_TARGET_LINE_EVENT5	371
+#define CMDQ_EVENT_DISPSYS_OVL0_4L_TARGET_LINE_EVENT6	372
+#define CMDQ_EVENT_DISPSYS_OVL0_4L_FRAME_RESET_DONE_EVENT	373
+#define CMDQ_EVENT_DISPSYS_OVL1_4L_TARGET_LINE_EVENT0	374
+#define CMDQ_EVENT_DISPSYS_OVL1_4L_TARGET_LINE_EVENT1	375
+#define CMDQ_EVENT_DISPSYS_OVL1_4L_TARGET_LINE_EVENT2	376
+#define CMDQ_EVENT_DISPSYS_OVL1_4L_TARGET_LINE_EVENT3	377
+#define CMDQ_EVENT_DISPSYS_OVL1_4L_TARGET_LINE_EVENT4	378
+#define CMDQ_EVENT_DISPSYS_OVL1_4L_TARGET_LINE_EVENT5	379
+#define CMDQ_EVENT_DISPSYS_OVL1_4L_TARGET_LINE_EVENT6	380
+#define CMDQ_EVENT_DISPSYS_OVL1_4L_FRAME_RESET_DONE_EVENT	381
+#define CMDQ_EVENT_DISPSYS_DISP_MUTEX0_ENG_EVENT_0  382
+#define CMDQ_EVENT_DISPSYS_DISP_MUTEX0_ENG_EVENT_1  383
+#define CMDQ_EVENT_DISPSYS_DISP_MUTEX0_ENG_EVENT_2	384
+#define CMDQ_EVENT_DISPSYS_DISP_MUTEX0_ENG_EVENT_3	385
+#define CMDQ_EVENT_DISPSYS_DISP_MUTEX0_ENG_EVENT_4	386
+#define CMDQ_EVENT_DISPSYS_DISP_MUTEX0_ENG_EVENT_5	387
+#define CMDQ_EVENT_DISPSYS_DISP_MUTEX0_ENG_EVENT_6	388
+#define CMDQ_EVENT_DISPSYS_DISP_MUTEX0_ENG_EVENT_7	389
+#define CMDQ_EVENT_DISPSYS_DISP_MUTEX0_ENG_EVENT_8	390
+#define CMDQ_EVENT_DISPSYS_DISP_MUTEX0_ENG_EVENT_9	391
+#define CMDQ_EVENT_DISPSYS_DISP_MUTEX0_ENG_EVENT_10	392
+#define CMDQ_EVENT_DISPSYS_DISP_MUTEX0_ENG_EVENT_11	393
+#define CMDQ_EVENT_DISPSYS_DISP_MUTEX0_ENG_EVENT_12	394
+#define CMDQ_EVENT_DISPSYS_DISP_MUTEX0_ENG_EVENT_13	395
+#define CMDQ_EVENT_DISPSYS_DISP_MUTEX0_ENG_EVENT_14	396
+#define CMDQ_EVENT_DISPSYS_DISP_MUTEX0_ENG_EVENT_15	397
+#define CMDQ_EVENT_DISP_RDMA0_GCE_TARGET_LINE_EVENT	398
+#define CMDQ_EVENT_DISP_RDMA1_GCE_TARGET_LINE_EVENT 399
+
+#define CMDQ_EVENT_DISPSYS_DISP_OVL1_4L_ENG_EVENT_6	400
+#define CMDQ_EVENT_DISPSYS_DISP_OVL1_4L_RST_DONE_ENG_EVENT	401
+
+/* GCE-M hardware events */
+#define CMDQ_EVENT_VENC_EVENT_RESERVED                      0
+#define CMDQ_EVENT_VENC_CMDQ_FRAME_DONE                     1
+#define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE                     2
+#define CMDQ_EVENT_VENC_JPGENC_CMDQ_DONE                    3
+#define CMDQ_EVENT_VENC_CMDQ_MB_DONE					    4
+#define CMDQ_EVENT_VENC_CMDQ_12BYTE_CNT_DONE				5
+#define CMDQ_EVENT_VENC_JPGDEC_CMDQ_DONE               6
+#define CMDQ_EVENT_VENC_JPGDEC_INSUFF_CMDQ_DONE				8
+#define CMDQ_EVENT_VENC_CMDQ_WP_2ND_STAGE_DONE              10
+#define CMDQ_EVENT_VENC_CMDQ_WP_3RD_STAGE_DONE              11
+#define CMDQ_EVENT_VENC_CMDQ_PPS_DONE                       12
+#define CMDQ_EVENT_VENC_CMDQ_SPS_DONE                       13
+#define CMDQ_EVENT_VENC_CMDQ_VPS_DONE                       14
+#define CMDQ_EVENT_VENC_CMDQ_SLICE_DONE                     15
+#define CMDQ_EVENT_VENC_EVENT_16                            16
+#define CMDQ_EVENT_VENC_EVENT_17                            17
+#define CMDQ_EVENT_VDEC_LINE_COUNT_THRESHOLD_INTERRUPT      32
+#define CMDQ_EVENT_VDEC_INT                                 33
+#define CMDQ_EVENT_VDEC_PAUSE                               34
+#define CMDQ_EVENT_VDEC_DEC_ERROR                           35
+#define CMDQ_EVENT_VDEC_MC_BUSY_OVERFLOW_OR_MDEC_TIMEOUT	36
+#define CMDQ_EVENT_VDEC_VDEC_DRAM_IDLE                      37
+#define CMDQ_EVENT_VDEC_INI_FETCH_RDY                       38
+#define CMDQ_EVENT_VDEC_PROCESS_FLAG                        39
+#define CMDQ_EVENT_VDEC_SEARCH_START_CODE_DONE_OR_CTX_COUNT_DMA_RDY	40
+#define CMDQ_EVENT_VDEC_REF_REORDER_DONE_OR_UPDATE_PROBS_RDY        41
+#define CMDQ_EVENT_VDEC_WP_TBLE_DONE_OR_BOOL_INIT_RDY               42
+#define CMDQ_EVENT_VDEC_COUNT_SRAM_CLR_DONE_AND_CTX_SRAM_CLR_DONE	43
+#define CMDQ_EVENT_GCE_CNT_OP_THRESHOLD                             47
+#define CMDQ_EVENT_CAM_EVENT_0                                      64
+#define CMDQ_EVENT_CAM_ISP_FRAME_DONE_A	65
+#define CMDQ_EVENT_CAM_ISP_FRAME_DONE_B	66
+#define CMDQ_EVENT_CAM_ISP_FRAME_DONE_C	67
+#define CMDQ_EVENT_CAM_CAMSV0_PASS1_DONE	68
+#define CMDQ_EVENT_CAM_CAMSV02_PASS1_DONE	69
+#define CMDQ_EVENT_CAM_CAMSV1_PASS1_DONE	70
+#define CMDQ_EVENT_CAM_CAMSV2_PASS1_DONE	71
+#define CMDQ_EVENT_CAM_CAMSV3_PASS1_DONE	72
+#define CMDQ_EVENT_CAM_CAMSV4_PASS1_DONE	73
+#define CMDQ_EVENT_CAM_CAMSV42_PASS1_DONE	74
+#define CMDQ_EVENT_CAM_MRAW_0_PASS1_DONE	75
+#define CMDQ_EVENT_CAM_MRAW_1_PASS1_DONE	76
+#define CMDQ_EVENT_CAM_SENINF_CAM0_FIFO_FULL	77
+#define CMDQ_EVENT_CAM_SENINF_CAM1_FIFO_FULL	78
+#define CMDQ_EVENT_CAM_SENINF_CAM2_FIFO_FULL	79
+#define CMDQ_EVENT_CAM_SENINF_CAM3_FIFO_FULL	80
+#define CMDQ_EVENT_CAM_SENINF_CAM4_FIFO_FULL	81
+#define CMDQ_EVENT_CAM_SENINF_CAM5_FIFO_FULL	82
+#define CMDQ_EVENT_CAM_SENINF_CAM6_FIFO_FULL	83
+#define CMDQ_EVENT_CAM_SENINF_CAM7_FIFO_FULL	84
+#define CMDQ_EVENT_CAM_SENINF_CAM8_FIFO_FULL	85
+#define CMDQ_EVENT_CAM_SENINF_CAM9_FIFO_FULL	86
+#define CMDQ_EVENT_CAM_SENINF_CAM10_FIFO_FULL	87
+#define CMDQ_EVENT_CAM_SENINF_CAM11_FIFO_FULL	88
+#define CMDQ_EVENT_CAM_SENINF_CAM12_FIFO_FULL	89
+#define CMDQ_EVENT_CAM_TG_OVRUN_A_INT	90
+#define CMDQ_EVENT_CAM_DMA_R1_ERROR_A_INT	91
+#define CMDQ_EVENT_CAM_TG_OVRUN_B_INT	92
+#define CMDQ_EVENT_CAM_DMA_R1_ERROR_B_INT	93
+#define CMDQ_EVENT_CAM_TG_OVRUN_C_INT	94
+#define CMDQ_EVENT_CAM_DMA_R1_ERROR_C_INT	95
+#define CMDQ_EVENT_CAM_TG_OVRUN_INT	96
+#define CMDQ_EVENT_CAM_DMA_R1_ERROR_M0_INT	97
+#define CMDQ_EVENT_CAM_TG_GRABERR_M0_INT	98
+#define CMDQ_EVENT_CAM_TG_GRABERR_M1_INT	99
+#define CMDQ_EVENT_CAM_TG_GRABERR_A_INT	100
+#define CMDQ_EVENT_CAM_CQ_VR_SNAP_A_INT	101
+#define CMDQ_EVENT_CAM_TG_GRABERR_B_INT	102
+#define CMDQ_EVENT_CAM_CQ_VR_SNAP_B_INT	103
+#define CMDQ_EVENT_CAM_TG_GRABERR_C_INT	104
+#define CMDQ_EVENT_CAM_CQ_VR_SNAP_C_INT	105
+#define CMDQ_EVENT_CAM_PDA_IRQO_EVENT_DONE_D1	106
+#define CMDQ_EVENT_CAM_SENINF_CAM13_FIFO_FULL	107
+#define CMDQ_EVENT_CAM_SENINF_CAM14_FIFO_FULL	108
+#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_0	129
+#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_1	130
+#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_2	131
+#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_3	132
+#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_4	133
+#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_5	134
+#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_6	135
+#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_7	136
+#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_8	137
+#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_9	138
+#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_10	139
+#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_11	140
+#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_12	141
+#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_13	142
+#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_14	143
+#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_15	144
+#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_16	145
+#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_17	146
+#define CMDQ_EVENT_IMG1_DIP_FRAME_DONE_P2_18	147
+#define CMDQ_EVENT_IMG1_DIP_DMA_ERR_EVENT	148
+#define CMDQ_EVENT_IMG1_AMD_FRAME_DONE	149
+#define CMDQ_EVENT_IMG1_MFB_DONE_LINK_MISC	150
+#define CMDQ_EVENT_IMG1_WPE_A_DONE_LINK_MISC	151
+#define CMDQ_EVENT_IMG1_MSS_DONE_LINK_MISC	152
+#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_0	161
+#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_1	162
+#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_2	163
+#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_3	164
+#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_4	165
+#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_5	166
+#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_6	167
+#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_7	168
+#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_8	169
+#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_9	170
+#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_10	171
+#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_11	172
+#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_12	173
+#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_13	174
+#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_14	175
+#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_15	176
+#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_16	177
+#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_17	178
+#define CMDQ_EVENT_IMG2_DIP_FRAME_DONE_P2_18	179
+#define CMDQ_EVENT_IMG2_DIP_DMA_ERR_EVENT	180
+#define CMDQ_EVENT_IMG2_AMD_FRAME_DONE	181
+#define CMDQ_EVENT_IMG2_MFB_DONE_LINK_MISC	182
+#define CMDQ_EVENT_IMG2_WPE_A_DONE_LINK_MISC	183
+#define CMDQ_EVENT_IMG2_MSS_DONE_LINK_MISC	184
+#define CMDQ_EVENT_IPE_FDVT_DONE	193
+#define CMDQ_EVENT_IPE_FE_DONE	194
+#define CMDQ_EVENT_IPE_RSC_DONE	195
+#define CMDQ_EVENT_IPE_DVS_DONE_ASYNC_SHOT	196
+#define CMDQ_EVENT_IPE_DVP_DONE_ASYNC_SHOT	197
+
+#define CMDQ_EVENT_GCE_SMI_ALL_EVENT_0 898
+#define CMDQ_EVENT_GCE_SMI_ALL_EVENT_1 899
+#define CMDQ_EVENT_GCE_SMI_ALL_EVENT_2 900
+
+/* end of hw event and begin of sw token */
+#define CMDQ_MAX_HW_EVENT				512
+
+/* CMDQ sw tokens
+ * Following definitions are gce sw token which may use by clients
+ * event operation API.
+ * Note that token 512 to 639 may set secure
+ */
+
+/* begin of GCE-D sw token */
+/* MML sw tokens */
+#define CMDQ_SYNC_TOKEN_MML_BUFA			661
+#define CMDQ_SYNC_TOKEN_MML_BUFB			662
+#define CMDQ_SYNC_TOKEN_MML_BUF_NEXT			663
+#define CMDQ_SYNC_TOKEN_MML_IR_MML_READY		664
+#define CMDQ_SYNC_TOKEN_MML_IR_DISP_READY		665
+#define CMDQ_SYNC_TOKEN_MML_MML_STOP			666
+#define CMDQ_SYNC_TOKEN_MML_PIPE0			667
+#define CMDQ_SYNC_TOKEN_MML_PIPE1			668
+#define CMDQ_SYNC_TOKEN_MML_PIPE1_NEXT			669
+#define CMDQ_SYNC_TOKEN_MML_APU_START           670
+
+/* Config thread notify trigger thread */
+#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY			640
+/* Trigger thread notify config thread */
+#define CMDQ_SYNC_TOKEN_STREAM_EOF			641
+/* Block Trigger thread until the ESD check finishes. */
+#define CMDQ_SYNC_TOKEN_ESD_EOF				642
+#define CMDQ_SYNC_TOKEN_STREAM_BLOCK			643
+/* check CABC setup finish */
+#define CMDQ_SYNC_TOKEN_CABC_EOF			644
+
+/*VFP period token for Msync*/
+#define CMDQ_SYNC_TOKEN_VFP_PERIOD			645
+/* SW sync token for dual display */
+#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY_1			694
+#define CMDQ_SYNC_TOKEN_STREAM_EOF_1			695
+#define CMDQ_SYNC_TOKEN_ESD_EOF_1			696
+#define CMDQ_SYNC_TOKEN_STREAM_BLOCK_1			697
+#define CMDQ_SYNC_TOKEN_CABC_EOF_1			698
+
+/* GPR access tokens (for HW register backup)
+ * There are 15 32-bit GPR, 3 GPR form a set
+ * (64-bit for address, 32-bit for value)
+ * MUST NOT CHANGE, these tokens sync with MDP
+ */
+#define CMDQ_SYNC_TOKEN_GPR_SET_0			700
+#define CMDQ_SYNC_TOKEN_GPR_SET_1			701
+#define CMDQ_SYNC_TOKEN_GPR_SET_2			702
+#define CMDQ_SYNC_TOKEN_GPR_SET_3			703
+#define CMDQ_SYNC_TOKEN_GPR_SET_4			704
+
+#define CMDQ_SYNC_TOKEN_TE_0				705
+#define CMDQ_SYNC_TOKEN_PREFETCH_TE_0			706
+#define CMDQ_SYNC_TOKEN_VIDLE_POWER_ON			707
+#define CMDQ_SYNC_TOKEN_CHECK_TRIGGER_MERGE		708
+
+/* Resource lock event to control resource in GCE thread */
+#define CMDQ_SYNC_RESOURCE_WROT0			710
+#define CMDQ_SYNC_RESOURCE_WROT1			711
+
+/* HW TRACE sw token */
+#define CMDQ_SYNC_TOKEN_HW_TRACE_WAIT			712
+#define CMDQ_SYNC_TOKEN_HW_TRACE_LOCK			713
+
+/* SW sync token for dual display */
+#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY_3			714
+#define CMDQ_SYNC_TOKEN_STREAM_EOF_3			715
+#define CMDQ_SYNC_TOKEN_ESD_EOF_3			716
+#define CMDQ_SYNC_TOKEN_STREAM_BLOCK_3			717
+#define CMDQ_SYNC_TOKEN_CABC_EOF_3			718
+/* end of GCE-D sw token */
+
+/* begin of GCE-M sw token */
+/* IMGSYS_POOL */
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_1		514
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_2		515
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_3		516
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_4		517
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_5		518
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_6		519
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_7		520
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_8		521
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_9		522
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_10		523
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_11		524
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_12		525
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_13		526
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_14		527
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_15		528
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_16		529
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_17		530
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_18		531
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_19		532
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_20		533
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_21		534
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_22		535
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_23		536
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_24		537
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_25		538
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_26		539
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_27		540
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_28		541
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_29		542
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_30		543
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_31		544
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_32		545
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_33		546
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_34		547
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_35		548
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_36		549
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_37		550
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_38		551
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_39		552
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_40		553
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_41		554
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_42		555
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_43		556
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_44		557
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_45		558
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_46		559
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_47		560
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_48		561
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_49		562
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_50		563
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_51		564
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_52		565
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_53		566
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_54		567
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_55		568
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_56		569
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_57		570
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_58		571
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_59		572
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_60		573
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_61		574
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_62		575
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_63		576
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_64		577
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_65		578
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_66		579
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_67		580
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_68		581
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_69		582
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_70		583
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_71		584
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_72		585
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_73		586
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_74		587
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_75		588
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_76		589
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_77		590
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_78		591
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_79		592
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_80		593
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_81		594
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_82		595
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_83		596
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_84		597
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_85		598
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_86		599
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_87		600
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_88		601
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_89		602
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_90		603
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_91		604
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_92		605
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_93		606
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_94		607
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_95		608
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_96		609
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_97		610
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_98		611
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_99		612
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_100		613
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_101		614
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_102		615
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_103		616
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_104		617
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_105		618
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_106		619
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_107		620
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_108		621
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_109		622
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_110		623
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_111		624
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_112		625
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_113		626
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_114		627
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_115		628
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_116		629
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_117		630
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_118		631
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_119		632
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_120		633
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_121		634
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_122		635
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_123		636
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_124		637
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_125		638
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_126		639
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_127		640
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_128		641
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_129		642
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_130		643
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_131		644
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_132		645
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_133		646
+
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_134		694
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_135		695
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_136		696
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_137		697
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_138		698
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_139		699
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_140		700
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_141		701
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_142		702
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_143		703
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_144		704
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_145		705
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_146		706
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_147		707
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_148		708
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_149		709
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_150		710
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_151		711
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_152		714
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_153		715
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_154		716
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_155		717
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_156		718
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_157		719
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_158		720
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_159		721
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_160		722
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_161		723
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_162		724
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_163		725
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_164		726
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_165		727
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_166		728
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_167		729
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_168		730
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_169		731
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_170		732
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_171		733
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_172		734
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_173		735
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_174		736
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_175		737
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_176		738
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_177		739
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_178		740
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_179		741
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_180		742
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_181		743
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_182		744
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_183		745
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_184		746
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_185		747
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_186		748
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_187		749
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_188		750
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_189		751
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_190		752
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_191		753
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_192		754
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_193		755
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_194		756
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_195		757
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_196		758
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_197		759
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_198		760
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_199		761
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_200		762
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_201		763
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_202		764
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_203		765
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_204		766
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_205		767
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_206		784
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_207		785
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_208		786
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_209		787
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_210		788
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_211		789
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_212		790
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_213		791
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_214		792
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_215		793
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_216		794
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_217		795
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_218		796
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_219		797
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_220		798
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_221		799
+
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_222		833
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_223		834
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_224		835
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_225		836
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_226		837
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_227		838
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_228		839
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_229		840
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_230		841
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_231		842
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_232		843
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_233		844
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_234		845
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_235		846
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_236		847
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_237		848
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_238		849
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_239		850
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_240		851
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_241		852
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_242		853
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_243		854
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_244		855
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_245		856
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_246		857
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_247		858
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_248		859
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_249		860
+#define	CMDQ_SYNC_TOKEN_IMGSYS_POOL_250		861
+
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_251		901
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_252		902
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_253		903
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_254		904
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_255		905
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_256		906
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_257		907
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_258		908
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_259		909
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_260		910
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_261		911
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_262		912
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_263		913
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_264		914
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_265		915
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_266		916
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_267		917
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_268		918
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_269		919
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_270		920
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_271		921
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_272		922
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_273		923
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_274		924
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_275		925
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_276		926
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_277		927
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_278		928
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_279		929
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_280		930
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_281		931
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_282		932
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_283		933
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_284		934
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_285		935
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_286		936
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_287		937
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_288		938
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_289		939
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_290		940
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_291		941
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_292		942
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_293		943
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_294		944
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_295		945
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_296		946
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_297		947
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_298		948
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_299		949
+#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_300		950
+
+/* ISP sw token */
+#define CMDQ_SYNC_TOKEN_MSS			665
+#define CMDQ_SYNC_TOKEN_MSF			666
+/* end of GCE-M sw token */
+
+/* begin of common sw token */
+
+/* Notify normal CMDQ there are some secure task done
+ * MUST NOT CHANGE, this token sync with secure world
+ */
+#define CMDQ_SYNC_SECURE_THR_EOF			647
+
+/* CMDQ use sw token */
+#define CMDQ_SYNC_TOKEN_USER_0				649
+#define CMDQ_SYNC_TOKEN_USER_1				650
+#define CMDQ_SYNC_TOKEN_POLL_MONITOR			651
+#define CMDQ_SYNC_TOKEN_TPR_LOCK			652
+
+/* TZMP sw token */
+#define CMDQ_SYNC_TOKEN_TZMP_DISP_WAIT			653
+#define CMDQ_SYNC_TOKEN_TZMP_DISP_SET			654
+#define CMDQ_SYNC_TOKEN_TZMP_ISP_WAIT			655
+#define CMDQ_SYNC_TOKEN_TZMP_ISP_SET			656
+#define CMDQ_SYNC_TOKEN_TZMP_AIE_WAIT			657
+#define CMDQ_SYNC_TOKEN_TZMP_AIE_SET			658
+#define CMDQ_SYNC_TOKEN_TZMP_ADL_WAIT			659
+#define CMDQ_SYNC_TOKEN_TZMP_ADL_SET			660
+
+/* PREBUILT sw token */
+#define CMDQ_SYNC_TOKEN_PREBUILT_MDP_LOCK		682
+#define CMDQ_SYNC_TOKEN_PREBUILT_MML_LOCK		685
+#define CMDQ_SYNC_TOKEN_PREBUILT_VFMT_LOCK		688
+#define CMDQ_SYNC_TOKEN_PREBUILT_DISP_LOCK		691
+#define CMDQ_SYNC_TOKEN_DISP_VA_START			692
+#define CMDQ_SYNC_TOKEN_DISP_VA_END			693
+
+/* Notify normal CMDQ there are some secure task done
+ * MUST NOT CHANGE, this token sync with secure world
+ */
+#define CMDQ_SYNC_TOKEN_SECURE_THR_EOF			855
+
+/* sw token should use the unused event id from 0 to 1023 */
+#define CMDQ_SYNC_TOKEN_INVALID				(-1)
+
+/* event for gpr timer, used in sleep and poll with timeout */
+#define CMDQ_TOKEN_GPR_TIMER_R0				994
+#define CMDQ_TOKEN_GPR_TIMER_R1				995
+#define CMDQ_TOKEN_GPR_TIMER_R2				996
+#define CMDQ_TOKEN_GPR_TIMER_R3				997
+#define CMDQ_TOKEN_GPR_TIMER_R4				998
+#define CMDQ_TOKEN_GPR_TIMER_R5				999
+#define CMDQ_TOKEN_GPR_TIMER_R6				1000
+#define CMDQ_TOKEN_GPR_TIMER_R7				1001
+#define CMDQ_TOKEN_GPR_TIMER_R8				1002
+#define CMDQ_TOKEN_GPR_TIMER_R9				1003
+#define CMDQ_TOKEN_GPR_TIMER_R10			1004
+#define CMDQ_TOKEN_GPR_TIMER_R11			1005
+#define CMDQ_TOKEN_GPR_TIMER_R12			1006
+#define CMDQ_TOKEN_GPR_TIMER_R13			1007
+#define CMDQ_TOKEN_GPR_TIMER_R14			1008
+#define CMDQ_TOKEN_GPR_TIMER_R15			1009
+
+#define CMDQ_EVENT_MAX					0x3ff
+/* end of common sw token */
+/* CMDQ sw tokens END */
+
+#endif
-- 
2.46.0

[PATCH v4 3/4] mailbox: mtk-cmdq: Add CMDQ driver support for mt8189

[Xiandong Wang]

Add CMDQ driver support for mt8189 by adding its compatible and
driver data in CMDQ driver.

These changes ensure correct GCE operation for MT8189.

Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.com>
---
 drivers/mailbox/mtk-cmdq-mailbox.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index a0f1616d9e42..54d008ebdf33 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -838,6 +838,15 @@ static const struct gce_plat gce_plat_mt8188 = {
 	.gce_num = 2
 };
 
+static const struct gce_plat gce_plat_mt8189 = {
+	.thread_nr = 32,
+	.shift = 3,
+	.mminfra_offset = 0x40000000, /* 1GB */
+	.control_by_sw = false,
+	.sw_ddr_en = true,
+	.gce_num = 2
+};
+
 static const struct gce_plat gce_plat_mt8192 = {
 	.thread_nr = 24,
 	.shift = 3,
@@ -858,6 +867,7 @@ static const struct of_device_id cmdq_of_ids[] = {
 	{.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_mt8183},
 	{.compatible = "mediatek,mt8186-gce", .data = (void *)&gce_plat_mt8186},
 	{.compatible = "mediatek,mt8188-gce", .data = (void *)&gce_plat_mt8188},
+	{.compatible = "mediatek,mt8189-gce", .data = (void *)&gce_plat_mt8189},
 	{.compatible = "mediatek,mt8192-gce", .data = (void *)&gce_plat_mt8192},
 	{.compatible = "mediatek,mt8195-gce", .data = (void *)&gce_plat_mt8195},
 	{}
-- 
2.46.0

[PATCH v4 4/4] mailbox: mtk-cmdq: Fix clock handling using clk_bulk_prepare_enable

[Xiandong Wang]

On MT8189, the GCE clock is mounted on the MMInfra clock, so it is
necessary to enable or disable the parent clock before handling  the GCE
clock to ensure correct switching for GCE usage.

Replace clk_bulk_enable and clk_bulk_disable with
clk_bulk_prepare_enable and clk_bulk_disable_unprepare in  suspend and
resume, so both the module clock and its parent clock can be enabled or
disabled properly.

This change modifies the clock API used for suspend and resume
to ensure correct module and parent clock handling on MT8189.

Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.com>
---
 drivers/mailbox/mtk-cmdq-mailbox.c | 14 ++++----------
 1 file changed, 4 insertions(+), 10 deletions(-)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index 54d008ebdf33..98c9742ea6f4 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -211,7 +211,7 @@ static void cmdq_init(struct cmdq *cmdq)
 {
 	int i;
 
-	WARN_ON(clk_bulk_enable(cmdq->pdata->gce_num, cmdq->clocks));
+	WARN_ON(clk_bulk_prepare_enable(cmdq->pdata->gce_num, cmdq->clocks));
 
 	cmdq_vm_toggle(cmdq, true);
 	cmdq_gctl_value_toggle(cmdq, true);
@@ -219,7 +219,7 @@ static void cmdq_init(struct cmdq *cmdq)
 	writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
 	for (i = 0; i <= CMDQ_MAX_EVENT; i++)
 		writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
-	clk_bulk_disable(cmdq->pdata->gce_num, cmdq->clocks);
+	clk_bulk_disable_unprepare(cmdq->pdata->gce_num, cmdq->clocks);
 }
 
 static int cmdq_thread_reset(struct cmdq *cmdq, struct cmdq_thread *thread)
@@ -383,7 +383,7 @@ static int cmdq_runtime_resume(struct device *dev)
 	struct cmdq *cmdq = dev_get_drvdata(dev);
 	int ret;
 
-	ret = clk_bulk_enable(cmdq->pdata->gce_num, cmdq->clocks);
+	ret = clk_bulk_prepare_enable(cmdq->pdata->gce_num, cmdq->clocks);
 	if (ret)
 		return ret;
 
@@ -398,7 +398,7 @@ static int cmdq_runtime_suspend(struct device *dev)
 
 	cmdq_gctl_value_toggle(cmdq, false);
 	cmdq_vm_toggle(cmdq, false);
-	clk_bulk_disable(cmdq->pdata->gce_num, cmdq->clocks);
+	clk_bulk_disable_unprepare(cmdq->pdata->gce_num, cmdq->clocks);
 	return 0;
 }
 
@@ -437,12 +437,8 @@ static int cmdq_resume(struct device *dev)
 
 static void cmdq_remove(struct platform_device *pdev)
 {
-	struct cmdq *cmdq = platform_get_drvdata(pdev);
-
 	if (!IS_ENABLED(CONFIG_PM))
 		cmdq_runtime_suspend(&pdev->dev);
-
-	clk_bulk_unprepare(cmdq->pdata->gce_num, cmdq->clocks);
 }
 
 static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
@@ -761,8 +757,6 @@ static int cmdq_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, cmdq);
 
-	WARN_ON(clk_bulk_prepare(cmdq->pdata->gce_num, cmdq->clocks));
-
 	cmdq_init(cmdq);
 
 	err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
-- 
2.46.0

Re: [PATCH v4 1/4] dt-bindings: mailbox: add cmdq yaml for MT8189

[Conor Dooley]

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On Wed, Aug 20, 2025 at 05:38:20PM +0800, Xiandong Wang wrote:
> Add compatible string to support cmdq for MT8189.
> 
> Signed-off-by: Xiandong Wang <xiandong.wang@mediatek.com>

Please look at https://lore.kernel.org/all/20250819-coliseum-unsheathe-0c12a58e65e0@spud/
and reply.

> ---
>  .../devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml        | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
> index 73d6db34d64a..f9718b90d36a 100644
> --- a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
> +++ b/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml
> @@ -23,6 +23,7 @@ properties:
>            - mediatek,mt8183-gce
>            - mediatek,mt8186-gce
>            - mediatek,mt8188-gce
> +          - mediatek,mt8189-gce
>            - mediatek,mt8192-gce
>            - mediatek,mt8195-gce
>            - mediatek,mt8196-gce
> -- 
> 2.46.0
> 

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