From: SungMin Park Add initial device tree support for Axis ARTPEC-8 SoC. This SoC contains 4 Cortex-A53 CPUs and several other peripheral IPs. Signed-off-by: SungMin Park Signed-off-by: SeonGu Kang Signed-off-by: Ravi Patel --- MAINTAINERS | 12 + arch/arm64/Kconfig.platforms | 7 + arch/arm64/boot/dts/exynos/Makefile | 1 + .../boot/dts/exynos/axis/artpec-pinctrl.h | 36 +++ .../boot/dts/exynos/axis/artpec8-pinctrl.dtsi | 120 +++++++++ arch/arm64/boot/dts/exynos/axis/artpec8.dtsi | 244 ++++++++++++++++++ 6 files changed, 420 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h create mode 100644 arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/axis/artpec8.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index 69511c3b2b76..956140fbf639 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3929,6 +3929,18 @@ S: Maintained F: Documentation/devicetree/bindings/sound/axentia,* F: sound/soc/atmel/tse850-pcm5142.c +AXIS ARTPEC ARM64 SoC SUPPORT +M: Jesper Nilsson +M: Lars Persson +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +L: linux-samsung-soc@vger.kernel.org +L: linux-arm-kernel@axis.com +S: Maintained +F: Documentation/devicetree/bindings/clock/axis,artpec*-clock.yaml +F: arch/arm64/boot/dts/exynos/axis/ +F: drivers/clk/samsung/clk-artpec*.c +F: include/dt-bindings/clock/axis,artpec*-clk.h + AXI-FAN-CONTROL HARDWARE MONITOR DRIVER M: Nuno Sá L: linux-hwmon@vger.kernel.org diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 8b76821f190f..48af8b154f7a 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -40,6 +40,13 @@ config ARCH_APPLE This enables support for Apple's in-house ARM SoC family, such as the Apple M1. +config ARCH_ARTPEC + bool "Axis Communications ARTPEC SoC Family" + depends on ARCH_EXYNOS + select ARM_GIC + help + This enables support for the ARMv8 based ARTPEC SoC Family. + menuconfig ARCH_BCM bool "Broadcom SoC Support" diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile index f6f4bc650a94..c1a64cd29078 100644 --- a/arch/arm64/boot/dts/exynos/Makefile +++ b/arch/arm64/boot/dts/exynos/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +subdir-y += axis subdir-y += google dtb-$(CONFIG_ARCH_EXYNOS) += \ diff --git a/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h b/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h new file mode 100644 index 000000000000..70bd1dcac85e --- /dev/null +++ b/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Axis ARTPEC-8 SoC device tree pinctrl constants + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2025 Axis Communications AB. + * https://www.axis.com + */ + +#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ +#define __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ + +#define ARTPEC_PIN_PULL_NONE 0 +#define ARTPEC_PIN_PULL_DOWN 1 +#define ARTPEC_PIN_PULL_UP 3 + +#define ARTPEC_PIN_FUNC_INPUT 0 +#define ARTPEC_PIN_FUNC_OUTPUT 1 +#define ARTPEC_PIN_FUNC_2 2 +#define ARTPEC_PIN_FUNC_3 3 +#define ARTPEC_PIN_FUNC_4 4 +#define ARTPEC_PIN_FUNC_5 5 +#define ARTPEC_PIN_FUNC_6 6 +#define ARTPEC_PIN_FUNC_EINT 0xf +#define ARTPEC_PIN_FUNC_F ARTPEC_PIN_FUNC_EINT + +/* Drive strength for ARTPEC */ +#define ARTPEC_PIN_DRV_SR1 0x8 +#define ARTPEC_PIN_DRV_SR2 0x9 +#define ARTPEC_PIN_DRV_SR3 0xa +#define ARTPEC_PIN_DRV_SR4 0xb +#define ARTPEC_PIN_DRV_SR5 0xc +#define ARTPEC_PIN_DRV_SR6 0xd + +#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ */ diff --git a/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi new file mode 100644 index 000000000000..8d239a70f1b4 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Axis ARTPEC-8 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2025 Axis Communications AB. + * https://www.axis.com + */ + +#include "artpec-pinctrl.h" + +&pinctrl_fsys { + gpe0: gpe0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe1: gpe1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpe2: gpe2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf2: gpf2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf3: gpf3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf4: gpf4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gps0: gps0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gps1: gps1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + serial0_bus: serial0-bus-pins { + samsung,pins = "gpf4-4", "gpf4-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_peric { + gpa0: gpa0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa2: gpa2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk0: gpk0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/axis/artpec8.dtsi b/arch/arm64/boot/dts/exynos/axis/artpec8.dtsi new file mode 100644 index 000000000000..8ee20bf4f680 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/axis/artpec8.dtsi @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Axis ARTPEC-8 SoC device tree source + * + * Copyright (c) 2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2025 Axis Communications AB. + * https://www.axis.com + */ + +#include +#include + +/ { + compatible = "axis,artpec8"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + pinctrl0 = &pinctrl_fsys; + pinctrl1 = &pinctrl_peric; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + cpu-idle-states = <&cpu_sleep>; + clocks = <&cmu_cpucl CLK_GOUT_CPUCL_CLUSTER_CPU>; + clock-names = "cpu"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + cpu-idle-states = <&cpu_sleep>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + enable-method = "psci"; + cpu-idle-states = <&cpu_sleep>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + enable-method = "psci"; + cpu-idle-states = <&cpu_sleep>; + }; + + idle-states { + entry-method = "psci"; + + cpu_sleep: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <300>; + exit-latency-us = <1200>; + min-residency-us = <2000>; + }; + }; + }; + + fin_pll: clock-finpll { + compatible = "fixed-factor-clock"; + clocks = <&osc_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "fin_pll"; + }; + + osc_clk: clock-osc { + /* XXTI */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "osc_clk"; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + soc: soc@0 { + compatible = "simple-bus"; + ranges = <0x0 0x0 0x0 0x17000000>; + #address-cells = <1>; + #size-cells = <1>; + + cmu_imem: clock-controller@10010000 { + compatible = "axis,artpec8-cmu-imem"; + reg = <0x10010000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_IMEM_ACLK>, + <&cmu_cmu CLK_DOUT_CMU_IMEM_JPEG>; + clock-names = "fin_pll", "aclk", "jpeg"; + }; + + timer@10040000 { + compatible = "axis,artpec8-mct", "samsung,exynos4210-mct"; + reg = <0x10040000 0x1000>; + clocks = <&fin_pll>, <&cmu_imem CLK_GOUT_IMEM_MCT_PCLK>; + clock-names = "fin_pll", "mct"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + }; + + gic: interrupt-controller@10201000 { + compatible = "arm,gic-400"; + reg = <0x10201000 0x1000>, + <0x10202000 0x2000>, + <0x10204000 0x2000>, + <0x10206000 0x2000>; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + }; + + cmu_cpucl: clock-controller@11410000 { + compatible = "axis,artpec8-cmu-cpucl"; + reg = <0x11410000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_CPUCL_SWITCH>; + clock-names = "fin_pll", "switch"; + }; + + cmu_cmu: clock-controller@12400000 { + compatible = "axis,artpec8-cmu-cmu"; + reg = <0x12400000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>; + clock-names = "fin_pll"; + }; + + cmu_core: clock-controller@12410000 { + compatible = "axis,artpec8-cmu-core"; + reg = <0x12410000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_CORE_MAIN>, + <&cmu_cmu CLK_DOUT_CMU_CORE_DLP>; + clock-names = "fin_pll", "main", "dlp"; + }; + + cmu_bus: clock-controller@12c10000 { + compatible = "axis,artpec8-cmu-bus"; + reg = <0x12c10000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_BUS>, + <&cmu_cmu CLK_DOUT_CMU_BUS_DLP>; + clock-names = "fin_pll", "bus", "dlp"; + }; + + cmu_peri: clock-controller@16410000 { + compatible = "axis,artpec8-cmu-peri"; + reg = <0x16410000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_PERI_IP>, + <&cmu_cmu CLK_DOUT_CMU_PERI_AUDIO>, + <&cmu_cmu CLK_DOUT_CMU_PERI_DISP>; + clock-names = "fin_pll", "ip", "audio", "disp"; + }; + + pinctrl_peric: pinctrl@165f0000 { + compatible = "axis,artpec8-pinctrl"; + reg = <0x165f0000 0x1000>; + interrupts = ; + }; + + cmu_fsys: clock-controller@16c10000 { + compatible = "axis,artpec8-cmu-fsys"; + reg = <0x16c10000 0x4000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN0>, + <&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN1>, + <&cmu_cmu CLK_DOUT_CMU_FSYS_BUS>, + <&cmu_cmu CLK_DOUT_CMU_FSYS_IP>; + clock-names = "fin_pll", "scan0", "scan1", "bus", "ip"; + }; + + pinctrl_fsys: pinctrl@16c30000 { + compatible = "axis,artpec8-pinctrl"; + reg = <0x16c30000 0x1000>; + interrupts = ; + }; + + serial_0: serial@16cc0000 { + compatible = "axis,artpec8-uart"; + reg = <0x16cc0000 0x100>; + clocks = <&cmu_fsys CLK_GOUT_FSYS_UART0_PCLK>, + <&cmu_fsys CLK_GOUT_FSYS_UART0_SCLK_UART>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&serial0_bus>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; -- 2.49.0