[PATCH 0/6] arm64: dts: renesas: Add support for WDT/USB2.0 on RZ/{T2H,N2H} SoCs and EVKs

[PATCH 0/6] arm64: dts: renesas: Add support for WDT/USB2.0 on RZ/{T2H,N2H} SoCs and EVKs

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi All,

Extend hardware support on Renesas RZ/T2H and RZ/N2H SoCs and evaluation
boards. Below are the features added for the RZ/T2H and RZ/N2H SoCs and
EVKs:
- Add Watchdog Timer (WDT) nodes for RZ/T2H and RZ/N2H SoCs.
- Enable WDT2 on RZ/T2H and RZ/N2H EVKs.
- Add USB2.0 nodes for RZ/T2H and RZ/N2H SoCs.
- Enable USB2.0 support for RZ/T2H and RZ/N2H EVKs.

Note
1] This series applies on top of the following series:
   - https://lore.kernel.org/all/20250820200659.2048755-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
2] WDT driver and binding patches have been submitted separately.
   - https://lore.kernel.org/all/20250820202322.2051969-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
3] USB2.0 driver and binding patches have been submitted separately
   and are already merged into -next a fix for PHY driver is posted,
   - https://lore.kernel.org/all/20250821155957.1088337-1-prabhakar.mahadev-lad.rj@bp.renesas.com/

Cheers,
Prabhakar

Lad Prabhakar (6):
  arm64: dts: renesas: r9a09g077: Add WDT nodes
  arm64: dts: renesas: r9a09g087: Add WDT nodes
  arm64: dts: renesas: rzt2h-evk-common: Enable WDT2
  arm64: dts: renesas: r9a09g077: Add USB2.0 support
  arm64: dts: renesas: r9a09g087: Add USB2.0 support
  arm64: dts: renesas: rzt2h-n2h-evk: Enable USB2.0 support

 arch/arm64/boot/dts/renesas/r9a09g077.dtsi    | 107 ++++++++++++++++++
 .../dts/renesas/r9a09g077m44-rzt2h-evk.dts    |  36 ++++++
 arch/arm64/boot/dts/renesas/r9a09g087.dtsi    | 107 ++++++++++++++++++
 .../dts/renesas/r9a09g087m44-rzn2h-evk.dts    |  41 +++++++
 .../dts/renesas/rzt2h-n2h-evk-common.dtsi     |  27 +++++
 5 files changed, 318 insertions(+)

-- 
2.51.0

[PATCH 1/6] arm64: dts: renesas: r9a09g077: Add WDT nodes

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add WDT0-5 nodes to RZ/T2H (R9A09G077) SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 60 ++++++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
index 0929ce2db05c..5291ea9fc326 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -160,6 +160,66 @@ sci5: serial@81005000 {
 			status = "disabled";
 		};
 
+		wdt0: watchdog@80082000 {
+			compatible = "renesas,r9a09g077-wdt";
+			reg = <0 0x80082000 0 0x400>,
+			      <0 0x81295100 0 0x04>;
+			clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>;
+			clock-names = "pclk";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		wdt1: watchdog@80082400 {
+			compatible = "renesas,r9a09g077-wdt";
+			reg = <0 0x80082400 0 0x400>,
+			      <0 0x81295104 0 0x04>;
+			clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>;
+			clock-names = "pclk";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		wdt2: watchdog@80082800 {
+			compatible = "renesas,r9a09g077-wdt";
+			reg = <0 0x80082800 0 0x400>,
+			      <0 0x81295108 0 0x04>;
+			clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>;
+			clock-names = "pclk";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		wdt3: watchdog@80082c00 {
+			compatible = "renesas,r9a09g077-wdt";
+			reg = <0 0x80082c00 0 0x400>,
+			      <0 0x8129510c 0 0x04>;
+			clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>;
+			clock-names = "pclk";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		wdt4: watchdog@80083000 {
+			compatible = "renesas,r9a09g077-wdt";
+			reg = <0 0x80083000 0 0x400>,
+			      <0 0x81295110 0 0x04>;
+			clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>;
+			clock-names = "pclk";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		wdt5: watchdog@80083400 {
+			compatible = "renesas,r9a09g077-wdt";
+			reg = <0 0x80083400 0 0x400>,
+			      <0 0x81295114 0 0x04>;
+			clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>;
+			clock-names = "pclk";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
 		i2c0: i2c@80088000 {
 			compatible = "renesas,riic-r9a09g077";
 			reg = <0 0x80088000 0 0x400>;
-- 
2.51.0

[PATCH 2/6] arm64: dts: renesas: r9a09g087: Add WDT nodes

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add WDT0-5 nodes to RZ/N2H (R9A09G087) SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 60 ++++++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
index ecbb7b93aed2..b669c1a506d3 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
@@ -160,6 +160,66 @@ sci5: serial@81005000 {
 			status = "disabled";
 		};
 
+		wdt0: watchdog@80082000 {
+			compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt";
+			reg = <0 0x80082000 0 0x400>,
+			      <0 0x81295100 0 0x04>;
+			clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>;
+			clock-names = "pclk";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		wdt1: watchdog@80082400 {
+			compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt";
+			reg = <0 0x80082400 0 0x400>,
+			      <0 0x81295104 0 0x04>;
+			clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>;
+			clock-names = "pclk";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		wdt2: watchdog@80082800 {
+			compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt";
+			reg = <0 0x80082800 0 0x400>,
+			      <0 0x81295108 0 0x04>;
+			clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>;
+			clock-names = "pclk";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		wdt3: watchdog@80082c00 {
+			compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt";
+			reg = <0 0x80082c00 0 0x400>,
+			      <0 0x8129510c 0 0x04>;
+			clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>;
+			clock-names = "pclk";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		wdt4: watchdog@80083000 {
+			compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt";
+			reg = <0 0x80083000 0 0x400>,
+			      <0 0x81295110 0 0x04>;
+			clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>;
+			clock-names = "pclk";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		wdt5: watchdog@80083400 {
+			compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt";
+			reg = <0 0x80083400 0 0x400>,
+			      <0 0x81295114 0 0x04>;
+			clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>;
+			clock-names = "pclk";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
 		i2c0: i2c@80088000 {
 			compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077";
 			reg = <0 0x80088000 0 0x400>;
-- 
2.51.0

[PATCH 3/6] arm64: dts: renesas: rzt2h-evk-common: Enable WDT2

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Enable watchdog (WDT2) on RZ/T2H and RZ/N2H EVKs.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
index 8b9d04dce8ae..91068042bec0 100644
--- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
@@ -217,3 +217,8 @@ &sdhi1 {
 	status = "okay";
 };
 #endif
+
+&wdt2 {
+	status = "okay";
+	timeout-sec = <60>;
+};
-- 
2.51.0

[PATCH 4/6] arm64: dts: renesas: r9a09g077: Add USB2.0 support

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add EHCI, OHCI, PHY and HSUSB nodes to RZ/T2H (R9A09G077) SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 47 ++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
index 5291ea9fc326..433e3317a324 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -299,6 +299,53 @@ gic: interrupt-controller@83000000 {
 			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
 		};
 
+		ohci: usb@92040000 {
+			compatible = "generic-ohci";
+			reg = <0 0x92040000 0 0x100>;
+			interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 408>;
+			phys = <&usb2_phy 1>;
+			phy-names = "usb";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		ehci: usb@92040100 {
+			compatible = "generic-ehci";
+			reg = <0 0x92040100 0 0x100>;
+			interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 408>;
+			phys = <&usb2_phy 2>;
+			phy-names = "usb";
+			companion = <&ohci>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		usb2_phy: usb-phy@92040200 {
+			compatible = "renesas,usb2-phy-r9a09g077";
+			reg = <0 0x92040200 0 0x700>;
+			interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 408>,
+				 <&cpg CPG_CORE R9A09G077_USB_CLK>;
+			#phy-cells = <1>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		hsusb: usb@92041000 {
+			compatible = "renesas,usbhs-r9a09g077";
+			reg = <0 0x92041000 0 0x10000>;
+			interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 408>;
+			phys = <&usb2_phy 3>;
+			phy-names = "usb";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
 		sdhi0: mmc@92080000  {
 			compatible = "renesas,sdhi-r9a09g077",
 				     "renesas,sdhi-r9a09g057";
-- 
2.51.0

[PATCH 5/6] arm64: dts: renesas: r9a09g087: Add USB2.0 support

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add EHCI, OHCI, PHY and HSUSB nodes to RZ/N2H (R9A09G087) SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 47 ++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
index b669c1a506d3..cd8e409b8db8 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
@@ -299,6 +299,53 @@ gic: interrupt-controller@83000000 {
 			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
 		};
 
+		ohci: usb@92040000 {
+			compatible = "generic-ohci";
+			reg = <0 0x92040000 0 0x100>;
+			interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 408>;
+			phys = <&usb2_phy 1>;
+			phy-names = "usb";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		ehci: usb@92040100 {
+			compatible = "generic-ehci";
+			reg = <0 0x92040100 0 0x100>;
+			interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 408>;
+			phys = <&usb2_phy 2>;
+			phy-names = "usb";
+			companion = <&ohci>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		usb2_phy: usb-phy@92040200 {
+			compatible = "renesas,usb2-phy-r9a09g087", "renesas,usb2-phy-r9a09g077";
+			reg = <0 0x92040200 0 0x700>;
+			interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 408>,
+				 <&cpg CPG_CORE R9A09G087_USB_CLK>;
+			#phy-cells = <1>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		hsusb: usb@92041000 {
+			compatible = "renesas,usbhs-r9a09g087", "renesas,usbhs-r9a09g077";
+			reg = <0 0x92041000 0 0x10000>;
+			interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 408>;
+			phys = <&usb2_phy 3>;
+			phy-names = "usb";
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
 		sdhi0: mmc@92080000  {
 			compatible = "renesas,sdhi-r9a09g087",
 				     "renesas,sdhi-r9a09g057";
-- 
2.51.0

[PATCH 6/6] arm64: dts: renesas: rzt2h-n2h-evk: Enable USB2.0 support

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Enable USB2.0 support on RZ/T2H and RZ/N2H EVKs.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../dts/renesas/r9a09g077m44-rzt2h-evk.dts    | 36 ++++++++++++++++
 .../dts/renesas/r9a09g087m44-rzn2h-evk.dts    | 41 +++++++++++++++++++
 .../dts/renesas/rzt2h-n2h-evk-common.dtsi     | 22 ++++++++++
 3 files changed, 99 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
index 264f7ddb8cc5..bcd779cd51a2 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
@@ -29,6 +29,28 @@
  */
 #define SD1_MICRO_SD	1
 
+/*
+ * USB Pin Configuration:
+ *
+ * This board is equipped with three USB connectors: Type-A (CN80), Mini-B (CN79),
+ * and Micro-AB (CN33). The RZ/T2H SoC has a single USB channel, so either the USB
+ * host interface or the USB function interface can be used, but not both at the
+ * same time.
+ *
+ * By default, the Type-A (CN80) and Mini-B (CN79) connectors are enabled.
+ * Configure the switches as follows:
+ *   - P00_0 - P00_2 (control signals for USB power supply): SW1[5] = ON
+ *   - USB_VBUSIN (used for USB function): SW7[7] = OFF; SW7[8] = ON
+ *   - USB_VBUSEN (used for USB_HF_VBUSEN): SW7[9] = OFF; SW7[10] = ON
+ *
+ * To enable the Micro-AB (CN33) USB OTG connector, set the following macro to 1
+ * and configure the switches as follows:
+ *   - P00_0 - P00_2 (control signals for USB power supply): SW1[5] = ON
+ *   - USB_VBUSIN (used for USB OTG): SW7[7] = ON; SW7[8] = OFF
+ *   - USB_VBUSEN (used for USB_OTG_VBUSEN): SW7[9] = ON; SW7[10] = OFF
+ */
+#define USB_OTG		0
+
 #include "rzt2h-n2h-evk-common.dtsi"
 
 / {
@@ -145,4 +167,18 @@ i2c1_pins: i2c1-pins {
 		pinmux = <RZT2H_PORT_PINMUX(5, 0, 0x17)>, /* SDA */
 			 <RZT2H_PORT_PINMUX(4, 7, 0x17)>; /* SCL */
 	};
+
+#if USB_OTG
+	usb-exicen-hog {
+		gpio-hog;
+		gpios = <RZT2H_GPIO(0, 2) GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "usb_exicen_a";
+	};
+#endif
+
+	usb_pins: usb-pins {
+		pinmux = <RZT2H_PORT_PINMUX(0, 0, 0x13)>, /* VBUS */
+			 <RZT2H_PORT_PINMUX(0, 1, 0x13)>; /* OVRCUR */
+	};
 };
diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
index 80f358fb2d74..b98b0f7c1128 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
@@ -33,6 +33,33 @@
  */
 #define SD1_MICRO_SD	1
 
+/*
+ * USB Pin Configuration:
+ *
+ * This board is equipped with three USB connectors: Type-A (CN7), Mini-B (CN8),
+ * and Micro-AB (CN9). The RZ/N2H SoC has a single USB channel, so either the USB
+ * host interface or the USB function interface can be used, but not both at the
+ * same time.
+ *
+ * By default, the Type-A (CN7) and Mini-B (CN8) connectors are enabled.
+ * Configure the switches as follows:
+ *   - P02_2 - P02_3 (control signals for USB power supply): DSW2[6] = OFF;
+ *     - P02_2 (used for VBUSEN): DSW14[5] = OFF; DSW14[6] = ON
+ *     - P02_3 (used for USB_OVRCUR): DSW14[1] = OFF; DSW14[2] = ON
+ *   - USB_VBUSIN (used for VBUS of CN8 for function): DSW16[1] = OFF; DSW16[2] = ON
+ *   - USB_VBUSEN (used for USB_HF_VBUSEN): DSW16[3] = OFF; DSW16[4] = ON
+ *
+ * To enable the Micro-AB (CN9) USB OTG connector, set the following macro to 1
+ * and configure the switches as follows:
+ *   - P02_2 - P02_3 (control signals for USB power supply): DSW2[6] = OFF;
+ *     - P02_2 (used for VBUSEN): DSW14[5] = OFF; DSW14[6] = ON
+ *     - P02_3 (used for USB_OVRCUR): DSW14[1] = OFF; DSW14[2] = ON
+ *   - USB_VBUSIN (used for VBUS of CN9 for OTG): DSW16[1] = ON; DSW16[2] = OFF
+ *   - USB_VBUSEN (used for USB_OTG_VBUSEN): DSW16[3] = ON; DSW16[4] = OFF
+ *   - USB_EXICEN (used for USB OTG EXICEN): DSW14[3] = OFF; DSW14[4] = ON
+ */
+#define USB_OTG		0
+
 #include "rzt2h-n2h-evk-common.dtsi"
 
 /*
@@ -185,4 +212,18 @@ i2c1_pins: i2c1-pins {
 		pinmux = <RZT2H_PORT_PINMUX(3, 3, 0x17)>,
 			 <RZT2H_PORT_PINMUX(3, 4, 0x17)>;
 	};
+
+#if USB_OTG
+	usb-exicen-hog {
+		gpio-hog;
+		gpios = <RZT2H_GPIO(2, 4) GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "usb_exicen_a";
+	};
+#endif
+
+	usb_pins: usb-pins {
+		pinmux = <RZT2H_PORT_PINMUX(2, 2, 0x13)>, /* VBUS */
+			 <RZT2H_PORT_PINMUX(2, 3, 0x13)>; /* OVRCUR */
+	};
 };
diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
index 91068042bec0..5c91002c99c4 100644
--- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
@@ -65,10 +65,20 @@ vccq_sdhi1: regulator-vccq-sdhi1 {
 #endif
 };
 
+&ehci {
+	dr_mode = "otg";
+	status = "okay";
+};
+
 &extal_clk {
 	clock-frequency = <25000000>;
 };
 
+&hsusb {
+	dr_mode = "otg";
+	status = "okay";
+};
+
 &i2c0 {
 	eeprom: eeprom@50 {
 		compatible = "renesas,r1ex24016", "atmel,24c16";
@@ -77,6 +87,11 @@ eeprom: eeprom@50 {
 	};
 };
 
+&ohci {
+	dr_mode = "otg";
+	status = "okay";
+};
+
 &pinctrl {
 	/*
 	 * SCI0 Pin Configuration:
@@ -218,6 +233,13 @@ &sdhi1 {
 };
 #endif
 
+&usb2_phy {
+	pinctrl-0 = <&usb_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
 &wdt2 {
 	status = "okay";
 	timeout-sec = <60>;
-- 
2.51.0

Re: [PATCH 1/6] arm64: dts: renesas: r9a09g077: Add WDT nodes

[Geert Uytterhoeven]

Hi Prabhakar,

On Thu, 21 Aug 2025 at 18:19, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add WDT0-5 nodes to RZ/T2H (R9A09G077) SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.18.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 2/6] arm64: dts: renesas: r9a09g087: Add WDT nodes

[Geert Uytterhoeven]

On Thu, 21 Aug 2025 at 18:19, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add WDT0-5 nodes to RZ/N2H (R9A09G087) SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.18.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/6] arm64: dts: renesas: rzt2h-evk-common: Enable WDT2

[Geert Uytterhoeven]

On Thu, 21 Aug 2025 at 18:19, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Enable watchdog (WDT2) on RZ/T2H and RZ/N2H EVKs.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.18.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 4/6] arm64: dts: renesas: r9a09g077: Add USB2.0 support

[Geert Uytterhoeven]

Hi Prabhakar,

On Thu, 21 Aug 2025 at 18:19, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add EHCI, OHCI, PHY and HSUSB nodes to RZ/T2H (R9A09G077) SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi

> +               hsusb: usb@92041000 {
> +                       compatible = "renesas,usbhs-r9a09g077";
> +                       reg = <0 0x92041000 0 0x10000>;

"0x1000", as the region starting at 0x92043000 is marked reserved?
I can fix that while applying.

> +                       interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&cpg CPG_MOD 408>;
> +                       phys = <&usb2_phy 3>;
> +                       phy-names = "usb";
> +                       power-domains = <&cpg>;
> +                       status = "disabled";
> +               };
> +
>                 sdhi0: mmc@92080000  {
>                         compatible = "renesas,sdhi-r9a09g077",
>                                      "renesas,sdhi-r9a09g057";

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 5/6] arm64: dts: renesas: r9a09g087: Add USB2.0 support

[Geert Uytterhoeven]

Hi Prabhakar,

On Thu, 21 Aug 2025 at 18:19, Prabhakar <prabhakar.csengg@gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add EHCI, OHCI, PHY and HSUSB nodes to RZ/N2H (R9A09G087) SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi

> +               hsusb: usb@92041000 {
> +                       compatible = "renesas,usbhs-r9a09g087", "renesas,usbhs-r9a09g077";
> +                       reg = <0 0x92041000 0 0x10000>;

"0x1000", as the region starting at 0x92043000 is marked reserved?
I can fix that while applying.

> +                       interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&cpg CPG_MOD 408>;
> +                       phys = <&usb2_phy 3>;
> +                       phy-names = "usb";
> +                       power-domains = <&cpg>;
> +                       status = "disabled";
> +               };
> +
>                 sdhi0: mmc@92080000  {
>                         compatible = "renesas,sdhi-r9a09g087",
>                                      "renesas,sdhi-r9a09g057";

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 4/6] arm64: dts: renesas: r9a09g077: Add USB2.0 support

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Wed, Sep 3, 2025 at 3:05 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Thu, 21 Aug 2025 at 18:19, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add EHCI, OHCI, PHY and HSUSB nodes to RZ/T2H (R9A09G077) SoC DTSI.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
>
> > +               hsusb: usb@92041000 {
> > +                       compatible = "renesas,usbhs-r9a09g077";
> > +                       reg = <0 0x92041000 0 0x10000>;
>
> "0x1000", as the region starting at 0x92043000 is marked reserved?
> I can fix that while applying.
>
Ouch agreed, thank you for taking care of this (also for RZ/N2H patch).

Cheers,
Prabhakar

> > +                       interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&cpg CPG_MOD 408>;
> > +                       phys = <&usb2_phy 3>;
> > +                       phy-names = "usb";
> > +                       power-domains = <&cpg>;
> > +                       status = "disabled";
> > +               };
> > +
> >                 sdhi0: mmc@92080000  {
> >                         compatible = "renesas,sdhi-r9a09g077",
> >                                      "renesas,sdhi-r9a09g057";
>
> The rest LGTM.
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

Re: [PATCH 6/6] arm64: dts: renesas: rzt2h-n2h-evk: Enable USB2.0 support

[Geert Uytterhoeven]

Hi Prabhakar,

On Thu, 21 Aug 2025 at 18:19, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Enable USB2.0 support on RZ/T2H and RZ/N2H EVKs.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
> +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
> @@ -29,6 +29,28 @@
>   */
>  #define SD1_MICRO_SD   1
>
> +/*
> + * USB Pin Configuration:
> + *
> + * This board is equipped with three USB connectors: Type-A (CN80), Mini-B (CN79),
> + * and Micro-AB (CN33). The RZ/T2H SoC has a single USB channel, so either the USB
> + * host interface or the USB function interface can be used, but not both at the
> + * same time.

Please reflow the text to fit in 80 columns.

The last sentence applies to the CN80 and CN79 connectors only, right?

> + *
> + * By default, the Type-A (CN80) and Mini-B (CN79) connectors are enabled.
> + * Configure the switches as follows:
> + *   - P00_0 - P00_2 (control signals for USB power supply): SW1[5] = ON
> + *   - USB_VBUSIN (used for USB function): SW7[7] = OFF; SW7[8] = ON
> + *   - USB_VBUSEN (used for USB_HF_VBUSEN): SW7[9] = OFF; SW7[10] = ON
> + *
> + * To enable the Micro-AB (CN33) USB OTG connector, set the following macro to 1
> + * and configure the switches as follows:
> + *   - P00_0 - P00_2 (control signals for USB power supply): SW1[5] = ON
> + *   - USB_VBUSIN (used for USB OTG): SW7[7] = ON; SW7[8] = OFF
> + *   - USB_VBUSEN (used for USB_OTG_VBUSEN): SW7[9] = ON; SW7[10] = OFF
> + */
> +#define USB_OTG                0
> +
>  #include "rzt2h-n2h-evk-common.dtsi"
>
>  / {
> @@ -145,4 +167,18 @@ i2c1_pins: i2c1-pins {
>                 pinmux = <RZT2H_PORT_PINMUX(5, 0, 0x17)>, /* SDA */
>                          <RZT2H_PORT_PINMUX(4, 7, 0x17)>; /* SCL */
>         };
> +
> +#if USB_OTG
> +       usb-exicen-hog {
> +               gpio-hog;
> +               gpios = <RZT2H_GPIO(0, 2) GPIO_ACTIVE_HIGH>;
> +               output-high;
> +               line-name = "usb_exicen_a";
> +       };
> +#endif
> +
> +       usb_pins: usb-pins {
> +               pinmux = <RZT2H_PORT_PINMUX(0, 0, 0x13)>, /* VBUS */

s/VBUS/VBUSEN/?

> +                        <RZT2H_PORT_PINMUX(0, 1, 0x13)>; /* OVRCUR */
> +       };
>  };
> diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
> index 80f358fb2d74..b98b0f7c1128 100644
> --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
> +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
> @@ -33,6 +33,33 @@
>   */
>  #define SD1_MICRO_SD   1
>
> +/*
> + * USB Pin Configuration:
> + *
> + * This board is equipped with three USB connectors: Type-A (CN7), Mini-B (CN8),
> + * and Micro-AB (CN9). The RZ/N2H SoC has a single USB channel, so either the USB
> + * host interface or the USB function interface can be used, but not both at the
> + * same time.

Please reflow the text to fit in 80 columns.

The last sentence applies to the CN7 and CN8 connectors only, right?

> + *
> + * By default, the Type-A (CN7) and Mini-B (CN8) connectors are enabled.
> + * Configure the switches as follows:
> + *   - P02_2 - P02_3 (control signals for USB power supply): DSW2[6] = OFF;

s/DSW2[6]/DSW2[5]/?

> + *     - P02_2 (used for VBUSEN): DSW14[5] = OFF; DSW14[6] = ON
> + *     - P02_3 (used for USB_OVRCUR): DSW14[1] = OFF; DSW14[2] = ON
> + *   - USB_VBUSIN (used for VBUS of CN8 for function): DSW16[1] = OFF; DSW16[2] = ON
> + *   - USB_VBUSEN (used for USB_HF_VBUSEN): DSW16[3] = OFF; DSW16[4] = ON
> + *
> + * To enable the Micro-AB (CN9) USB OTG connector, set the following macro to 1
> + * and configure the switches as follows:
> + *   - P02_2 - P02_3 (control signals for USB power supply): DSW2[6] = OFF;

s/DSW2[6]/DSW2[5]/?

> + *     - P02_2 (used for VBUSEN): DSW14[5] = OFF; DSW14[6] = ON
> + *     - P02_3 (used for USB_OVRCUR): DSW14[1] = OFF; DSW14[2] = ON
> + *   - USB_VBUSIN (used for VBUS of CN9 for OTG): DSW16[1] = ON; DSW16[2] = OFF
> + *   - USB_VBUSEN (used for USB_OTG_VBUSEN): DSW16[3] = ON; DSW16[4] = OFF
> + *   - USB_EXICEN (used for USB OTG EXICEN): DSW14[3] = OFF; DSW14[4] = ON

Looks like you could use P00_0 - P00_2 instead of P02_2 - P02_3, like
on the RZ/T2H EVK?
But you don't want to do that because you want to use these pins for Ethernet?

> + */
> +#define USB_OTG                0
> +
>  #include "rzt2h-n2h-evk-common.dtsi"
>
>  /*
> @@ -185,4 +212,18 @@ i2c1_pins: i2c1-pins {
>                 pinmux = <RZT2H_PORT_PINMUX(3, 3, 0x17)>,
>                          <RZT2H_PORT_PINMUX(3, 4, 0x17)>;
>         };
> +
> +#if USB_OTG
> +       usb-exicen-hog {
> +               gpio-hog;
> +               gpios = <RZT2H_GPIO(2, 4) GPIO_ACTIVE_HIGH>;
> +               output-high;
> +               line-name = "usb_exicen_a";
> +       };
> +#endif
> +
> +       usb_pins: usb-pins {
> +               pinmux = <RZT2H_PORT_PINMUX(2, 2, 0x13)>, /* VBUS */

s/VBUS/VBUSEN/?

> +                        <RZT2H_PORT_PINMUX(2, 3, 0x13)>; /* OVRCUR */
> +       };
>  };

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 6/6] arm64: dts: renesas: rzt2h-n2h-evk: Enable USB2.0 support

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Wed, Sep 3, 2025 at 4:04 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Thu, 21 Aug 2025 at 18:19, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Enable USB2.0 support on RZ/T2H and RZ/N2H EVKs.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
> > @@ -29,6 +29,28 @@
> >   */
> >  #define SD1_MICRO_SD   1
> >
> > +/*
> > + * USB Pin Configuration:
> > + *
> > + * This board is equipped with three USB connectors: Type-A (CN80), Mini-B (CN79),
> > + * and Micro-AB (CN33). The RZ/T2H SoC has a single USB channel, so either the USB
> > + * host interface or the USB function interface can be used, but not both at the
> > + * same time.
>
> Please reflow the text to fit in 80 columns.
>
Ok, I will reflow it to 80 columns
> The last sentence applies to the CN80 and CN79 connectors only, right?
>
Yes,  I'll reword it to say `but not both at the same time while using
CN79 and CN80 connectors.`

> > + *
> > + * By default, the Type-A (CN80) and Mini-B (CN79) connectors are enabled.
> > + * Configure the switches as follows:
> > + *   - P00_0 - P00_2 (control signals for USB power supply): SW1[5] = ON
> > + *   - USB_VBUSIN (used for USB function): SW7[7] = OFF; SW7[8] = ON
> > + *   - USB_VBUSEN (used for USB_HF_VBUSEN): SW7[9] = OFF; SW7[10] = ON
> > + *
> > + * To enable the Micro-AB (CN33) USB OTG connector, set the following macro to 1
> > + * and configure the switches as follows:
> > + *   - P00_0 - P00_2 (control signals for USB power supply): SW1[5] = ON
> > + *   - USB_VBUSIN (used for USB OTG): SW7[7] = ON; SW7[8] = OFF
> > + *   - USB_VBUSEN (used for USB_OTG_VBUSEN): SW7[9] = ON; SW7[10] = OFF
> > + */
> > +#define USB_OTG                0
> > +
> >  #include "rzt2h-n2h-evk-common.dtsi"
> >
> >  / {
> > @@ -145,4 +167,18 @@ i2c1_pins: i2c1-pins {
> >                 pinmux = <RZT2H_PORT_PINMUX(5, 0, 0x17)>, /* SDA */
> >                          <RZT2H_PORT_PINMUX(4, 7, 0x17)>; /* SCL */
> >         };
> > +
> > +#if USB_OTG
> > +       usb-exicen-hog {
> > +               gpio-hog;
> > +               gpios = <RZT2H_GPIO(0, 2) GPIO_ACTIVE_HIGH>;
> > +               output-high;
> > +               line-name = "usb_exicen_a";
> > +       };
> > +#endif
> > +
> > +       usb_pins: usb-pins {
> > +               pinmux = <RZT2H_PORT_PINMUX(0, 0, 0x13)>, /* VBUS */
>
> s/VBUS/VBUSEN/?
>
OK.

> > +                        <RZT2H_PORT_PINMUX(0, 1, 0x13)>; /* OVRCUR */
> > +       };
> >  };
> > diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
> > index 80f358fb2d74..b98b0f7c1128 100644
> > --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
> > @@ -33,6 +33,33 @@
> >   */
> >  #define SD1_MICRO_SD   1
> >
> > +/*
> > + * USB Pin Configuration:
> > + *
> > + * This board is equipped with three USB connectors: Type-A (CN7), Mini-B (CN8),
> > + * and Micro-AB (CN9). The RZ/N2H SoC has a single USB channel, so either the USB
> > + * host interface or the USB function interface can be used, but not both at the
> > + * same time.
>
> Please reflow the text to fit in 80 columns.
>
OK.

> The last sentence applies to the CN7 and CN8 connectors only, right?
>
Yes. I'll reword it to say `but not both at the same time while using
CN7 and CN8 connectors`

> > + *
> > + * By default, the Type-A (CN7) and Mini-B (CN8) connectors are enabled.
> > + * Configure the switches as follows:
> > + *   - P02_2 - P02_3 (control signals for USB power supply): DSW2[6] = OFF;
>
> s/DSW2[6]/DSW2[5]/?
>
The above is correct,

DSW2[5] is OFF, P00_0 to P00_2 are connected to BSC2(CN43) and GPT0(CN49).
DSW2[5] is ON, P00_0 to P00_2 are used as control signals for the USB
power-supply IC.

But we are using P02_2 and P02_3
DSW2[5] is OFF, P01_0, P01_2, P01_4 to P01_7, and P02_0 to P02_3 are
connected to ENCIF0(CN44) and GPT0(CN49), and used as control signals
for the USB power-supply IC.

> > + *     - P02_2 (used for VBUSEN): DSW14[5] = OFF; DSW14[6] = ON
> > + *     - P02_3 (used for USB_OVRCUR): DSW14[1] = OFF; DSW14[2] = ON
> > + *   - USB_VBUSIN (used for VBUS of CN8 for function): DSW16[1] = OFF; DSW16[2] = ON
> > + *   - USB_VBUSEN (used for USB_HF_VBUSEN): DSW16[3] = OFF; DSW16[4] = ON
> > + *
> > + * To enable the Micro-AB (CN9) USB OTG connector, set the following macro to 1
> > + * and configure the switches as follows:
> > + *   - P02_2 - P02_3 (control signals for USB power supply): DSW2[6] = OFF;
>
> s/DSW2[6]/DSW2[5]/?
>
ditto.

> > + *     - P02_2 (used for VBUSEN): DSW14[5] = OFF; DSW14[6] = ON
> > + *     - P02_3 (used for USB_OVRCUR): DSW14[1] = OFF; DSW14[2] = ON
> > + *   - USB_VBUSIN (used for VBUS of CN9 for OTG): DSW16[1] = ON; DSW16[2] = OFF
> > + *   - USB_VBUSEN (used for USB_OTG_VBUSEN): DSW16[3] = ON; DSW16[4] = OFF
> > + *   - USB_EXICEN (used for USB OTG EXICEN): DSW14[3] = OFF; DSW14[4] = ON
>
> Looks like you could use P00_0 - P00_2 instead of P02_2 - P02_3, like
> on the RZ/T2H EVK?
> But you don't want to do that because you want to use these pins for Ethernet?
>
Yes, I plan to use them for Ethernet.

> > + */
> > +#define USB_OTG                0
> > +
> >  #include "rzt2h-n2h-evk-common.dtsi"
> >
> >  /*
> > @@ -185,4 +212,18 @@ i2c1_pins: i2c1-pins {
> >                 pinmux = <RZT2H_PORT_PINMUX(3, 3, 0x17)>,
> >                          <RZT2H_PORT_PINMUX(3, 4, 0x17)>;
> >         };
> > +
> > +#if USB_OTG
> > +       usb-exicen-hog {
> > +               gpio-hog;
> > +               gpios = <RZT2H_GPIO(2, 4) GPIO_ACTIVE_HIGH>;
> > +               output-high;
> > +               line-name = "usb_exicen_a";
> > +       };
> > +#endif
> > +
> > +       usb_pins: usb-pins {
> > +               pinmux = <RZT2H_PORT_PINMUX(2, 2, 0x13)>, /* VBUS */
>
> s/VBUS/VBUSEN/?
>
OK.

Cheers,
Prabhakar