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Sun, 24 Aug 2025 19:55:45 -0700 (PDT) Received: from [127.0.0.1] ([172.191.151.57]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4b2b8c61adcsm43970491cf.5.2025.08.24.19.55.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Aug 2025 19:55:44 -0700 (PDT) From: Denzeel Oliva Subject: [PATCH v3 0/4] clk: samsung: exynos990: CMU_TOP fixes (mux regs, widths, factors) Date: Mon, 25 Aug 2025 02:55:42 +0000 Message-Id: <20250825-cmu-top-v3-0-8838641432dc@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAK7Qq2gC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyjHUUlJIzE vPSU3UzU4B8JSMDI1MDCyNT3eTcUt2S/AJd02RzA8tkwxQD82QjJaDqgqLUtMwKsEnRsbW1AIW cgzJZAAAA X-Change-ID: 20250825-cmu-top-5c709c1d07c2 To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Denzeel Oliva X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1756090544; l=1248; i=wachiturroxd150@gmail.com; s=20250825; h=from:subject:message-id; bh=Il0Ec3pMC9RC7MiF9xNyXJRyNNelcuGbw9atXy12I8U=; b=UgqjtqzT/u3t+ZdgWcXKvRaVCsE/5E5v3H1Jf2w8mP52nY0Rb0Y2GRtVdosb+qF8736d4KU5Y S9o3sz7Ouk2AOwGVS2NRieQqemj4FgH8DW8xEsuq0rAR9T0UyYYWiRb X-Developer-Key: i=wachiturroxd150@gmail.com; a=ed25519; pk=qZrip2idhSTNQABELWG6WKCrg9xOKep//pV9JGKmW5k= Hi, Two small fixes for Exynos990 CMU_TOP: Correct PLL mux register selection (use PLL_CON0), add DPU_BUS and CMUREF mux/div, and update clock IDs. Fix mux/div bit widths and replace a few bogus divs with fixed-factor clocks (HSI1/2 PCIe, USBDP debug); also fix OTP rate. Changes in v2: - In the first commit the divratio of PLL_SHARED0_DIV3 should not be changed. Changes in v3: - There is no ABI massive break, the new ID clocks are in the last define CMU_TOP block. Please review. Denzeel Oliva Signed-off-by: Denzeel Oliva --- Denzeel Oliva (4): clk: samsung: exynos990: Fix CMU TOP mux/div widths and add fixed-factors dt-bindings: clock: exynos990: Extend clocks IDs clk: samsung: exynos990: update CLK_NR_TOP for new IDs clocks clk: samsung: exynos990: Fix PLL mux regs, add DPU/CMUREF drivers/clk/samsung/clk-exynos990.c | 136 ++++++++++++++++---------- include/dt-bindings/clock/samsung,exynos990.h | 4 + 2 files changed, 89 insertions(+), 51 deletions(-) --- base-commit: 0f4c93f7eb861acab537dbe94441817a270537bf change-id: 20250825-cmu-top-5c709c1d07c2 Best regards, -- Denzeel Oliva