[PATCH v1 0/5] Icicle Kit with prod device and Discovery Kit support

[PATCH v1 0/5] Icicle Kit with prod device and Discovery Kit support

[Valentina Fernandez]

Hi all,

With the introduction of the Icicle Kit with the production device
(MPFS250T) to the market, it's necessary to distinguish it from the
engineering sample (-es) variant. This is because engineering samples
cannot write to flash from the MSS, as noted in the PolarFire SoC
FPGA ES errata.

This series adds a common board DTSI for the Icicle Kit, containing
hardware shared by both the engineering sample and production
versions, as well as a DTS for each Icicle Kit variant.

The last two patches add support for the PolarFire SoC Discovery Kit
board.

Thanks,
Valentina

Valentina Fernandez (5):
  riscv: dts: microchip: add common board dtsi for icicle kit variants
  dt-bindings: riscv: microchip: document icicle kit with production
    device
  riscv: dts: microchip: add icicle kit with production device
  dt-bindings: riscv: microchip: document Discovery Kit
  riscv: dts: microchip: add a device tree for Discovery Kit

 .../devicetree/bindings/riscv/microchip.yaml  |  13 +
 arch/riscv/boot/dts/microchip/Makefile        |   2 +
 .../dts/microchip/mpfs-disco-kit-fabric.dtsi  |  58 ++++
 .../boot/dts/microchip/mpfs-disco-kit.dts     | 191 +++++++++++++
 .../dts/microchip/mpfs-icicle-kit-common.dtsi | 251 ++++++++++++++++++
 .../dts/microchip/mpfs-icicle-kit-fabric.dtsi |  23 +-
 .../dts/microchip/mpfs-icicle-kit-prod.dts    |  23 ++
 .../boot/dts/microchip/mpfs-icicle-kit.dts    | 244 +----------------
 8 files changed, 561 insertions(+), 244 deletions(-)
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts

-- 
2.34.1

[PATCH v1 1/5] riscv: dts: microchip: add common board dtsi for icicle kit variants

[Valentina Fernandez]

In preparation for supporting the Icicle Kit with production silicon,
add a common board dtsi for the icicle kit with hardware shared by both
the engineering sample and production versions.

Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com>
---
 .../dts/microchip/mpfs-icicle-kit-common.dtsi | 247 ++++++++++++++++++
 .../boot/dts/microchip/mpfs-icicle-kit.dts    | 241 +----------------
 2 files changed, 248 insertions(+), 240 deletions(-)
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi

diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi
new file mode 100644
index 000000000000..eafea3b69cd7
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2025 Microchip Technology Inc */
+
+/dts-v1/;
+
+#include "mpfs.dtsi"
+#include "mpfs-icicle-kit-fabric.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	aliases {
+		ethernet0 = &mac1;
+		serial0 = &mmuart0;
+		serial1 = &mmuart1;
+		serial2 = &mmuart2;
+		serial3 = &mmuart3;
+		serial4 = &mmuart4;
+	};
+
+	chosen {
+		stdout-path = "serial1:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-1 {
+			gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
+			color = <LED_COLOR_ID_RED>;
+			label = "led1";
+		};
+
+		led-2 {
+			gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
+			color = <LED_COLOR_ID_RED>;
+			label = "led2";
+		};
+
+		led-3 {
+			gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
+			color = <LED_COLOR_ID_AMBER>;
+			label = "led3";
+		};
+
+		led-4 {
+			gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+			color = <LED_COLOR_ID_AMBER>;
+			label = "led4";
+		};
+	};
+
+	ddrc_cache_lo: memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x40000000>;
+		status = "okay";
+	};
+
+	ddrc_cache_hi: memory@1040000000 {
+		device_type = "memory";
+		reg = <0x10 0x40000000 0x0 0x40000000>;
+		status = "okay";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		hss_payload: region@BFC00000 {
+			reg = <0x0 0xBFC00000 0x0 0x400000>;
+			no-map;
+		};
+	};
+};
+
+&core_pwm0 {
+	status = "okay";
+};
+
+&gpio2 {
+	interrupts = <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>;
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+
+	power-monitor@10 {
+		compatible = "microchip,pac1934";
+		reg = <0x10>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		channel@1 {
+			reg = <0x1>;
+			shunt-resistor-micro-ohms = <10000>;
+			label = "VDDREG";
+		};
+
+		channel@2 {
+			reg = <0x2>;
+			shunt-resistor-micro-ohms = <10000>;
+			label = "VDDA25";
+		};
+
+		channel@3 {
+			reg = <0x3>;
+			shunt-resistor-micro-ohms = <10000>;
+			label = "VDD25";
+		};
+
+		channel@4 {
+			reg = <0x4>;
+			shunt-resistor-micro-ohms = <10000>;
+			label = "VDDA_REG";
+		};
+	};
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&mac0 {
+	phy-mode = "sgmii";
+	phy-handle = <&phy0>;
+	status = "okay";
+};
+
+&mac1 {
+	phy-mode = "sgmii";
+	phy-handle = <&phy1>;
+	status = "okay";
+
+	phy1: ethernet-phy@9 {
+		reg = <9>;
+	};
+
+	phy0: ethernet-phy@8 {
+		reg = <8>;
+	};
+};
+
+&mbox {
+	status = "okay";
+};
+
+&mmc {
+	bus-width = <4>;
+	disable-wp;
+	cap-sd-highspeed;
+	cap-mmc-highspeed;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	status = "okay";
+};
+
+&mmuart1 {
+	status = "okay";
+};
+
+&mmuart2 {
+	status = "okay";
+};
+
+&mmuart3 {
+	status = "okay";
+};
+
+&mmuart4 {
+	status = "okay";
+};
+
+&pcie {
+	status = "okay";
+};
+
+&qspi {
+	status = "okay";
+};
+
+&refclk {
+	clock-frequency = <125000000>;
+};
+
+&refclk_ccc {
+	clock-frequency = <50000000>;
+};
+
+&rtc {
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+};
+
+&spi1 {
+	status = "okay";
+};
+
+&syscontroller {
+	status = "okay";
+};
+
+&syscontroller_qspi {
+	/*
+	 * The flash *is* there, but Icicle kits that have engineering sample
+	 * silicon (write?) access to this flash to non-functional. The system
+	 * controller itself can actually access it, but the MSS cannot write
+	 * an image there. Instantiating a coreQSPI in the fabric & connecting
+	 * it to the flash instead should work though. Pre-production or later
+	 * silicon does not have this issue.
+	 */
+	status = "disabled";
+
+	sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <20000000>;
+		spi-rx-bus-width = <1>;
+		reg = <0>;
+	};
+};
+
+&usb {
+	status = "okay";
+	dr_mode = "host";
+};
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index f80df225f72b..2cb08ed0946d 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -3,249 +3,10 @@
 
 /dts-v1/;
 
-#include "mpfs.dtsi"
-#include "mpfs-icicle-kit-fabric.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
+#include "mpfs-icicle-kit-common.dtsi"
 
 / {
 	model = "Microchip PolarFire-SoC Icicle Kit";
 	compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
 		     "microchip,mpfs";
-
-	aliases {
-		ethernet0 = &mac1;
-		serial0 = &mmuart0;
-		serial1 = &mmuart1;
-		serial2 = &mmuart2;
-		serial3 = &mmuart3;
-		serial4 = &mmuart4;
-	};
-
-	chosen {
-		stdout-path = "serial1:115200n8";
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led-1 {
-			gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
-			color = <LED_COLOR_ID_RED>;
-			label = "led1";
-		};
-
-		led-2 {
-			gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
-			color = <LED_COLOR_ID_RED>;
-			label = "led2";
-		};
-
-		led-3 {
-			gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
-			color = <LED_COLOR_ID_AMBER>;
-			label = "led3";
-		};
-
-		led-4 {
-			gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
-			color = <LED_COLOR_ID_AMBER>;
-			label = "led4";
-		};
-	};
-
-	ddrc_cache_lo: memory@80000000 {
-		device_type = "memory";
-		reg = <0x0 0x80000000 0x0 0x40000000>;
-		status = "okay";
-	};
-
-	ddrc_cache_hi: memory@1040000000 {
-		device_type = "memory";
-		reg = <0x10 0x40000000 0x0 0x40000000>;
-		status = "okay";
-	};
-
-	reserved-memory {
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
-
-		hss_payload: region@BFC00000 {
-			reg = <0x0 0xBFC00000 0x0 0x400000>;
-			no-map;
-		};
-	};
-};
-
-&core_pwm0 {
-	status = "okay";
-};
-
-&gpio2 {
-	interrupts = <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>;
-	status = "okay";
-};
-
-&i2c0 {
-	status = "okay";
-};
-
-&i2c1 {
-	status = "okay";
-
-	power-monitor@10 {
-		compatible = "microchip,pac1934";
-		reg = <0x10>;
-
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		channel@1 {
-			reg = <0x1>;
-			shunt-resistor-micro-ohms = <10000>;
-			label = "VDDREG";
-		};
-
-		channel@2 {
-			reg = <0x2>;
-			shunt-resistor-micro-ohms = <10000>;
-			label = "VDDA25";
-		};
-
-		channel@3 {
-			reg = <0x3>;
-			shunt-resistor-micro-ohms = <10000>;
-			label = "VDD25";
-		};
-
-		channel@4 {
-			reg = <0x4>;
-			shunt-resistor-micro-ohms = <10000>;
-			label = "VDDA_REG";
-		};
-	};
-};
-
-&i2c2 {
-	status = "okay";
-};
-
-&mac0 {
-	phy-mode = "sgmii";
-	phy-handle = <&phy0>;
-	status = "okay";
-};
-
-&mac1 {
-	phy-mode = "sgmii";
-	phy-handle = <&phy1>;
-	status = "okay";
-
-	phy1: ethernet-phy@9 {
-		reg = <9>;
-	};
-
-	phy0: ethernet-phy@8 {
-		reg = <8>;
-	};
-};
-
-&mbox {
-	status = "okay";
-};
-
-&mmc {
-	bus-width = <4>;
-	disable-wp;
-	cap-sd-highspeed;
-	cap-mmc-highspeed;
-	mmc-ddr-1_8v;
-	mmc-hs200-1_8v;
-	sd-uhs-sdr12;
-	sd-uhs-sdr25;
-	sd-uhs-sdr50;
-	sd-uhs-sdr104;
-	status = "okay";
-};
-
-&mmuart1 {
-	status = "okay";
-};
-
-&mmuart2 {
-	status = "okay";
-};
-
-&mmuart3 {
-	status = "okay";
-};
-
-&mmuart4 {
-	status = "okay";
-};
-
-&pcie {
-	status = "okay";
-};
-
-&qspi {
-	status = "okay";
-};
-
-&refclk {
-	clock-frequency = <125000000>;
-};
-
-&refclk_ccc {
-	clock-frequency = <50000000>;
-};
-
-&rtc {
-	status = "okay";
-};
-
-&spi0 {
-	status = "okay";
-};
-
-&spi1 {
-	status = "okay";
-};
-
-&syscontroller {
-	status = "okay";
-};
-
-&syscontroller_qspi {
-	/*
-	 * The flash *is* there, but Icicle kits that have engineering sample
-	 * silicon (write?) access to this flash to non-functional. The system
-	 * controller itself can actually access it, but the MSS cannot write
-	 * an image there. Instantiating a coreQSPI in the fabric & connecting
-	 * it to the flash instead should work though. Pre-production or later
-	 * silicon does not have this issue.
-	 */
-	status = "disabled";
-
-	sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT
-		compatible = "jedec,spi-nor";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		spi-max-frequency = <20000000>;
-		spi-rx-bus-width = <1>;
-		reg = <0>;
-	};
-};
-
-&usb {
-	status = "okay";
-	dr_mode = "host";
 };
-- 
2.34.1

[PATCH v1 2/5] dt-bindings: riscv: microchip: document icicle kit with production device

[Valentina Fernandez]

With the introduction of the Icicle Kit using the production MPFS250T
device, it's necessary to distinguish it from the engineering sample
(-es) variant. Engineering samples cannot write to flash from the MSS,
as noted in the PolarFire SoC FPGA ES errata.

Add specific compatibles for the Icicle Kit with Production device
(MPFS250T) and Icicle Kit with Engineering Sample (MPFS250T_ES).

The icicle kit reference designs in the v2025.07 release include the
Mi-V IHC IP v2, used to send/receive data between clusters when
using Asymmetric Multiprocessing (AMP) mode.

In reference design releases prior to v2025.07, the MI-V IHC subsystem
was included as a proof of concept in the design prior to becoming an
IP available in the Libero catalog.

Among other improvements, the new Mi-V IHC IP v2 includes some
changes to the register map. For this reason, make use of a new
reference design compatible to denote that v2025.07 reference design
releases are not backwards compatible.

Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com>
---
 Documentation/devicetree/bindings/riscv/microchip.yaml | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
index 78ce76ae1b6d..8ddc5c02973e 100644
--- a/Documentation/devicetree/bindings/riscv/microchip.yaml
+++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
@@ -18,10 +18,18 @@ properties:
     const: '/'
   compatible:
     oneOf:
+      - items:
+          - const: microchip,mpfs-icicle-prod-reference-rtl-v2507
+          - const: microchip,mpfs-icicle-kit-prod
+          - const: microchip,mpfs-icicle-kit
+          - const: microchip,mpfs-prod
+          - const: microchip,mpfs
+
       - items:
           - enum:
               - microchip,mpfs-icicle-reference-rtlv2203
               - microchip,mpfs-icicle-reference-rtlv2210
+              - microchip,mpfs-icicle-es-reference-rtl-v2507
           - const: microchip,mpfs-icicle-kit
           - const: microchip,mpfs
 
-- 
2.34.1

[PATCH v1 3/5] riscv: dts: microchip: add icicle kit with production device

[Valentina Fernandez]

With the introduction of the Icicle Kit using the production MPFS250T
device, it's necessary to distinguish it from the engineering sample
(-es) variant. Engineering samples cannot write to flash from the MSS,
as noted in the PolarFire SoC FPGA ES errata.

Add a new device tree (mpfs-icicle-kit-prod.dts) for the production
board which includes the icicle kit common dtsi and enable the system
controller SPI flash, which is only accessible on production silicon.

Remove redundant board compatible from fabric dtsi and update board
compatibles for v2025.07 release, which includes Mi-V IHC v2 for AMP
cluster communication.

Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com>
---
 arch/riscv/boot/dts/microchip/Makefile        |  1 +
 .../dts/microchip/mpfs-icicle-kit-common.dtsi |  4 ++++
 .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 23 ++++++++++++++++---
 .../dts/microchip/mpfs-icicle-kit-prod.dts    | 23 +++++++++++++++++++
 .../boot/dts/microchip/mpfs-icicle-kit.dts    |  3 ++-
 5 files changed, 50 insertions(+), 4 deletions(-)
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts

diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
index f51aeeb9fd3b..1e2f4e41bf0d 100644
--- a/arch/riscv/boot/dts/microchip/Makefile
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-beaglev-fire.dtb
 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
+dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit-prod.dtb
 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb
 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi
index eafea3b69cd7..5c7a8ffad85b 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi
@@ -134,6 +134,10 @@ &i2c2 {
 	status = "okay";
 };
 
+&ihc {
+	status = "okay";
+};
+
 &mac0 {
 	phy-mode = "sgmii";
 	phy-handle = <&phy0>;
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index a6dda55a2d1d..92a49f91013e 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -2,9 +2,6 @@
 /* Copyright (c) 2020-2021 Microchip Technology Inc */
 
 / {
-	compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
-		     "microchip,mpfs";
-
 	core_pwm0: pwm@40000000 {
 		compatible = "microchip,corepwm-rtl-v4";
 		reg = <0x0 0x40000000 0x0 0xF0>;
@@ -26,6 +23,26 @@ i2c2: i2c@40000200 {
 		status = "disabled";
 	};
 
+	ihc: mailbox {
+		compatible = "microchip,sbi-ipc";
+		interrupt-parent = <&plic>;
+		interrupts = <180>, <179>, <178>, <177>;
+		interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
+		#mbox-cells = <1>;
+		status = "disabled";
+	};
+
+	mailbox@50000000 {
+		compatible = "microchip,miv-ihc-rtl-v2";
+		microchip,ihc-chan-disabled-mask = /bits/ 16 <0>;
+		reg = <0x0 0x50000000 0x0 0x1c000>;
+		interrupt-parent = <&plic>;
+		interrupts = <180>, <179>, <178>, <177>;
+		interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
+		#mbox-cells = <1>;
+		status = "disabled";
+	};
+
 	pcie: pcie@3000000000 {
 		compatible = "microchip,pcie-host-1.0";
 		#address-cells = <0x3>;
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts
new file mode 100644
index 000000000000..8afedece89d1
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2025 Microchip Technology Inc */
+
+/dts-v1/;
+
+#include "mpfs-icicle-kit-common.dtsi"
+
+/ {
+	model = "Microchip PolarFire-SoC Icicle Kit (Production Silicon)";
+	compatible = "microchip,mpfs-icicle-prod-reference-rtl-v2507",
+		     "microchip,mpfs-icicle-kit-prod",
+		     "microchip,mpfs-icicle-kit",
+		     "microchip,mpfs-prod",
+		     "microchip,mpfs";
+};
+
+&syscontroller {
+	microchip,bitstream-flash = <&sys_ctrl_flash>;
+};
+
+&syscontroller_qspi {
+	status = "okay";
+};
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index 2cb08ed0946d..556aa9638282 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -7,6 +7,7 @@
 
 / {
 	model = "Microchip PolarFire-SoC Icicle Kit";
-	compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
+	compatible = "microchip,mpfs-icicle-es-reference-rtl-v2507",
+		     "microchip,mpfs-icicle-kit",
 		     "microchip,mpfs";
 };
-- 
2.34.1

[PATCH v1 4/5] dt-bindings: riscv: microchip: document Discovery Kit

[Valentina Fernandez]

The Discovery Kit (MPFS-DISCO-KIT) is a development board featuring
a Microchip PolarFire SoC MPFS095T.

Link: https://www.microchip.com/en-us/development-tool/mpfs-disco-kit
Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com>
---
 Documentation/devicetree/bindings/riscv/microchip.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml
index 8ddc5c02973e..381d6eb6672e 100644
--- a/Documentation/devicetree/bindings/riscv/microchip.yaml
+++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
@@ -33,6 +33,11 @@ properties:
           - const: microchip,mpfs-icicle-kit
           - const: microchip,mpfs
 
+      - items:
+          - const: microchip,mpfs-disco-kit-reference-rtl-v2507
+          - const: microchip,mpfs-disco-kit
+          - const: microchip,mpfs
+
       - items:
           - enum:
               - aldec,tysom-m-mpfs250t-rev2
-- 
2.34.1

[PATCH v1 5/5] riscv: dts: microchip: add a device tree for Discovery Kit

[Valentina Fernandez]

Add a minimal device tree for the Microchip PolarFire SoC Discovery Kit.
The Discovery Kit is a cost-optimized board based on PolarFire SoC
MPFS095T and features:

- 1 GB DDR4x16
- 1x Gigabit Ethernet
- 3x UARTs
- Raspberry Pi connector
- mikroBus connector
- microSD card connector

Link: https://www.microchip.com/en-us/development-tool/mpfs-disco-kit
Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com>
---
 arch/riscv/boot/dts/microchip/Makefile        |   1 +
 .../dts/microchip/mpfs-disco-kit-fabric.dtsi  |  58 ++++++
 .../boot/dts/microchip/mpfs-disco-kit.dts     | 191 ++++++++++++++++++
 3 files changed, 250 insertions(+)
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi
 create mode 100644 arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts

diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
index 1e2f4e41bf0d..345ed7a48cc1 100644
--- a/arch/riscv/boot/dts/microchip/Makefile
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-beaglev-fire.dtb
+dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-disco-kit.dtb
 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit-prod.dtb
 dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb
diff --git a/arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi
new file mode 100644
index 000000000000..f9b94b5ead96
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2025 Microchip Technology Inc */
+
+/ {
+	core_pwm0: pwm@40000000 {
+		compatible = "microchip,corepwm-rtl-v4";
+		reg = <0x0 0x40000000 0x0 0xF0>;
+		microchip,sync-update-mask = /bits/ 32 <0>;
+		#pwm-cells = <3>;
+		clocks = <&ccc_sw CLK_CCC_PLL0_OUT3>;
+		status = "disabled";
+	};
+
+	i2c2: i2c@40000200 {
+		compatible = "microchip,corei2c-rtl-v7";
+		reg = <0x0 0x40000200 0x0 0x100>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&ccc_sw CLK_CCC_PLL0_OUT3>;
+		interrupt-parent = <&plic>;
+		interrupts = <122>;
+		clock-frequency = <100000>;
+		status = "disabled";
+	};
+
+	ihc: mailbox {
+		compatible = "microchip,sbi-ipc";
+		interrupt-parent = <&plic>;
+		interrupts = <180>, <179>, <178>, <177>;
+		interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
+		#mbox-cells = <1>;
+		status = "disabled";
+	};
+
+	mailbox@50000000 {
+		compatible = "microchip,miv-ihc-rtl-v2";
+		microchip,ihc-chan-disabled-mask = /bits/ 16 <0>;
+		reg = <0x0 0x50000000 0x0 0x1c000>;
+		interrupt-parent = <&plic>;
+		interrupts = <180>, <179>, <178>, <177>;
+		interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
+		#mbox-cells = <1>;
+		status = "disabled";
+	};
+
+	refclk_ccc: cccrefclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+	};
+};
+
+&ccc_sw {
+	clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
+		 <&refclk_ccc>, <&refclk_ccc>;
+	clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
+		      "dll0_ref", "dll1_ref";
+	status = "okay";
+};
diff --git a/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts
new file mode 100644
index 000000000000..742369470ab0
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2025 Microchip Technology Inc */
+
+/dts-v1/;
+
+#include "mpfs.dtsi"
+#include "mpfs-disco-kit-fabric.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	model = "Microchip PolarFire-SoC Discovery Kit";
+	compatible = "microchip,mpfs-disco-kit-reference-rtl-v2507",
+		     "microchip,mpfs-disco-kit",
+		     "microchip,mpfs";
+
+	aliases {
+		ethernet0 = &mac0;
+		serial4 = &mmuart4;
+	};
+
+	chosen {
+		stdout-path = "serial4:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-1 {
+			gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
+			color = <LED_COLOR_ID_AMBER>;
+			label = "led1";
+		};
+
+		led-2 {
+			gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
+			color = <LED_COLOR_ID_RED>;
+			label = "led2";
+		};
+
+		led-3 {
+			gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+			color = <LED_COLOR_ID_AMBER>;
+			label = "led3";
+		};
+
+		led-4 {
+			gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+			color = <LED_COLOR_ID_RED>;
+			label = "led4";
+		};
+
+		led-5 {
+			gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
+			color = <LED_COLOR_ID_AMBER>;
+			label = "led5";
+		};
+
+		led-6 {
+			gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
+			color = <LED_COLOR_ID_RED>;
+			label = "led6";
+		};
+
+		led-7 {
+			gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>;
+			color = <LED_COLOR_ID_AMBER>;
+			label = "led7";
+		};
+
+		led-8 {
+			gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+			color = <LED_COLOR_ID_RED>;
+			label = "led8";
+		};
+	};
+
+	ddrc_cache_lo: memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x40000000>;
+		status = "okay";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		hss_payload: region@BFC00000 {
+			reg = <0x0 0xBFC00000 0x0 0x400000>;
+			no-map;
+		};
+	};
+};
+
+&core_pwm0 {
+	status = "okay";
+};
+
+&gpio1 {
+	interrupts = <27>, <28>, <29>, <30>,
+		     <31>, <32>, <33>, <47>,
+		     <35>, <36>, <37>, <38>,
+		     <39>, <40>, <41>, <42>,
+		     <43>, <44>, <45>, <46>,
+		     <47>, <48>, <49>, <50>;
+	status = "okay";
+};
+
+&gpio2 {
+	interrupts = <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>;
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&ihc {
+	status = "okay";
+};
+
+&mac0 {
+	phy-mode = "sgmii";
+	phy-handle = <&phy0>;
+	status = "okay";
+
+	phy0: ethernet-phy@b {
+		reg = <0xb>;
+	};
+};
+
+&mbox {
+	status = "okay";
+};
+
+&mmc {
+	bus-width = <4>;
+	disable-wp;
+	cap-sd-highspeed;
+	cap-mmc-highspeed;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	no-1-8-v;
+	status = "okay";
+};
+
+&mmuart1 {
+	status = "okay";
+};
+
+&mmuart4 {
+	status = "okay";
+};
+
+&refclk {
+	clock-frequency = <125000000>;
+};
+
+&refclk_ccc {
+	clock-frequency = <50000000>;
+};
+
+&rtc {
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+};
+
+&spi1 {
+	status = "okay";
+};
+
+&syscontroller {
+	status = "okay";
+};
-- 
2.34.1

Re: [PATCH v1 0/5] Icicle Kit with prod device and Discovery Kit support

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

On Mon, 25 Aug 2025 17:19:47 +0100, Valentina Fernandez wrote:
> With the introduction of the Icicle Kit with the production device
> (MPFS250T) to the market, it's necessary to distinguish it from the
> engineering sample (-es) variant. This is because engineering samples
> cannot write to flash from the MSS, as noted in the PolarFire SoC
> FPGA ES errata.
> 
> This series adds a common board DTSI for the Icicle Kit, containing
> hardware shared by both the engineering sample and production
> versions, as well as a DTS for each Icicle Kit variant.
> 
> [...]

Applied to riscv-dt-for-next, thanks!

[1/5] riscv: dts: microchip: add common board dtsi for icicle kit variants
      https://git.kernel.org/conor/c/2a95aaa34dfe
[2/5] dt-bindings: riscv: microchip: document icicle kit with production device
      https://git.kernel.org/conor/c/4b9e63bb6491
[3/5] riscv: dts: microchip: add icicle kit with production device
      https://git.kernel.org/conor/c/1ba401aae7a1
[4/5] dt-bindings: riscv: microchip: document Discovery Kit
      https://git.kernel.org/conor/c/0d880b095a19
[5/5] riscv: dts: microchip: add a device tree for Discovery Kit
      https://git.kernel.org/conor/c/f66eb149b876

Thanks,
Conor.

Re: [PATCH v1 5/5] riscv: dts: microchip: add a device tree for Discovery Kit

[Krzysztof Kozlowski]

On 25/08/2025 18:19, Valentina Fernandez wrote:
> +++ b/arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi
> @@ -0,0 +1,58 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2020-2025 Microchip Technology Inc */
> +
> +/ {
> +	core_pwm0: pwm@40000000 {
> +		compatible = "microchip,corepwm-rtl-v4";
> +		reg = <0x0 0x40000000 0x0 0xF0>;
> +		microchip,sync-update-mask = /bits/ 32 <0>;
> +		#pwm-cells = <3>;
> +		clocks = <&ccc_sw CLK_CCC_PLL0_OUT3>;
> +		status = "disabled";
> +	};
> +
> +	i2c2: i2c@40000200 {
> +		compatible = "microchip,corei2c-rtl-v7";
> +		reg = <0x0 0x40000200 0x0 0x100>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		clocks = <&ccc_sw CLK_CCC_PLL0_OUT3>;
> +		interrupt-parent = <&plic>;
> +		interrupts = <122>;
> +		clock-frequency = <100000>;
> +		status = "disabled";
> +	};
> +
> +	ihc: mailbox {
> +		compatible = "microchip,sbi-ipc";
> +		interrupt-parent = <&plic>;
> +		interrupts = <180>, <179>, <178>, <177>;
> +		interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
> +		#mbox-cells = <1>;
> +		status = "disabled";
> +	};
> +
> +	mailbox@50000000 {
> +		compatible = "microchip,miv-ihc-rtl-v2";
> +		microchip,ihc-chan-disabled-mask = /bits/ 16 <0>;

Does not look like following DTS coding style - order of properties.

> +		reg = <0x0 0x50000000 0x0 0x1c000>;
> +		interrupt-parent = <&plic>;
> +		interrupts = <180>, <179>, <178>, <177>;
> +		interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
> +		#mbox-cells = <1>;
> +		status = "disabled";
> +	};
> +
> +	refclk_ccc: cccrefclk {

Please use name for all fixed clocks which matches current format
recommendation: 'clock-<freq>' (see also the pattern in the binding for
any other options).

https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml

Or anything more reasonable than just bunch of letters.

> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;


> +	};
> +};
> +
> +&ccc_sw {
> +	clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
> +		 <&refclk_ccc>, <&refclk_ccc>;
> +	clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
> +		      "dll0_ref", "dll1_ref";
> +	status = "okay";
> +};
> diff --git a/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts
> new file mode 100644
> index 000000000000..742369470ab0
> --- /dev/null
> +++ b/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts
> @@ -0,0 +1,191 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2020-2025 Microchip Technology Inc */
> +
> +/dts-v1/;
> +
> +#include "mpfs.dtsi"
> +#include "mpfs-disco-kit-fabric.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/leds/common.h>
> +
> +/ {
> +	model = "Microchip PolarFire-SoC Discovery Kit";
> +	compatible = "microchip,mpfs-disco-kit-reference-rtl-v2507",
> +		     "microchip,mpfs-disco-kit",
> +		     "microchip,mpfs";
> +
> +	aliases {
> +		ethernet0 = &mac0;
> +		serial4 = &mmuart4;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial4:115200n8";
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +
> +		led-1 {
> +			gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
> +			color = <LED_COLOR_ID_AMBER>;
> +			label = "led1";
> +		};
> +
> +		led-2 {
> +			gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
> +			color = <LED_COLOR_ID_RED>;
> +			label = "led2";
> +		};
> +
> +		led-3 {
> +			gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> +			color = <LED_COLOR_ID_AMBER>;
> +			label = "led3";
> +		};
> +
> +		led-4 {
> +			gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
> +			color = <LED_COLOR_ID_RED>;
> +			label = "led4";
> +		};
> +
> +		led-5 {
> +			gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
> +			color = <LED_COLOR_ID_AMBER>;
> +			label = "led5";
> +		};
> +
> +		led-6 {
> +			gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
> +			color = <LED_COLOR_ID_RED>;
> +			label = "led6";
> +		};
> +
> +		led-7 {
> +			gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>;
> +			color = <LED_COLOR_ID_AMBER>;
> +			label = "led7";
> +		};
> +
> +		led-8 {
> +			gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
> +			color = <LED_COLOR_ID_RED>;
> +			label = "led8";
> +		};
> +	};
> +
> +	ddrc_cache_lo: memory@80000000 {
> +		device_type = "memory";
> +		reg = <0x0 0x80000000 0x0 0x40000000>;
> +		status = "okay";

Why? Did you disable it anywhere?

> +	};
> +
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		hss_payload: region@BFC00000 {

Don't mix cases. Should be lowercase hex everywhere.

Best regards,
Krzysztof

Re: [PATCH v1 5/5] riscv: dts: microchip: add a device tree for Discovery Kit

[Valentina.FernandezAlanis]

On 28/08/2025 18:46, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On 25/08/2025 18:19, Valentina Fernandez wrote:
>> +++ b/arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi
>> @@ -0,0 +1,58 @@
>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>> +/* Copyright (c) 2020-2025 Microchip Technology Inc */
>> +
>> +/ {
>> +     core_pwm0: pwm@40000000 {
>> +             compatible = "microchip,corepwm-rtl-v4";
>> +             reg = <0x0 0x40000000 0x0 0xF0>;
>> +             microchip,sync-update-mask = /bits/ 32 <0>;
>> +             #pwm-cells = <3>;
>> +             clocks = <&ccc_sw CLK_CCC_PLL0_OUT3>;
>> +             status = "disabled";
>> +     };
>> +
>> +     i2c2: i2c@40000200 {
>> +             compatible = "microchip,corei2c-rtl-v7";
>> +             reg = <0x0 0x40000200 0x0 0x100>;
>> +             #address-cells = <1>;
>> +             #size-cells = <0>;
>> +             clocks = <&ccc_sw CLK_CCC_PLL0_OUT3>;
>> +             interrupt-parent = <&plic>;
>> +             interrupts = <122>;
>> +             clock-frequency = <100000>;
>> +             status = "disabled";
>> +     };
>> +
>> +     ihc: mailbox {
>> +             compatible = "microchip,sbi-ipc";
>> +             interrupt-parent = <&plic>;
>> +             interrupts = <180>, <179>, <178>, <177>;
>> +             interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
>> +             #mbox-cells = <1>;
>> +             status = "disabled";
>> +     };
>> +
>> +     mailbox@50000000 {
>> +             compatible = "microchip,miv-ihc-rtl-v2";
>> +             microchip,ihc-chan-disabled-mask = /bits/ 16 <0>;
> 
> Does not look like following DTS coding style - order of properties.
> 
>> +             reg = <0x0 0x50000000 0x0 0x1c000>;
>> +             interrupt-parent = <&plic>;
>> +             interrupts = <180>, <179>, <178>, <177>;
>> +             interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
>> +             #mbox-cells = <1>;
>> +             status = "disabled";
>> +     };
>> +
>> +     refclk_ccc: cccrefclk {
> 
> Please use name for all fixed clocks which matches current format
> recommendation: 'clock-<freq>' (see also the pattern in the binding for
> any other options).
> 
> https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml
The fabric dtsi describes elements configured by the FPGA bitstream. 
This node is named as such because the Clock Conditioner Circuit CCC's 
reference clock source is set by the FPGA bitstream, while its frequency 
is determined by an on-board oscillator.

Hope this clarifies the rationale behind the node name.

Thanks,
Valentina

> 
> Or anything more reasonable than just bunch of letters.
> 
>> +             compatible = "fixed-clock";
>> +             #clock-cells = <0>;
> 
> 
>> +     };
>> +};
>> +
>> +&ccc_sw {
>> +     clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
>> +              <&refclk_ccc>, <&refclk_ccc>;
>> +     clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
>> +                   "dll0_ref", "dll1_ref";
>> +     status = "okay";
>> +};
>> diff --git a/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts
>> new file mode 100644
>> index 000000000000..742369470ab0
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/microchip/mpfs-disco-kit.dts
>> @@ -0,0 +1,191 @@
>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>> +/* Copyright (c) 2020-2025 Microchip Technology Inc */
>> +
>> +/dts-v1/;
>> +
>> +#include "mpfs.dtsi"
>> +#include "mpfs-disco-kit-fabric.dtsi"
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/leds/common.h>
>> +
>> +/ {
>> +     model = "Microchip PolarFire-SoC Discovery Kit";
>> +     compatible = "microchip,mpfs-disco-kit-reference-rtl-v2507",
>> +                  "microchip,mpfs-disco-kit",
>> +                  "microchip,mpfs";
>> +
>> +     aliases {
>> +             ethernet0 = &mac0;
>> +             serial4 = &mmuart4;
>> +     };
>> +
>> +     chosen {
>> +             stdout-path = "serial4:115200n8";
>> +     };
>> +
>> +     leds {
>> +             compatible = "gpio-leds";
>> +
>> +             led-1 {
>> +                     gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
>> +                     color = <LED_COLOR_ID_AMBER>;
>> +                     label = "led1";
>> +             };
>> +
>> +             led-2 {
>> +                     gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
>> +                     color = <LED_COLOR_ID_RED>;
>> +                     label = "led2";
>> +             };
>> +
>> +             led-3 {
>> +                     gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
>> +                     color = <LED_COLOR_ID_AMBER>;
>> +                     label = "led3";
>> +             };
>> +
>> +             led-4 {
>> +                     gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
>> +                     color = <LED_COLOR_ID_RED>;
>> +                     label = "led4";
>> +             };
>> +
>> +             led-5 {
>> +                     gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
>> +                     color = <LED_COLOR_ID_AMBER>;
>> +                     label = "led5";
>> +             };
>> +
>> +             led-6 {
>> +                     gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
>> +                     color = <LED_COLOR_ID_RED>;
>> +                     label = "led6";
>> +             };
>> +
>> +             led-7 {
>> +                     gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>;
>> +                     color = <LED_COLOR_ID_AMBER>;
>> +                     label = "led7";
>> +             };
>> +
>> +             led-8 {
>> +                     gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
>> +                     color = <LED_COLOR_ID_RED>;
>> +                     label = "led8";
>> +             };
>> +     };
>> +
>> +     ddrc_cache_lo: memory@80000000 {
>> +             device_type = "memory";
>> +             reg = <0x0 0x80000000 0x0 0x40000000>;
>> +             status = "okay";
> 
> Why? Did you disable it anywhere?
> 
>> +     };
>> +
>> +     reserved-memory {
>> +             #address-cells = <2>;
>> +             #size-cells = <2>;
>> +             ranges;
>> +
>> +             hss_payload: region@BFC00000 {
> 
> Don't mix cases. Should be lowercase hex everywhere.
> 
> Best regards,
> Krzysztof

Re: [PATCH v1 5/5] riscv: dts: microchip: add a device tree for Discovery Kit

[Krzysztof Kozlowski]

On 01/09/2025 17:28, Valentina.FernandezAlanis@microchip.com wrote:
> On 28/08/2025 18:46, Krzysztof Kozlowski wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On 25/08/2025 18:19, Valentina Fernandez wrote:
>>> +++ b/arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi
>>> @@ -0,0 +1,58 @@
>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>> +/* Copyright (c) 2020-2025 Microchip Technology Inc */
>>> +
>>> +/ {
>>> +     core_pwm0: pwm@40000000 {
>>> +             compatible = "microchip,corepwm-rtl-v4";
>>> +             reg = <0x0 0x40000000 0x0 0xF0>;
>>> +             microchip,sync-update-mask = /bits/ 32 <0>;
>>> +             #pwm-cells = <3>;
>>> +             clocks = <&ccc_sw CLK_CCC_PLL0_OUT3>;
>>> +             status = "disabled";
>>> +     };
>>> +
>>> +     i2c2: i2c@40000200 {
>>> +             compatible = "microchip,corei2c-rtl-v7";
>>> +             reg = <0x0 0x40000200 0x0 0x100>;
>>> +             #address-cells = <1>;
>>> +             #size-cells = <0>;
>>> +             clocks = <&ccc_sw CLK_CCC_PLL0_OUT3>;
>>> +             interrupt-parent = <&plic>;
>>> +             interrupts = <122>;
>>> +             clock-frequency = <100000>;
>>> +             status = "disabled";
>>> +     };
>>> +
>>> +     ihc: mailbox {
>>> +             compatible = "microchip,sbi-ipc";
>>> +             interrupt-parent = <&plic>;
>>> +             interrupts = <180>, <179>, <178>, <177>;
>>> +             interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
>>> +             #mbox-cells = <1>;
>>> +             status = "disabled";
>>> +     };
>>> +
>>> +     mailbox@50000000 {
>>> +             compatible = "microchip,miv-ihc-rtl-v2";
>>> +             microchip,ihc-chan-disabled-mask = /bits/ 16 <0>;
>>
>> Does not look like following DTS coding style - order of properties.
>>
>>> +             reg = <0x0 0x50000000 0x0 0x1c000>;
>>> +             interrupt-parent = <&plic>;
>>> +             interrupts = <180>, <179>, <178>, <177>;
>>> +             interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
>>> +             #mbox-cells = <1>;
>>> +             status = "disabled";
>>> +     };
>>> +
>>> +     refclk_ccc: cccrefclk {
>>
>> Please use name for all fixed clocks which matches current format
>> recommendation: 'clock-<freq>' (see also the pattern in the binding for
>> any other options).
>>
>> https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml
> The fabric dtsi describes elements configured by the FPGA bitstream. 
> This node is named as such because the Clock Conditioner Circuit CCC's 
> reference clock source is set by the FPGA bitstream, while its frequency 
> is determined by an on-board oscillator.
> 
> Hope this clarifies the rationale behind the node name.
No, because there is no style naming clocks like this. Neither proper
suffix, nor prefix. Use standard naming.

And all other comments you ignored?

Best regards,
Krzysztof

Re: [PATCH v1 5/5] riscv: dts: microchip: add a device tree for Discovery Kit

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1100 bytes --]

On Tue, Sep 02, 2025 at 08:22:02AM +0200, Krzysztof Kozlowski wrote:

> >>> +     refclk_ccc: cccrefclk {
> >>
> >> Please use name for all fixed clocks which matches current format
> >> recommendation: 'clock-<freq>' (see also the pattern in the binding for
> >> any other options).
> >>
> >> https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml
> > The fabric dtsi describes elements configured by the FPGA bitstream. 
> > This node is named as such because the Clock Conditioner Circuit CCC's 
> > reference clock source is set by the FPGA bitstream, while its frequency 
> > is determined by an on-board oscillator.
> > 
> > Hope this clarifies the rationale behind the node name.
> No, because there is no style naming clocks like this. Neither proper
> suffix, nor prefix. Use standard naming.

So you want all fixed frequency clocks to be named "clk-foo" when
"clk-<freq>" is not suitable? Fine if you do, but I didn't realise that
it was required and haven't been keeping an eye out for it.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v1 5/5] riscv: dts: microchip: add a device tree for Discovery Kit

[Valentina.FernandezAlanis]

On 02/09/2025 07:22, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On 01/09/2025 17:28, Valentina.FernandezAlanis@microchip.com wrote:
>> On 28/08/2025 18:46, Krzysztof Kozlowski wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On 25/08/2025 18:19, Valentina Fernandez wrote:
>>>> +++ b/arch/riscv/boot/dts/microchip/mpfs-disco-kit-fabric.dtsi
>>>> @@ -0,0 +1,58 @@
>>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>>> +/* Copyright (c) 2020-2025 Microchip Technology Inc */
>>>> +
>>>> +/ {
>>>> +     core_pwm0: pwm@40000000 {
>>>> +             compatible = "microchip,corepwm-rtl-v4";
>>>> +             reg = <0x0 0x40000000 0x0 0xF0>;
>>>> +             microchip,sync-update-mask = /bits/ 32 <0>;
>>>> +             #pwm-cells = <3>;
>>>> +             clocks = <&ccc_sw CLK_CCC_PLL0_OUT3>;
>>>> +             status = "disabled";
>>>> +     };
>>>> +
>>>> +     i2c2: i2c@40000200 {
>>>> +             compatible = "microchip,corei2c-rtl-v7";
>>>> +             reg = <0x0 0x40000200 0x0 0x100>;
>>>> +             #address-cells = <1>;
>>>> +             #size-cells = <0>;
>>>> +             clocks = <&ccc_sw CLK_CCC_PLL0_OUT3>;
>>>> +             interrupt-parent = <&plic>;
>>>> +             interrupts = <122>;
>>>> +             clock-frequency = <100000>;
>>>> +             status = "disabled";
>>>> +     };
>>>> +
>>>> +     ihc: mailbox {
>>>> +             compatible = "microchip,sbi-ipc";
>>>> +             interrupt-parent = <&plic>;
>>>> +             interrupts = <180>, <179>, <178>, <177>;
>>>> +             interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
>>>> +             #mbox-cells = <1>;
>>>> +             status = "disabled";
>>>> +     };
>>>> +
>>>> +     mailbox@50000000 {
>>>> +             compatible = "microchip,miv-ihc-rtl-v2";
>>>> +             microchip,ihc-chan-disabled-mask = /bits/ 16 <0>;
>>>
>>> Does not look like following DTS coding style - order of properties.
>>>
>>>> +             reg = <0x0 0x50000000 0x0 0x1c000>;
>>>> +             interrupt-parent = <&plic>;
>>>> +             interrupts = <180>, <179>, <178>, <177>;
>>>> +             interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
>>>> +             #mbox-cells = <1>;
>>>> +             status = "disabled";
>>>> +     };
>>>> +
>>>> +     refclk_ccc: cccrefclk {
>>>
>>> Please use name for all fixed clocks which matches current format
>>> recommendation: 'clock-<freq>' (see also the pattern in the binding for
>>> any other options).
>>>
>>> https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml
>> The fabric dtsi describes elements configured by the FPGA bitstream.
>> This node is named as such because the Clock Conditioner Circuit CCC's
>> reference clock source is set by the FPGA bitstream, while its frequency
>> is determined by an on-board oscillator.
>>
>> Hope this clarifies the rationale behind the node name.
> No, because there is no style naming clocks like this. Neither proper
> suffix, nor prefix. Use standard naming.
> 
> And all other comments you ignored?
I sent a v2 with the rest of the comments addressed. I didn't notice you 
were still not happy with the clock node name, please ignore the v2.

> 
> Best regards,
> Krzysztof

Re: [PATCH v1 5/5] riscv: dts: microchip: add a device tree for Discovery Kit

[Krzysztof Kozlowski]

On 02/09/2025 10:31, Conor Dooley wrote:
> On Tue, Sep 02, 2025 at 08:22:02AM +0200, Krzysztof Kozlowski wrote:
> 
>>>>> +     refclk_ccc: cccrefclk {
>>>>
>>>> Please use name for all fixed clocks which matches current format
>>>> recommendation: 'clock-<freq>' (see also the pattern in the binding for
>>>> any other options).
>>>>
>>>> https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml
>>> The fabric dtsi describes elements configured by the FPGA bitstream. 
>>> This node is named as such because the Clock Conditioner Circuit CCC's 
>>> reference clock source is set by the FPGA bitstream, while its frequency 
>>> is determined by an on-board oscillator.
>>>
>>> Hope this clarifies the rationale behind the node name.
>> No, because there is no style naming clocks like this. Neither proper
>> suffix, nor prefix. Use standard naming.
> 
> So you want all fixed frequency clocks to be named "clk-foo" when
> "clk-<freq>" is not suitable? Fine if you do, but I didn't realise that
> it was required and haven't been keeping an eye out for it.

Recommended is to just use consistent suffixes or prefixes. Binding asks
for "clock-" so that's what I propose to use here.

Best regards,
Krzysztof

Re: [PATCH v1 5/5] riscv: dts: microchip: add a device tree for Discovery Kit

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1437 bytes --]

On Tue, Sep 02, 2025 at 03:47:56PM +0200, Krzysztof Kozlowski wrote:
> On 02/09/2025 10:31, Conor Dooley wrote:
> > On Tue, Sep 02, 2025 at 08:22:02AM +0200, Krzysztof Kozlowski wrote:
> > 
> >>>>> +     refclk_ccc: cccrefclk {
> >>>>
> >>>> Please use name for all fixed clocks which matches current format
> >>>> recommendation: 'clock-<freq>' (see also the pattern in the binding for
> >>>> any other options).
> >>>>
> >>>> https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml
> >>> The fabric dtsi describes elements configured by the FPGA bitstream. 
> >>> This node is named as such because the Clock Conditioner Circuit CCC's 
> >>> reference clock source is set by the FPGA bitstream, while its frequency 
> >>> is determined by an on-board oscillator.
> >>>
> >>> Hope this clarifies the rationale behind the node name.
> >> No, because there is no style naming clocks like this. Neither proper
> >> suffix, nor prefix. Use standard naming.
> > 
> > So you want all fixed frequency clocks to be named "clk-foo" when
> > "clk-<freq>" is not suitable? Fine if you do, but I didn't realise that
> > it was required and haven't been keeping an eye out for it.
> 
> Recommended is to just use consistent suffixes or prefixes. Binding asks
> for "clock-" so that's what I propose to use here.

Okay, I'll keep that in mind. 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]