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smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TuzhpasJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TuzhpasJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id F1F71C4CEED; Mon, 25 Aug 2025 22:41:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756161669; bh=hcgh5oqMsvEek9C9auiVRt+yT8DF3gRRdz8vIwAO460=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=TuzhpasJSKONwmodl29hxEeu1B+jNP9tEnNDVUu5J+c2hP06IPu8smtAiAy/paA5D nQ7OpGab4minbAOsbjXXcQSkH/TI61SiMOxo7linJiZDbP6Jo2Fh2gtIHiIiZjiP/N mf9A26nzWQ+DOGu7DynGHvPP7N0ZHQU2sT68opCJns/zJBs6HWbEVSHmxXzvpyh5pp xl3cWCdgAOSNlciX9GaNuWSCTfhoxsI0v3bx0ke0VA8L3vRNHy/ALm9wKcVRs/LBDI Jfa0gF4IsoAKqhjqPYzyz0kQSIj32X8rbLnBzfg2E6cmQXIvI3A4c5qKxfv4HGvFMC zijfQ4ECgtsWA== Date: Mon, 25 Aug 2025 17:41:08 -0500 From: Rob Herring To: Michael Riesch Cc: Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , Kever Yang , Jagan Teki , Sebastian Reichel , Diederik de Haas , Neil Armstrong , Collabora Kernel Team , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Subject: Re: [PATCH v2 3/7] dt-bindings: phy: rockchip-inno-csi-dphy: add rk3588 variant Message-ID: <20250825224108.GA766877-robh@kernel.org> References: <20250616-rk3588-csi-dphy-v2-0-7a94f079b712@collabora.com> <20250616-rk3588-csi-dphy-v2-3-7a94f079b712@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250616-rk3588-csi-dphy-v2-3-7a94f079b712@collabora.com> On Tue, Aug 19, 2025 at 01:00:37AM +0200, Michael Riesch wrote: > The Rockchip RK3588 variant of the CSI-2 DPHY features two reset lines. > Add the variant and allow for the additional reset. > > Signed-off-by: Michael Riesch > --- > .../bindings/phy/rockchip-inno-csi-dphy.yaml | 60 ++++++++++++++++++++-- > 1 file changed, 56 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml > index 42da616ae2e3..10197cc9dc47 100644 > --- a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml > +++ b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml > @@ -21,6 +21,7 @@ properties: > - rockchip,rk3326-csi-dphy > - rockchip,rk3368-csi-dphy > - rockchip,rk3568-csi-dphy > + - rockchip,rk3588-csi-dphy > > reg: > maxItems: 1 > @@ -39,18 +40,50 @@ properties: > maxItems: 1 > > resets: > - items: > - - description: exclusive PHY reset line > + minItems: 1 > + maxItems: 2 Add a description for the 2nd reset here. > > reset-names: > - items: > - - const: apb > + minItems: 1 > + maxItems: 2 Add 'phy' to the list here and just minItems. > > rockchip,grf: > $ref: /schemas/types.yaml#/definitions/phandle > description: > Some additional phy settings are access through GRF regs. > > +allOf: > + - if: > + properties: > + compatible: > + contains: > + enum: > + - rockchip,px30-csi-dphy > + - rockchip,rk1808-csi-dphy > + - rockchip,rk3326-csi-dphy > + - rockchip,rk3368-csi-dphy > + - rockchip,rk3568-csi-dphy > + then: > + properties: > + resets: > + items: > + - description: exclusive PHY reset line > + > + reset-names: > + items: > + - const: apb Then just 'maxItems: 1' here. > + else: > + properties: > + resets: > + items: > + - description: APB reset line > + - description: PHY reset line > + > + reset-names: > + items: > + - const: apb > + - const: phy And 'minItems: 2' here. > + > required: > - compatible > - reg > @@ -77,3 +110,22 @@ examples: > reset-names = "apb"; > rockchip,grf = <&grf>; > }; > + - | > + #include > + #include > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + phy@fedc0000 { > + compatible = "rockchip,rk3588-csi-dphy"; > + reg = <0x0 0xfedc0000 0x0 0x8000>; > + clocks = <&cru PCLK_CSIPHY0>; > + clock-names = "pclk"; > + #phy-cells = <0>; > + resets = <&cru SRST_P_CSIPHY0>, <&cru SRST_CSIPHY0>; > + reset-names = "apb", "phy"; > + rockchip,grf = <&csidphy0_grf>; > + }; > + }; > > -- > 2.39.5 >