From: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
To: paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, anup@brainfault.org,
pbonzini@redhat.com, shuah@kernel.org, cyan.yang@sifive.com,
cleger@rivosinc.com, charlie@rivosinc.com,
cuiyunhui@bytedance.com, samuel.holland@sifive.com,
namcao@linutronix.de, jesse@rivosinc.com, inochiama@gmail.com,
yongxuan.wang@sifive.com, ajones@ventanamicro.com,
parri.andrea@gmail.com, mikisabate@gmail.com,
yikming2222@gmail.com, thomas.weissschuh@linutronix.de
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, devicetree@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-kselftest@vger.kernel.org, pincheng.plct@isrc.iscas.ac.cn
Subject: [PATCH v2 0/5] Add Zilsd/Zclsd support in hwprobe and KVM
Date: Wed, 27 Aug 2025 00:29:34 +0800 [thread overview]
Message-ID: <20250826162939.1494021-1-pincheng.plct@isrc.iscas.ac.cn> (raw)
Hi all,
This is v2 of a short series that adds kernel support for the ratified
Zilsd (Load/Store pair) and Zclsd (Compressed Load/Store pair) RISC-V
ISA extensions. The series enables kernel-side exposure so user-space
(for example glibc) can detect and use these extensions via hwprobe and
runtime checks.
Patches:
- Patch 1:Add device tree bindings documentation for Zilsd and Zclsd.
- Patch 2: Extend RISC-V ISA extension string parsing to recognize them.
- Patch 3: Export Zilsd and Zclsd via riscv_hwprobe.
- Patch 4: Allow KVM guests to use them.
- Patch 5: Add KVM selftests.
Changes in v2:
- Device-tree schema: simplified the rv64 validation for Zilsd by
removing a redundant `contais: const: zilsd` in the `if` clause; the
simpler `if (riscv, isa-base contains rv64i) then (riscv,
isa-extension not contains zilsd)` form is used instead. Behaviour is
unchanged, and the logic is cleaner.
- Device-tree schema: corrected Zclsd dependency to require both Zilsd
and Zca (previous `anyOf` was incorrect; now both are enforced).
- Commit message typo fixed: "dt-bidings" -> "dt-bindings" in the Patch
1 commit subject.
The v2 changes are documentation/schema corrections in extensions.yaml.
No functional changes were made to ISA parsing, hwprobe syscall, KVM
guest support or the selftests beyond ensuring the binding correctly
documents and validates the extension relationships.
Please review v2 and advise if futher changes are needed.
Thanks,
Pincheng Wang
Pincheng Wang (5):
dt-bindings: riscv: add Zilsd and Zclsd extension descriptions
riscv: add ISA extension parsing for Zilsd and Zclsd
riscv: hwprobe: export Zilsd and Zclsd ISA extensions
riscv: KVM: allow Zilsd and Zclsd extensions for Guest/VM
KVM: riscv: selftests: add Zilsd and Zclsd extension to get-reg-list
test
Documentation/arch/riscv/hwprobe.rst | 8 +++++
.../devicetree/bindings/riscv/extensions.yaml | 36 +++++++++++++++++++
arch/riscv/include/asm/hwcap.h | 2 ++
arch/riscv/include/uapi/asm/hwprobe.h | 2 ++
arch/riscv/include/uapi/asm/kvm.h | 2 ++
arch/riscv/kernel/cpufeature.c | 24 +++++++++++++
arch/riscv/kernel/sys_hwprobe.c | 2 ++
arch/riscv/kvm/vcpu_onereg.c | 2 ++
.../selftests/kvm/riscv/get-reg-list.c | 6 ++++
9 files changed, 84 insertions(+)
--
2.39.5
next reply other threads:[~2025-08-26 16:30 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-26 16:29 Pincheng Wang [this message]
2025-08-26 16:29 ` [PATCH v2 1/5] dt-bindings: riscv: add Zilsd and Zclsd extension descriptions Pincheng Wang
2025-08-26 17:39 ` Conor Dooley
2025-09-01 8:46 ` Nutty.Liu
2025-08-26 16:29 ` [PATCH v2 2/5] riscv: add ISA extension parsing for Zilsd and Zclsd Pincheng Wang
2025-09-01 8:41 ` Nutty.Liu
2025-08-26 16:29 ` [PATCH v2 3/5] riscv: hwprobe: export Zilsd and Zclsd ISA extensions Pincheng Wang
2025-09-01 8:39 ` Nutty.Liu
2025-08-26 16:29 ` [PATCH v2 4/5] riscv: KVM: allow Zilsd and Zclsd extensions for Guest/VM Pincheng Wang
2025-09-01 8:37 ` Nutty.Liu
2025-08-26 16:29 ` [PATCH v2 5/5] KVM: riscv: selftests: add Zilsd and Zclsd extension to get-reg-list test Pincheng Wang
2025-09-01 8:37 ` Nutty.Liu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250826162939.1494021-1-pincheng.plct@isrc.iscas.ac.cn \
--to=pincheng.plct@isrc.iscas.ac.cn \
--cc=ajones@ventanamicro.com \
--cc=alex@ghiti.fr \
--cc=anup@brainfault.org \
--cc=aou@eecs.berkeley.edu \
--cc=charlie@rivosinc.com \
--cc=cleger@rivosinc.com \
--cc=conor+dt@kernel.org \
--cc=cuiyunhui@bytedance.com \
--cc=cyan.yang@sifive.com \
--cc=devicetree@vger.kernel.org \
--cc=inochiama@gmail.com \
--cc=jesse@rivosinc.com \
--cc=krzk+dt@kernel.org \
--cc=kvm-riscv@lists.infradead.org \
--cc=kvm@vger.kernel.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-kselftest@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=mikisabate@gmail.com \
--cc=namcao@linutronix.de \
--cc=palmer@dabbelt.com \
--cc=parri.andrea@gmail.com \
--cc=paul.walmsley@sifive.com \
--cc=pbonzini@redhat.com \
--cc=robh@kernel.org \
--cc=samuel.holland@sifive.com \
--cc=shuah@kernel.org \
--cc=thomas.weissschuh@linutronix.de \
--cc=yikming2222@gmail.com \
--cc=yongxuan.wang@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).