From: James Clark <james.clark@linaro.org>
To: Frank Li <Frank.Li@nxp.com>, Mark Brown <broonie@kernel.org>,
Clark Wang <xiaoning.wang@nxp.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>,
Larisa Grigore <larisa.grigore@oss.nxp.com>,
Larisa Grigore <larisa.grigore@nxp.com>,
Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>,
Ciprianmarian Costea <ciprianmarian.costea@nxp.com>,
s32@nxp.com
Cc: James Clark <james.clark@linaro.org>,
linux-spi@vger.kernel.org, imx@lists.linux.dev,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: [PATCH v2 3/9] spi: spi-fsl-lpspi: Reset FIFO and disable module on transfer abort
Date: Thu, 28 Aug 2025 11:14:42 +0100 [thread overview]
Message-ID: <20250828-james-nxp-lpspi-v2-3-6262b9aa9be4@linaro.org> (raw)
In-Reply-To: <20250828-james-nxp-lpspi-v2-0-6262b9aa9be4@linaro.org>
From: Larisa Grigore <larisa.grigore@nxp.com>
In DMA mode fsl_lpspi_reset() is always called at the end, even when the
transfer is aborted. In PIO mode aborts skip the reset leaving the FIFO
filled and the module enabled.
Fix it by always calling fsl_lpspi_reset().
Fixes: a15dc3d657fa ("spi: lpspi: Fix CLK pin becomes low before one transfer")
Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: James Clark <james.clark@linaro.org>
---
drivers/spi/spi-fsl-lpspi.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c
index 5ea4a306ffa6..e50261e9a1fa 100644
--- a/drivers/spi/spi-fsl-lpspi.c
+++ b/drivers/spi/spi-fsl-lpspi.c
@@ -733,12 +733,10 @@ static int fsl_lpspi_pio_transfer(struct spi_controller *controller,
fsl_lpspi_write_tx_fifo(fsl_lpspi);
ret = fsl_lpspi_wait_for_completion(controller);
- if (ret)
- return ret;
fsl_lpspi_reset(fsl_lpspi);
- return 0;
+ return ret;
}
static int fsl_lpspi_transfer_one(struct spi_controller *controller,
--
2.34.1
next prev parent reply other threads:[~2025-08-28 10:15 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-28 10:14 [PATCH v2 0/9] spi: spi-fsl-lpspi: Generic fixes and support for S32G devices James Clark
2025-08-28 10:14 ` [PATCH v2 1/9] spi: spi-fsl-lpspi: Fix transmissions when using CONT James Clark
2025-08-29 11:38 ` Mark Brown
2025-08-29 14:27 ` Frank Li
2025-08-28 10:14 ` [PATCH v2 2/9] spi: spi-fsl-lpspi: Set correct chip-select polarity bit James Clark
2025-08-28 18:09 ` Frank Li
2025-08-28 10:14 ` James Clark [this message]
2025-08-28 10:14 ` [PATCH v2 4/9] spi: spi-fsl-lpspi: Clear status register after disabling the module James Clark
2025-08-28 10:14 ` [PATCH v2 5/9] dt-bindings: lpspi: Document support for S32G James Clark
2025-08-28 18:10 ` Frank Li
2025-08-29 17:52 ` Rob Herring (Arm)
2025-08-28 10:14 ` [PATCH v2 6/9] spi: spi-fsl-lpspi: Constify devtype datas James Clark
2025-08-28 18:11 ` Frank Li
2025-08-28 10:14 ` [PATCH v2 7/9] spi: spi-fsl-lpspi: Treat prescale_max == 0 as no erratum James Clark
2025-08-28 18:13 ` Frank Li
2025-08-28 10:14 ` [PATCH v2 8/9] spi: spi-fsl-lpspi: Parameterize reading num-cs from hardware James Clark
2025-08-28 18:14 ` Frank Li
2025-08-28 10:14 ` [PATCH v2 9/9] spi: spi-fsl-lpspi: Add compatible for S32G James Clark
2025-08-28 18:15 ` Frank Li
2025-09-02 9:50 ` [PATCH v2 0/9] spi: spi-fsl-lpspi: Generic fixes and support for S32G devices Mark Brown
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