From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F14B1278E75; Thu, 28 Aug 2025 08:09:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756368555; cv=none; b=NYVOoPt2fgDUkWUF5Vo7Whzp12YF4HD0RAVZKNLa6qwfvB3DqSHJ3+vWCu654G5+kwaQAv3r6miuqEoNX3vRqM6Sp+lpJcwJI4F/lU6+eIftyPYEoxi96S34vaSaMBKwh/U8DraSgqSKb1veb18s84Z/+PFC0bmn81jIwFJ/qaA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756368555; c=relaxed/simple; bh=zOW77bx1YdP/YekmqZQlBOsH7uvOU04dLNBtWrgaO68=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tkrLBZzJXdMef/D3XY0Qzc6Zw4uNTWtvS4CSy+JTWDq2KZqCNjiH/4S1BmIB05+xYDoj7zgvm6KPo0CzwGvKEOhHYC/Y8GPvLLSeGDCxmuhtZR9qcVISMF6352sXf8gChUqLHXRM7RllH8O8MERECR/9O3ne2abHt4lPo+K+JmI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=YNLED9lS; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="YNLED9lS" X-UUID: 44cce6d883e611f0bd5779446731db89-20250828 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=oTlz1MCKcn4rGSR6/2ktyt718NOXEmqe77kiQs2rCno=; b=YNLED9lSEtvsHCqsEsXXkRo4ZqzX3Wcf1E83/01RNv+ewvRIvx/8/IqBhKXeSb78DzmBlw0/Kq2v7GZUA9Oa1woBtz84ewgguOlU1nnczD2tGwpqXs0cX+ZfMUETzAU5pZPn4QqIBhO676Ttpb2FFLkKi1E812j/3NEAmJIIMyk=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.3,REQID:7c1a6fb4-4cee-402d-a947-a4ce43dddd82,IP:0,UR L:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:-5 X-CID-META: VersionHash:f1326cf,CLOUDID:1a719d7a-966c-41bd-96b5-7d0b3c22e782,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:-5,Content:0|15|50,EDM: -3,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0, AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 44cce6d883e611f0bd5779446731db89-20250828 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1247059330; Thu, 28 Aug 2025 16:09:06 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Thu, 28 Aug 2025 16:09:05 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Thu, 28 Aug 2025 16:09:05 +0800 From: Paul Chen To: , , , , CC: , , , , , , , , , , , , , , , , Subject: [PATCH v4 16/19] drm/mediatek: add OUTPROC support for MT8196 Date: Thu, 28 Aug 2025 16:07:11 +0800 Message-ID: <20250828080855.3502514-17-paul-pl.chen@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250828080855.3502514-1-paul-pl.chen@mediatek.com> References: <20250828080855.3502514-1-paul-pl.chen@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain From: Nancy Lin OUTPROC handles the post-stage of pixel processing in the overlapping procedure.OUTPROC manages pixels for gamma correction and ensures that pixel values are within the correct range. Signed-off-by: Nancy Lin Signed-off-by: Paul-pl Chen --- drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 1 + drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_disp_drv.h | 14 ++ drivers/gpu/drm/mediatek/mtk_disp_outproc.c | 235 ++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_outproc.h | 22 ++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + 8 files changed, 276 insertions(+) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_outproc.c create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_outproc.h diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index 8d18d5583903..7bc02a7f178c 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -10,6 +10,7 @@ mediatek-drm-y := mtk_crtc.o \ mtk_disp_gamma.o \ mtk_disp_merge.o \ mtk_disp_ovl.o \ + mtk_disp_outproc.o \ mtk_disp_ovl_adaptor.o \ mtk_disp_rdma.o \ mtk_drm_drv.o \ diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c index 2e45580f25ea..f3e8645c35b6 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -448,6 +448,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { [MTK_DSI] = "dsi", [MTK_OVL_BLENDER] = "blender", [MTK_OVL_EXDMA] = "exdma", + [MTK_OVL_OUTPROC] = "outproc", }; struct mtk_ddp_comp_match { diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h index 290190d366af..7f9facb5574b 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h @@ -45,6 +45,7 @@ enum mtk_ddp_comp_type { MTK_DSI, MTK_OVL_BLENDER, MTK_OVL_EXDMA, + MTK_OVL_OUTPROC, MTK_DDP_COMP_TYPE_MAX, }; diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index e0aeb87f0a5b..cecee77a8590 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -63,6 +63,20 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg, unsigned int bpc, unsigned int cfg, unsigned int dither_en, struct cmdq_pkt *cmdq_pkt); +void mtk_disp_outproc_start(struct device *dev); +void mtk_disp_outproc_stop(struct device *dev); +int mtk_disp_outproc_clk_enable(struct device *dev); +void mtk_disp_outproc_clk_disable(struct device *dev); +void mtk_disp_outproc_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +void mtk_disp_outproc_register_vblank_cb(struct device *dev, + void (*vblank_cb)(void *), + void *vblank_cb_data); +void mtk_disp_outproc_unregister_vblank_cb(struct device *dev); +void mtk_disp_outproc_enable_vblank(struct device *dev); +void mtk_disp_outproc_disable_vblank(struct device *dev); + void mtk_dpi_start(struct device *dev); void mtk_dpi_stop(struct device *dev); unsigned int mtk_dpi_encoder_index(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_outproc.c b/drivers/gpu/drm/mediatek/mtk_disp_outproc.c new file mode 100644 index 000000000000..99f0d60c3574 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_disp_outproc.c @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mtk_crtc.h" +#include "mtk_ddp_comp.h" +#include "mtk_disp_outproc.h" +#include "mtk_drm_drv.h" + +#define DISP_REG_OVL_OUTPROC_INTEN 0x004 +#define OVL_OUTPROC_FME_CPL_INTEN BIT(1) +#define DISP_REG_OVL_OUTPROC_INTSTA 0x008 +#define DISP_REG_OVL_OUTPROC_DATAPATH_CON 0x010 +#define OVL_OUTPROC_DATAPATH_CON_OUTPUT_CLAMP BIT(26) + +#define DISP_REG_OVL_OUTPROC_EN 0x020 +#define OVL_OUTPROC_OVL_EN BIT(0) +#define DISP_REG_OVL_OUTPROC_RST 0x024 +#define OVL_OUTPROC_RST BIT(0) +#define DISP_REG_OVL_OUTPROC_SHADOW_CTRL 0x028 +#define OVL_OUTPROC_BYPASS_SHADOW BIT(2) +#define DISP_REG_OVL_OUTPROC_ROI_SIZE 0x030 + +struct mtk_disp_outproc { + void __iomem *regs; + struct clk *clk; + void (*vblank_cb)(void *data); + void *vblank_cb_data; + int irq; + struct cmdq_client_reg cmdq_reg; +}; + +void mtk_disp_outproc_register_vblank_cb(struct device *dev, + void (*vblank_cb)(void *), + void *vblank_cb_data) +{ + struct mtk_disp_outproc *priv = dev_get_drvdata(dev); + + priv->vblank_cb = vblank_cb; + priv->vblank_cb_data = vblank_cb_data; +} + +void mtk_disp_outproc_unregister_vblank_cb(struct device *dev) +{ + struct mtk_disp_outproc *priv = dev_get_drvdata(dev); + + priv->vblank_cb = NULL; + priv->vblank_cb_data = NULL; +} + +void mtk_disp_outproc_enable_vblank(struct device *dev) +{ + struct mtk_disp_outproc *priv = dev_get_drvdata(dev); + + writel(0x0, priv->regs + DISP_REG_OVL_OUTPROC_INTSTA); + writel(OVL_OUTPROC_FME_CPL_INTEN, priv->regs + DISP_REG_OVL_OUTPROC_INTEN); +} + +void mtk_disp_outproc_disable_vblank(struct device *dev) +{ + struct mtk_disp_outproc *priv = dev_get_drvdata(dev); + + writel(0x0, priv->regs + DISP_REG_OVL_OUTPROC_INTEN); +} + +static irqreturn_t mtk_disp_outproc_irq_handler(int irq, void *dev_id) +{ + struct mtk_disp_outproc *priv = dev_id; + u32 val; + + val = readl(priv->regs + DISP_REG_OVL_OUTPROC_INTSTA); + if (!val) + return IRQ_NONE; + + writel(0x0, priv->regs + DISP_REG_OVL_OUTPROC_INTSTA); + + if (priv->vblank_cb) + priv->vblank_cb(priv->vblank_cb_data); + + return IRQ_HANDLED; +} + +void mtk_disp_outproc_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_disp_outproc *priv = dev_get_drvdata(dev); + u32 tmp = 0; + + dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h); + + writel((h << 16) | w, priv->regs + DISP_REG_OVL_OUTPROC_ROI_SIZE); + + tmp |= OVL_OUTPROC_DATAPATH_CON_OUTPUT_CLAMP; + writel(tmp, priv->regs + DISP_REG_OVL_OUTPROC_DATAPATH_CON); +} + +void mtk_disp_outproc_start(struct device *dev) +{ + struct mtk_disp_outproc *priv = dev_get_drvdata(dev); + unsigned int tmp = 0; + + tmp = readl(priv->regs + DISP_REG_OVL_OUTPROC_SHADOW_CTRL); + tmp |= OVL_OUTPROC_BYPASS_SHADOW; + writel(tmp, priv->regs + DISP_REG_OVL_OUTPROC_SHADOW_CTRL); + + writel(OVL_OUTPROC_OVL_EN, priv->regs + DISP_REG_OVL_OUTPROC_EN); +} + +void mtk_disp_outproc_stop(struct device *dev) +{ + struct mtk_disp_outproc *priv = dev_get_drvdata(dev); + + writel(0, priv->regs + DISP_REG_OVL_OUTPROC_EN); + writel(OVL_OUTPROC_RST, priv->regs + DISP_REG_OVL_OUTPROC_RST); + writel(0, priv->regs + DISP_REG_OVL_OUTPROC_RST); +} + +int mtk_disp_outproc_clk_enable(struct device *dev) +{ + struct mtk_disp_outproc *priv = dev_get_drvdata(dev); + + return clk_prepare_enable(priv->clk); +} + +void mtk_disp_outproc_clk_disable(struct device *dev) +{ + struct mtk_disp_outproc *priv = dev_get_drvdata(dev); + + clk_disable_unprepare(priv->clk); +} + +static int mtk_disp_outproc_bind(struct device *dev, struct device *master, + void *data) +{ + return 0; +} + +static void mtk_disp_outproc_unbind(struct device *dev, struct device *master, void *data) +{ +} + +static const struct component_ops mtk_disp_outproc_component_ops = { + .bind = mtk_disp_outproc_bind, + .unbind = mtk_disp_outproc_unbind, +}; + +static int mtk_disp_outproc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mtk_disp_outproc *priv; + int ret = 0; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->regs)) + return dev_err_probe(dev, PTR_ERR(priv->regs), "failed to ioremap outproc\n"); + + priv->clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) + return dev_err_probe(dev, PTR_ERR(priv->clk), "failed to get outproc clk\n"); + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); + if (ret) + dev_dbg(dev, "No mediatek,gce-client-reg\n"); +#endif + + if (of_property_read_u32_index(dev->of_node, "interrupts", 0, &ret)) { + dev_dbg(dev, "interrupts not defined\n"); + } else { + priv->irq = platform_get_irq(pdev, 0); + if (priv->irq < 0) + priv->irq = 0; + + if (priv->irq) { + ret = devm_request_irq(dev, priv->irq, mtk_disp_outproc_irq_handler, + IRQF_TRIGGER_NONE, dev_name(dev), priv); + if (ret < 0) { + dev_err(dev, "Failed to request irq %d: %d\n", priv->irq, ret); + return ret; + } + } + } + + platform_set_drvdata(pdev, priv); + + ret = component_add(dev, &mtk_disp_outproc_component_ops); + if (ret) + return dev_err_probe(dev, ret, "Failed to add component\n"); + + return ret; +} + +static void mtk_disp_outproc_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &mtk_disp_outproc_component_ops); +} + +static const struct of_device_id mtk_disp_outproc_driver_dt_match[] = { + { .compatible = "mediatek,mt8196-outproc"}, + {}, +}; + +MODULE_DEVICE_TABLE(of, mtk_disp_outproc_driver_dt_match); + +struct platform_driver mtk_disp_outproc_driver = { + .probe = mtk_disp_outproc_probe, + .remove = mtk_disp_outproc_remove, + .driver = { + .name = "mediatek-disp-outproc", + .owner = THIS_MODULE, + .of_match_table = mtk_disp_outproc_driver_dt_match, + }, +}; + +MODULE_AUTHOR("Nancy Lin "); +MODULE_DESCRIPTION("MediaTek Output processing Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_outproc.h b/drivers/gpu/drm/mediatek/mtk_disp_outproc.h new file mode 100644 index 000000000000..abb101979521 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_disp_outproc.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2025 MediaTek Inc. + */ + +#ifndef __MTK_DISP_OUTPROC_H__ +#define __MTK_DISP_OUTPROC_H__ + +void mtk_disp_outproc_start(struct device *dev); +void mtk_disp_outproc_stop(struct device *dev); +int mtk_disp_outproc_clk_enable(struct device *dev); +void mtk_disp_outproc_clk_disable(struct device *dev); +void mtk_disp_outproc_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +void mtk_disp_outproc_register_vblank_cb(struct device *dev, + void (*vblank_cb)(void *), + void *vblank_cb_data); +void mtk_disp_outproc_unregister_vblank_cb(struct device *dev); +void mtk_disp_outproc_enable_vblank(struct device *dev); +void mtk_disp_outproc_disable_vblank(struct device *dev); +#endif diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index f28146164431..cf5f9b8fc335 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -1294,6 +1294,7 @@ static struct platform_driver * const mtk_drm_drivers[] = { &mtk_disp_exdma_driver, &mtk_disp_gamma_driver, &mtk_disp_merge_driver, + &mtk_disp_outproc_driver, &mtk_disp_ovl_adaptor_driver, &mtk_disp_ovl_driver, &mtk_disp_rdma_driver, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index 89178de1478f..c4717c37b0f1 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -76,6 +76,7 @@ extern struct platform_driver mtk_disp_color_driver; extern struct platform_driver mtk_disp_exdma_driver; extern struct platform_driver mtk_disp_gamma_driver; extern struct platform_driver mtk_disp_merge_driver; +extern struct platform_driver mtk_disp_outproc_driver; extern struct platform_driver mtk_disp_ovl_adaptor_driver; extern struct platform_driver mtk_disp_ovl_driver; extern struct platform_driver mtk_disp_rdma_driver; -- 2.45.2