From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 238522D29B7; Thu, 28 Aug 2025 08:09:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756368556; cv=none; b=YumdAuy6FluoEbrS5Wn8UbDeX1gIyUWL5Ffi6fqvYEpaDTtVwTATh8p3A8vS/4ORvSVUXCxYosP/9sXWXRkUx5tD13+vWVOaTQIcz+FXo65fi5LWiQZqqZU/Kg31eklgwpp1Q7L+1yL6MDMRDZ2AWPHJvha6evuE1gYhvr5aevU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756368556; c=relaxed/simple; bh=XWVTIKDc4TcCHDaBoRTkBM+3y81U+P+OUaJ7GKtG9r0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=g7S2ZL53efyJ2gU3jNweqssDJ5RN491LJhz7kVzha4L4X5jP3aUCXKVa6iv3eKRuSuoioiZQYLH6ycQJe07Gv8Bfsc2TPqji2OM0QPmFnyoSsgyUUE/v2SgtW/ERbtYWSH8HrXHo/Mh1DPNFJ7vXVBEhzY3telto6dgKgPx93So= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=qFrT+7bx; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="qFrT+7bx" X-UUID: 43f0f92083e611f0b33aeb1e7f16c2b6-20250828 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=WJbMyGLRiJ6uq2rVn/fNg8udNWgiGmcvMhmhFr/g19Y=; b=qFrT+7bxxsuBoBXIY2gcTKgMs3TbcvggxzNjkykRHz8snqoGVRAgSDytMD2UT4bk73AF4UPnmR8Y7khT68S1ejlxKxdmc9fiu1ZV+sJhAEBRPZpm+DmxFTQzE/roso7IymT7849rM188b0lGauChcDf/7tVrXmhH6fKCYOE5qZ4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.3,REQID:82700ead-0d8a-4a62-a273-fbf7320cd5bb,IP:0,UR L:25,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:0 X-CID-META: VersionHash:f1326cf,CLOUDID:04719d7a-966c-41bd-96b5-7d0b3c22e782,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:-5,Content:0|15|50,EDM: -3,IP:nil,URL:11|97|99|83|106|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,CO L:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 43f0f92083e611f0b33aeb1e7f16c2b6-20250828 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 871743561; Thu, 28 Aug 2025 16:09:05 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Thu, 28 Aug 2025 16:09:03 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Thu, 28 Aug 2025 16:09:03 +0800 From: Paul Chen To: , , , , CC: , , , , , , , , , , , , , , , , Subject: [PATCH v4 03/19] dt-bindings: display: mediatek: add EXDMA yaml for MT8196 Date: Thu, 28 Aug 2025 16:06:58 +0800 Message-ID: <20250828080855.3502514-4-paul-pl.chen@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250828080855.3502514-1-paul-pl.chen@mediatek.com> References: <20250828080855.3502514-1-paul-pl.chen@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain From: Paul-pl Chen Add mediatek,exdma.yaml to support EXDMA for MT8196. The MediaTek display overlap extended DMA engine, namely OVL_EXDMA or EXDMA, primarily functions as a DMA engine for reading data from DRAM with various DRAM footprints and data formats. Signed-off-by: Paul-pl Chen --- .../bindings/dma/mediatek,exdma.yaml | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/mediatek,exdma.yaml diff --git a/Documentation/devicetree/bindings/dma/mediatek,exdma.yaml b/Documentation/devicetree/bindings/dma/mediatek,exdma.yaml new file mode 100644 index 000000000000..eabf0cfc839e --- /dev/null +++ b/Documentation/devicetree/bindings/dma/mediatek,exdma.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/mediatek,exdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek display overlap extended DMA engine + +maintainers: + - Chun-Kuang Hu + - Philipp Zabel + +description: + The MediaTek display overlap extended DMA engine, namely OVL_EXDMA or EXDMA, + primarily functions as a DMA engine for reading data from DRAM with various + DRAM footprints and data formats. For input sources in certain color formats + and color domains, OVL_EXDMA also includes a color transfer function + to process pixels into a consistent color domain. + +properties: + compatible: + const: mediatek,mt8196-exdma + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + mediatek,larb: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + A phandle to the local arbiters node in the current SoCs. + Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. + + iommus: + maxItems: 1 + + '#dma-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - power-domains + - mediatek,larb + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + exdma: dma-controller@32850000 { + compatible = "mediatek,mt8196-exdma"; + reg = <0 0x32850000 0 0x1000>; + clocks = <&ovlsys_config_clk 13>; + power-domains = <&hfrpsys 12>; + iommus = <&mm_smmu 144>; + #dma-cells = <1>; + }; + }; -- 2.45.2