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Sat, 30 Aug 2025 09:28:40 -0700 (PDT) Received: from [127.0.0.1] ([74.249.85.195]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70fb28b5a26sm8110786d6.64.2025.08.30.09.28.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Aug 2025 09:28:40 -0700 (PDT) From: Denzeel Oliva Subject: [PATCH v5 0/5] clk: samsung: exynos990: CMU_TOP fixes (mux regs, widths, factors) Date: Sat, 30 Aug 2025 16:28:37 +0000 Message-Id: <20250830-fix-cmu-top-v5-0-7c62f608309e@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIALUms2gC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyTHUUlJIzE vPSU3UzU4B8JSMDI1MDC2MD3bTMCt3k3FLdkvwCXQNLQ/PERAsTC3PDJCWgjoKiVKA02LTo2Np aAIZGO1pdAAAA X-Change-ID: 20250830-fix-cmu-top-0917aa84871b To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Denzeel Oliva X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756571319; l=1607; i=wachiturroxd150@gmail.com; s=20250830; h=from:subject:message-id; bh=DTu6htZoqYuzhaeQFD9mKEvbhzis4l6Wheni3yeZONY=; b=TLrfWOSA0lvmaSNnT+NdMXez4B1AptncW54LbNAkWa5w+d2JzK+N+1IQ+yAVMSNO25fxPCFEy UBnQgmyzbFwA4LaOd57KjANj/h0Y/WEc/z/cFH4T5EBqdNC4JeVz7MX X-Developer-Key: i=wachiturroxd150@gmail.com; a=ed25519; pk=rxHEBGA1eos5vQkPC9SlkEPD6sil9F03N6bc8qmUFrQ= Hi, Two small fixes for Exynos990 CMU_TOP: Correct PLL mux register selection (use PLL_CON0), add DPU_BUS and CMUREF mux/div, and update clock IDs. Fix mux/div bit widths and replace a few bogus divs with fixed-factor clocks (HSI1/2 PCIe, USBDP debug); also fix OTP rate. Changes in v2: - In the first commit the divratio of PLL_SHARED0_DIV3 should not be changed. Changes in v3: - There is no ABI massive break, the new ID clocks are in the last define CMU_TOP block. Changes in v4: - Fix compilation for define CLK_DOUT_CMU_CMUREF to CLK_DOUT_CMU_CLK_CMUREF Changes in v5: - Rewrite commits and remove cosmetic/non-operational changes and unrelated rebases. CLKS_NR_TOP will be moved to the patch that adds the new clocks. Please review. Denzeel Oliva Signed-off-by: Denzeel Oliva --- Denzeel Oliva (5): clk: samsung: exynos990: Use PLL_CON0 for PLL parent muxes clk: samsung: exynos990: Fix CMU_TOP mux/div bit widths clk: samsung: exynos990: Replace bogus divs with fixed-factor clocks dt-bindings: clock: exynos990: Extend clocks IDs clk: samsung: exynos990: Add DPU_BUS and CMUREF mux/div and update CLKS_NR_TOP drivers/clk/samsung/clk-exynos990.c | 80 ++++++++++++++++++++------- include/dt-bindings/clock/samsung,exynos990.h | 4 ++ 2 files changed, 63 insertions(+), 21 deletions(-) --- base-commit: 39f90c1967215375f7d87b81d14b0f3ed6b40c29 change-id: 20250830-fix-cmu-top-0917aa84871b Best regards, -- Denzeel Oliva