From: Xu Lu <luxu.kernel@bytedance.com>
To: paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
apw@canonical.com, joe@perches.com,
Xu Lu <luxu.kernel@bytedance.com>
Subject: [PATCH RESEND 2/2] riscv: mm: Clear cpu in mm_cpumask after local_flush_tlb_all_asid
Date: Mon, 1 Sep 2025 19:41:41 +0800 [thread overview]
Message-ID: <20250901114141.5438-3-luxu.kernel@bytedance.com> (raw)
In-Reply-To: <20250901114141.5438-1-luxu.kernel@bytedance.com>
Clear corresponding bit of current cpu in mm_cpumask after executing
local_flush_tlb_all_asid().
This reduces the number of IPI due to tlb flush:
* ltp - mmapstress01
Before: ~98k
After: 268
Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
---
arch/riscv/mm/tlbflush.c | 41 ++++++++++++++++++++++++----------------
1 file changed, 25 insertions(+), 16 deletions(-)
diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
index 962db300a1665..571358f385879 100644
--- a/arch/riscv/mm/tlbflush.c
+++ b/arch/riscv/mm/tlbflush.c
@@ -17,7 +17,8 @@
*/
unsigned long tlb_flush_all_threshold __read_mostly = 64;
-static void local_flush_tlb_range_threshold_asid(unsigned long start,
+static void local_flush_tlb_range_threshold_asid(struct mm_struct *mm,
+ unsigned long start,
unsigned long size,
unsigned long stride,
unsigned long asid)
@@ -27,6 +28,8 @@ static void local_flush_tlb_range_threshold_asid(unsigned long start,
if (nr_ptes_in_range > tlb_flush_all_threshold) {
local_flush_tlb_all_asid(asid);
+ if (mm && mm != current->active_mm)
+ cpumask_clear_cpu(raw_smp_processor_id(), mm_cpumask(mm));
return;
}
@@ -46,21 +49,28 @@ static void local_flush_tlb_range_threshold_asid(unsigned long start,
}
}
-static inline void local_flush_tlb_range_asid(unsigned long start,
- unsigned long size, unsigned long stride, unsigned long asid)
+static inline void local_flush_tlb_range_mm(struct mm_struct *mm,
+ unsigned long start,
+ unsigned long size,
+ unsigned long stride)
{
- if (size <= stride)
+ unsigned long asid = get_mm_asid(mm);
+
+ if (size <= stride) {
local_flush_tlb_page_asid(start, asid);
- else if (size == FLUSH_TLB_MAX_SIZE)
+ } else if (size == FLUSH_TLB_MAX_SIZE) {
local_flush_tlb_all_asid(asid);
- else
- local_flush_tlb_range_threshold_asid(start, size, stride, asid);
+ if (mm && mm != current->active_mm)
+ cpumask_clear_cpu(raw_smp_processor_id(), mm_cpumask(mm));
+ } else {
+ local_flush_tlb_range_threshold_asid(mm, start, size, stride, asid);
+ }
}
/* Flush a range of kernel pages without broadcasting */
void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
{
- local_flush_tlb_range_asid(start, end - start, PAGE_SIZE, FLUSH_TLB_NO_ASID);
+ local_flush_tlb_range_mm(NULL, start, end - start, PAGE_SIZE);
}
static void __ipi_flush_tlb_all(void *info)
@@ -79,17 +89,17 @@ void flush_tlb_all(void)
}
struct flush_tlb_range_data {
- unsigned long asid;
+ struct mm_struct *mm;
unsigned long start;
unsigned long size;
unsigned long stride;
};
-static void __ipi_flush_tlb_range_asid(void *info)
+static void __ipi_flush_tlb_range_mm(void *info)
{
struct flush_tlb_range_data *d = info;
- local_flush_tlb_range_asid(d->start, d->size, d->stride, d->asid);
+ local_flush_tlb_range_mm(d->mm, d->start, d->size, d->stride);
}
static void __flush_tlb_range(struct mm_struct *mm,
@@ -97,7 +107,6 @@ static void __flush_tlb_range(struct mm_struct *mm,
unsigned long start, unsigned long size,
unsigned long stride)
{
- unsigned long asid = get_mm_asid(mm);
unsigned int cpu;
if (cpumask_empty(cmask))
@@ -107,17 +116,17 @@ static void __flush_tlb_range(struct mm_struct *mm,
/* Check if the TLB flush needs to be sent to other CPUs. */
if (cpumask_any_but(cmask, cpu) >= nr_cpu_ids) {
- local_flush_tlb_range_asid(start, size, stride, asid);
+ local_flush_tlb_range_mm(mm, start, size, stride);
} else if (riscv_use_sbi_for_rfence()) {
- sbi_remote_sfence_vma_asid(cmask, start, size, asid);
+ sbi_remote_sfence_vma_asid(cmask, start, size, get_mm_asid(mm));
} else {
struct flush_tlb_range_data ftd;
- ftd.asid = asid;
+ ftd.mm = mm;
ftd.start = start;
ftd.size = size;
ftd.stride = stride;
- on_each_cpu_mask(cmask, __ipi_flush_tlb_range_asid, &ftd, 1);
+ on_each_cpu_mask(cmask, __ipi_flush_tlb_range_mm, &ftd, 1);
}
put_cpu();
--
2.20.1
prev parent reply other threads:[~2025-09-01 11:41 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-01 11:41 [PATCH RESEND 0/2] riscv: mm: Some optimizations for tlb flush Xu Lu
2025-09-01 11:41 ` [PATCH RESEND 1/2] riscv: mm: Apply svinval in update_mmu_cache() Xu Lu
2026-07-11 0:04 ` Paul Walmsley
2026-07-13 6:29 ` [External] " Xu Lu
2026-07-11 0:07 ` Paul Walmsley
2025-09-01 11:41 ` Xu Lu [this message]
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