From: Xu Lu <luxu.kernel@bytedance.com>
To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr, ajones@ventanamicro.com,
brs@rivosinc.com
Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, apw@canonical.com, joe@perches.com,
Xu Lu <luxu.kernel@bytedance.com>
Subject: [PATCH v2 4/4] riscv: Use Zalasr for smp_load_acquire/smp_store_release
Date: Tue, 2 Sep 2025 12:24:32 +0800 [thread overview]
Message-ID: <20250902042432.78960-5-luxu.kernel@bytedance.com> (raw)
In-Reply-To: <20250902042432.78960-1-luxu.kernel@bytedance.com>
Replace fence instructions with Zalasr instructions during acquire or
release operations.
Signed-off-by: Xu Lu <luxu.kernel@bytedance.com>
---
arch/riscv/include/asm/barrier.h | 79 +++++++++++++++++++++++++++-----
1 file changed, 68 insertions(+), 11 deletions(-)
diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h
index b8c5726d86acb..b1d2a9a85256d 100644
--- a/arch/riscv/include/asm/barrier.h
+++ b/arch/riscv/include/asm/barrier.h
@@ -51,19 +51,76 @@
*/
#define smp_mb__after_spinlock() RISCV_FENCE(iorw, iorw)
-#define __smp_store_release(p, v) \
-do { \
- compiletime_assert_atomic_type(*p); \
- RISCV_FENCE(rw, w); \
- WRITE_ONCE(*p, v); \
+extern void __bad_size_call_parameter(void);
+
+#define __smp_store_release(p, v) \
+do { \
+ compiletime_assert_atomic_type(*p); \
+ switch (sizeof(*p)) { \
+ case 1: \
+ asm volatile(ALTERNATIVE("fence rw, w;\t\nsb %0, 0(%1)\t\n", \
+ SB_RL(%0, %1) "\t\nnop\t\n", \
+ 0, RISCV_ISA_EXT_ZALASR, 1) \
+ : : "r" (v), "r" (p) : "memory"); \
+ break; \
+ case 2: \
+ asm volatile(ALTERNATIVE("fence rw, w;\t\nsh %0, 0(%1)\t\n", \
+ SH_RL(%0, %1) "\t\nnop\t\n", \
+ 0, RISCV_ISA_EXT_ZALASR, 1) \
+ : : "r" (v), "r" (p) : "memory"); \
+ break; \
+ case 4: \
+ asm volatile(ALTERNATIVE("fence rw, w;\t\nsw %0, 0(%1)\t\n", \
+ SW_RL(%0, %1) "\t\nnop\t\n", \
+ 0, RISCV_ISA_EXT_ZALASR, 1) \
+ : : "r" (v), "r" (p) : "memory"); \
+ break; \
+ case 8: \
+ asm volatile(ALTERNATIVE("fence rw, w;\t\nsd %0, 0(%1)\t\n", \
+ SD_RL(%0, %1) "\t\nnop\t\n", \
+ 0, RISCV_ISA_EXT_ZALASR, 1) \
+ : : "r" (v), "r" (p) : "memory"); \
+ break; \
+ default: \
+ __bad_size_call_parameter(); \
+ break; \
+ } \
} while (0)
-#define __smp_load_acquire(p) \
-({ \
- typeof(*p) ___p1 = READ_ONCE(*p); \
- compiletime_assert_atomic_type(*p); \
- RISCV_FENCE(r, rw); \
- ___p1; \
+#define __smp_load_acquire(p) \
+({ \
+ TYPEOF_UNQUAL(*p) val; \
+ compiletime_assert_atomic_type(*p); \
+ switch (sizeof(*p)) { \
+ case 1: \
+ asm volatile(ALTERNATIVE("lb %0, 0(%1)\t\nfence r, rw\t\n", \
+ LB_AQ(%0, %1) "\t\nnop\t\n", \
+ 0, RISCV_ISA_EXT_ZALASR, 1) \
+ : "=r" (val) : "r" (p) : "memory"); \
+ break; \
+ case 2: \
+ asm volatile(ALTERNATIVE("lh %0, 0(%1)\t\nfence r, rw\t\n", \
+ LH_AQ(%0, %1) "\t\nnop\t\n", \
+ 0, RISCV_ISA_EXT_ZALASR, 1) \
+ : "=r" (val) : "r" (p) : "memory"); \
+ break; \
+ case 4: \
+ asm volatile(ALTERNATIVE("lw %0, 0(%1)\t\nfence r, rw\t\n", \
+ LW_AQ(%0, %1) "\t\nnop\t\n", \
+ 0, RISCV_ISA_EXT_ZALASR, 1) \
+ : "=r" (val) : "r" (p) : "memory"); \
+ break; \
+ case 8: \
+ asm volatile(ALTERNATIVE("ld %0, 0(%1)\t\nfence r, rw\t\n", \
+ LD_AQ(%0, %1) "\t\nnop\t\n", \
+ 0, RISCV_ISA_EXT_ZALASR, 1) \
+ : "=r" (val) : "r" (p) : "memory"); \
+ break; \
+ default: \
+ __bad_size_call_parameter(); \
+ break; \
+ } \
+ val; \
})
#ifdef CONFIG_RISCV_ISA_ZAWRS
--
2.20.1
next prev parent reply other threads:[~2025-09-02 4:25 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-02 4:24 [PATCH v2 0/4] riscv: Add Zalasr ISA extension support Xu Lu
2025-09-02 4:24 ` [PATCH v2 1/4] riscv: add ISA extension parsing for Zalasr Xu Lu
2025-09-02 4:24 ` [PATCH v2 2/4] dt-bindings: riscv: Add Zalasr ISA extension description Xu Lu
2025-09-02 19:46 ` Conor Dooley
2025-09-02 4:24 ` [PATCH v2 3/4] riscv: Instroduce Zalasr instructions Xu Lu
2025-09-02 4:24 ` Xu Lu [this message]
2025-09-03 1:06 ` [PATCH v2 4/4] riscv: Use Zalasr for smp_load_acquire/smp_store_release kernel test robot
2025-09-02 16:59 ` [PATCH v2 0/4] riscv: Add Zalasr ISA extension support Andrea Parri
2025-09-03 11:41 ` [External] " Xu Lu
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