* [PATCH v5 0/3] Add SDM660 LPASS LPI TLMM
@ 2025-09-03 13:39 Nickolay Goppen
2025-09-03 13:39 ` [PATCH v5 1/3] pinctrl: qcom: lpass-lpi: Add ability to use custom pin offsets Nickolay Goppen
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Nickolay Goppen @ 2025-09-03 13:39 UTC (permalink / raw)
To: Bjorn Andersson, Linus Walleij, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Nickolay Goppen
Cc: linux-arm-msm, linux-gpio, linux-kernel, devicetree,
~postmarketos/upstreaming, linux, Nickolay Goppen, Richard Acayan
This patch series adds SDM660 LPASS LPI TLMM pinctrl driver and
introduces pin_offset field for LPI pinctrl drivers to support
SDM660's quirky pin_offsets taken from an array with
predefined offsets from downstream [1].
[1] https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/LA.UM.7.2.c27-07400-sdm660.0/drivers/pinctrl/qcom/pinctrl-lpi.c#L107
Signed-off-by: Nickolay Goppen <setotau@yandex.ru>
---
Changes in v5:
- As suggested by Konrad Dybcio Renamed pdm_2_gpios to pdm_tx, dmic12 and dmic34 to dmic1_[clk, data] and dmic2_[clk, data].
- As suggested by Krzysztof Kozlowski Added pinmux nodes to dt-binding example.
- Link to v4: https://lore.kernel.org/r/20250828-sdm660-lpass-lpi-v4-0-af4afdd52965@yandex.ru
Changes in v4:
- Replaced pin_offset callback with a pin_offset field in lpi_pingroup struct.
- Introduced LPI_PINGROUP_OFFSET macro with additional pin_offset field handling.
- Introduced LPI_FLAG_USE_PREDEFINED_PIN_OFFSET flag for indicating use of predefined pin_offsets.
- Replaced an array with offsets in SDM660 LPASS LPI TLMM driver with pin_offset defined for each pin in the new pin_offset field.
- Link to v3: https://lore.kernel.org/r/20250825-sdm660-lpass-lpi-v3-0-65d4a4db298e@yandex.ru
Changes in v3:
- Fixed compilation of LPI drivers as modules by changing pin_offset function determination logic.
- Link to v2: https://lore.kernel.org/r/20250825-sdm660-lpass-lpi-v2-0-af7739f5c27e@yandex.ru
Changes in v2:
- Extended description of "pinctrl: qcom: Add SDM660 LPASS LPI TLMM" patch.
- Resent using b4 relay
- Link to v1: https://lore.kernel.org/r/20250824-sdm660-lpass-lpi-v1-0-003d5cc28234@yandex.ru
---
Nickolay Goppen (2):
pinctrl: qcom: lpass-lpi: Add ability to use custom pin offsets
dt-bindings: pinctrl: qcom: Add SDM660 LPI pinctrl
Richard Acayan (1):
pinctrl: qcom: Add SDM660 LPASS LPI TLMM
.../pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml | 109 ++++++++++++++
drivers/pinctrl/qcom/Kconfig | 10 ++
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 18 ++-
drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 18 +++
drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c | 161 +++++++++++++++++++++
6 files changed, 315 insertions(+), 2 deletions(-)
---
base-commit: ef67c54a170cee962b09c638514d55790b68bdf5
change-id: 20250824-sdm660-lpass-lpi-a8b02a23861a
Best regards,
--
Nickolay Goppen <setotau@mainlining.org>
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v5 1/3] pinctrl: qcom: lpass-lpi: Add ability to use custom pin offsets 2025-09-03 13:39 [PATCH v5 0/3] Add SDM660 LPASS LPI TLMM Nickolay Goppen @ 2025-09-03 13:39 ` Nickolay Goppen 2025-09-03 13:39 ` [PATCH v5 2/3] dt-bindings: pinctrl: qcom: Add SDM660 LPI pinctrl Nickolay Goppen 2025-09-03 13:39 ` [PATCH v5 3/3] pinctrl: qcom: Add SDM660 LPASS LPI TLMM Nickolay Goppen 2 siblings, 0 replies; 6+ messages in thread From: Nickolay Goppen @ 2025-09-03 13:39 UTC (permalink / raw) To: Bjorn Andersson, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Nickolay Goppen Cc: linux-arm-msm, linux-gpio, linux-kernel, devicetree, ~postmarketos/upstreaming, linux, Nickolay Goppen By default pin_offset is calculated by formula: LPI_TLMM_REG_OFFSET * pin_id. However not all platforms are using this pin_offset formula (e.g. SDM660 LPASS LPI uses a predefined array of offsets [1]), so extend lpi_pingroup struct with pin_offset field, introduce extended LPI_PINGROUP_OFFSET macro with pin_offet field and introduce LPI_FLAG_USE_PREDEFINED_PIN_OFFSET flag. This adds an ability to use predefined offset for pin if it exists. [1] https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/LA.UM.7.2.c27-07400-sdm660.0/drivers/pinctrl/qcom/pinctrl-lpi.c#L107 Signed-off-by: Nickolay Goppen <setotau@mainlining.org> --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 18 ++++++++++++++++-- drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 18 ++++++++++++++++++ 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index 54c77e0b96e91de8d96ff3cbd0ca88fadc6d55f6..d6c1ba109b958296acd8f129a781da1a08e8e438 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -41,13 +41,27 @@ struct lpi_pinctrl { static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, unsigned int addr) { - return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr); + u32 pin_offset; + + if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET) + pin_offset = state->data->groups[pin].pin_offset; + else + pin_offset = LPI_TLMM_REG_OFFSET * pin; + + return ioread32(state->tlmm_base + pin_offset + addr); } static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin, unsigned int addr, unsigned int val) { - iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr); + u32 pin_offset; + + if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET) + pin_offset = state->data->groups[pin].pin_offset; + else + pin_offset = LPI_TLMM_REG_OFFSET * pin; + + iowrite32(val, state->tlmm_base + pin_offset + addr); return 0; } diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h index a9b2f65c1ebe0f8fb5d7814f8ef8b723c617c85b..f48368492861348519ea19b5291ac7df13050eef 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h @@ -55,6 +55,22 @@ struct pinctrl_pin_desc; LPI_MUX_##f4, \ }, \ .nfuncs = 5, \ + .pin_offset = 0, \ + } + +#define LPI_PINGROUP_OFFSET(id, soff, f1, f2, f3, f4, poff) \ + { \ + .pin = id, \ + .slew_offset = soff, \ + .funcs = (int[]){ \ + LPI_MUX_gpio, \ + LPI_MUX_##f1, \ + LPI_MUX_##f2, \ + LPI_MUX_##f3, \ + LPI_MUX_##f4, \ + }, \ + .nfuncs = 5, \ + .pin_offset = poff, \ } /* @@ -62,6 +78,7 @@ struct pinctrl_pin_desc; * pin configuration. */ #define LPI_FLAG_SLEW_RATE_SAME_REG BIT(0) +#define LPI_FLAG_USE_PREDEFINED_PIN_OFFSET BIT(1) struct lpi_pingroup { unsigned int pin; @@ -69,6 +86,7 @@ struct lpi_pingroup { int slew_offset; unsigned int *funcs; unsigned int nfuncs; + unsigned int pin_offset; }; struct lpi_function { -- 2.51.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v5 2/3] dt-bindings: pinctrl: qcom: Add SDM660 LPI pinctrl 2025-09-03 13:39 [PATCH v5 0/3] Add SDM660 LPASS LPI TLMM Nickolay Goppen 2025-09-03 13:39 ` [PATCH v5 1/3] pinctrl: qcom: lpass-lpi: Add ability to use custom pin offsets Nickolay Goppen @ 2025-09-03 13:39 ` Nickolay Goppen 2025-09-03 14:14 ` Krzysztof Kozlowski 2025-09-03 13:39 ` [PATCH v5 3/3] pinctrl: qcom: Add SDM660 LPASS LPI TLMM Nickolay Goppen 2 siblings, 1 reply; 6+ messages in thread From: Nickolay Goppen @ 2025-09-03 13:39 UTC (permalink / raw) To: Bjorn Andersson, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Nickolay Goppen Cc: linux-arm-msm, linux-gpio, linux-kernel, devicetree, ~postmarketos/upstreaming, linux, Nickolay Goppen, Richard Acayan Add bindings for pin controller in SDM660 Low Power Audio SubSystem (LPASS). Co-developed-by: Richard Acayan <mailingradian@gmail.com> Signed-off-by: Richard Acayan <mailingradian@gmail.com> Signed-off-by: Nickolay Goppen <setotau@mainlining.org> --- .../pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml | 109 +++++++++++++++++++++ 1 file changed, 109 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml new file mode 100644 index 0000000000000000000000000000000000000000..175d5dbf54fa3669805cb69d5b4df19ab57c1520 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDM660 SoC LPASS LPI TLMM + +maintainers: + - Nickolay Goppen <setotau@mainlining.org> + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem + (LPASS) Low Power Island (LPI) of Qualcomm SDM660 SoC. + +properties: + compatible: + const: qcom,sdm660-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sdm660-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sdm660-lpass-state" + additionalProperties: false + +$defs: + qcom-sdm660-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-2][0-9]|3[0-1])$" + + function: + enum: [ gpio, comp_rx, dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, + mclk0, pdm_tx, pdm_clk, pdm_rx, pdm_sync ] + description: + Specify the alternative function to be configured for the specified + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + lpi_tlmm: pinctrl@15070000 { + compatible = "qcom,sdm660-lpass-lpi-pinctrl"; + reg = <0x15070000 0x20000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpi_tlmm 0 0 32>; + + cdc_pdm_default: cdc-pdm-default-state { + clk-pins { + pins = "gpio18"; + function = "pdm_clk"; + drive-strength = <8>; + output-high; + }; + + sync-pins{ + pins = "gpio19"; + function = "pdm_sync"; + drive-strength = <4>; + output-high; + }; + + tx-pins { + pins = "gpio20"; + function = "pdm_tx"; + drive-strength = <8>; + }; + + rx-pins { + pins = "gpio21", "gpio23", "gpio25"; + function = "pdm_rx"; + drive-strength = <4>; + output-high; + }; + }; + + cdc_comp_default: cdc-comp-default-state { + pins = "gpio22", "gpio24"; + function = "comp_rx"; + drive-strength = <8>; + }; + }; -- 2.51.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v5 2/3] dt-bindings: pinctrl: qcom: Add SDM660 LPI pinctrl 2025-09-03 13:39 ` [PATCH v5 2/3] dt-bindings: pinctrl: qcom: Add SDM660 LPI pinctrl Nickolay Goppen @ 2025-09-03 14:14 ` Krzysztof Kozlowski 0 siblings, 0 replies; 6+ messages in thread From: Krzysztof Kozlowski @ 2025-09-03 14:14 UTC (permalink / raw) To: Nickolay Goppen, Bjorn Andersson, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, linux-gpio, linux-kernel, devicetree, ~postmarketos/upstreaming, linux, Nickolay Goppen, Richard Acayan On 03/09/2025 15:39, Nickolay Goppen wrote: > + > +examples: > + - | > + lpi_tlmm: pinctrl@15070000 { > + compatible = "qcom,sdm660-lpass-lpi-pinctrl"; > + reg = <0x15070000 0x20000>; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&lpi_tlmm 0 0 32>; > + > + cdc_pdm_default: cdc-pdm-default-state { > + clk-pins { Messed indentation. Keep four spaces. > + pins = "gpio18"; > + function = "pdm_clk"; > + drive-strength = <8>; > + output-high; > + }; > + > + sync-pins{ > + pins = "gpio19"; > + function = "pdm_sync"; > + drive-strength = <4>; > + output-high; > + }; > + > + tx-pins { > + pins = "gpio20"; > + function = "pdm_tx"; > + drive-strength = <8>; > + }; > + > + rx-pins { > + pins = "gpio21", "gpio23", "gpio25"; > + function = "pdm_rx"; > + drive-strength = <4>; > + output-high; > + }; > + }; > + > + cdc_comp_default: cdc-comp-default-state { > + pins = "gpio22", "gpio24"; Also here. With these fixed: Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v5 3/3] pinctrl: qcom: Add SDM660 LPASS LPI TLMM 2025-09-03 13:39 [PATCH v5 0/3] Add SDM660 LPASS LPI TLMM Nickolay Goppen 2025-09-03 13:39 ` [PATCH v5 1/3] pinctrl: qcom: lpass-lpi: Add ability to use custom pin offsets Nickolay Goppen 2025-09-03 13:39 ` [PATCH v5 2/3] dt-bindings: pinctrl: qcom: Add SDM660 LPI pinctrl Nickolay Goppen @ 2025-09-03 13:39 ` Nickolay Goppen 2025-09-03 21:23 ` Richard Acayan 2 siblings, 1 reply; 6+ messages in thread From: Nickolay Goppen @ 2025-09-03 13:39 UTC (permalink / raw) To: Bjorn Andersson, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Nickolay Goppen Cc: linux-arm-msm, linux-gpio, linux-kernel, devicetree, ~postmarketos/upstreaming, linux, Nickolay Goppen, Richard Acayan From: Richard Acayan <mailingradian@gmail.com> The Snapdragon 660 has a Low-Power Island (LPI) TLMM for configuring pins related to audio. Add the driver for this. Also, this driver uses predefined pin_offsets for each pin taken from downstream driver, which does not follow the usual 0x1000 distance between pins and uses an array with predefined offsets that do not follow any regular pattern [1]. [1] https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/LA.UM.7.2.c27-07400-sdm660.0/drivers/pinctrl/qcom/pinctrl-lpi.c#L107 Signed-off-by: Richard Acayan <mailingradian@gmail.com> Co-developed-by: Nickolay Goppen <setotau@mainlining.org> Signed-off-by: Nickolay Goppen <setotau@mainlining.org> --- drivers/pinctrl/qcom/Kconfig | 10 ++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c | 161 ++++++++++++++++++++++++ 3 files changed, 172 insertions(+) diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index dd9bbe8f3e11c37418d2143b33c21eeea10d456b..ef42520115f461302098d878cb76c6f25e55b5e4 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -68,6 +68,16 @@ config PINCTRL_SC7280_LPASS_LPI Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI (Low Power Island) found on the Qualcomm Technologies Inc SC7280 platform. +config PINCTRL_SDM660_LPASS_LPI + tristate "Qualcomm Technologies Inc SDM660 LPASS LPI pin controller driver" + depends on GPIOLIB + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SDM660 platform. + config PINCTRL_SM4250_LPASS_LPI tristate "Qualcomm Technologies Inc SM4250 LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 2acff520a285a47a4a179f815402adaa5ce5addd..a81c1e127897a50fb2136c5eb38a076ebe5709a6 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_PINCTRL_SC7280_LPASS_LPI) += pinctrl-sc7280-lpass-lpi.o obj-$(CONFIG_PINCTRL_SC8180X) += pinctrl-sc8180x.o obj-$(CONFIG_PINCTRL_SC8280XP) += pinctrl-sc8280xp.o obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o +obj-$(CONFIG_PINCTRL_SDM660_LPASS_LPI) += pinctrl-sdm660-lpass-lpi.o obj-$(CONFIG_PINCTRL_SDM670) += pinctrl-sdm670.o obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o diff --git a/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c new file mode 100644 index 0000000000000000000000000000000000000000..a8dae43f19c3cf5025bf17860685d05407305c11 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * This driver is solely based on the limited information in downstream code. + * Any verification with schematics would be greatly appreciated. + * + * Copyright (c) 2023, Richard Acayan. All rights reserved. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_comp_rx, + LPI_MUX_dmic1_clk, + LPI_MUX_dmic1_data, + LPI_MUX_dmic2_clk, + LPI_MUX_dmic2_data, + LPI_MUX_mclk0, + LPI_MUX_pdm_tx, + LPI_MUX_pdm_clk, + LPI_MUX_pdm_rx, + LPI_MUX_pdm_sync, + + LPI_MUX_gpio, + LPI_MUX__, +}; + +static const struct pinctrl_pin_desc sdm660_lpi_pinctrl_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), + PINCTRL_PIN(19, "gpio19"), + PINCTRL_PIN(20, "gpio20"), + PINCTRL_PIN(21, "gpio21"), + PINCTRL_PIN(22, "gpio22"), + PINCTRL_PIN(23, "gpio23"), + PINCTRL_PIN(24, "gpio24"), + PINCTRL_PIN(25, "gpio25"), + PINCTRL_PIN(26, "gpio26"), + PINCTRL_PIN(27, "gpio27"), + PINCTRL_PIN(28, "gpio28"), + PINCTRL_PIN(29, "gpio29"), + PINCTRL_PIN(30, "gpio30"), + PINCTRL_PIN(31, "gpio31"), +}; + +static const char * const comp_rx_groups[] = { "gpio22", "gpio24" }; +static const char * const dmic1_clk_groups[] = { "gpio26" }; +static const char * const dmic1_data_groups[] = { "gpio27" }; +static const char * const dmic2_clk_groups[] = { "gpio28" }; +static const char * const dmic2_data_groups[] = { "gpio29" }; +static const char * const mclk0_groups[] = { "gpio18" }; +static const char * const pdm_tx_groups[] = { "gpio20" }; +static const char * const pdm_clk_groups[] = { "gpio18" }; +static const char * const pdm_rx_groups[] = { "gpio21", "gpio23", "gpio25" }; +static const char * const pdm_sync_groups[] = { "gpio19" }; + +const struct lpi_pingroup sdm660_lpi_pinctrl_groups[] = { + LPI_PINGROUP_OFFSET(0, LPI_NO_SLEW, _, _, _, _, 0x0000), + LPI_PINGROUP_OFFSET(1, LPI_NO_SLEW, _, _, _, _, 0x1000), + LPI_PINGROUP_OFFSET(2, LPI_NO_SLEW, _, _, _, _, 0x2000), + LPI_PINGROUP_OFFSET(3, LPI_NO_SLEW, _, _, _, _, 0x2010), + LPI_PINGROUP_OFFSET(4, LPI_NO_SLEW, _, _, _, _, 0x3000), + LPI_PINGROUP_OFFSET(5, LPI_NO_SLEW, _, _, _, _, 0x3010), + LPI_PINGROUP_OFFSET(6, LPI_NO_SLEW, _, _, _, _, 0x4000), + LPI_PINGROUP_OFFSET(7, LPI_NO_SLEW, _, _, _, _, 0x4010), + LPI_PINGROUP_OFFSET(8, LPI_NO_SLEW, _, _, _, _, 0x5000), + LPI_PINGROUP_OFFSET(9, LPI_NO_SLEW, _, _, _, _, 0x5010), + LPI_PINGROUP_OFFSET(10, LPI_NO_SLEW, _, _, _, _, 0x5020), + LPI_PINGROUP_OFFSET(11, LPI_NO_SLEW, _, _, _, _, 0x5030), + LPI_PINGROUP_OFFSET(12, LPI_NO_SLEW, _, _, _, _, 0x6000), + LPI_PINGROUP_OFFSET(13, LPI_NO_SLEW, _, _, _, _, 0x6010), + LPI_PINGROUP_OFFSET(14, LPI_NO_SLEW, _, _, _, _, 0x7000), + LPI_PINGROUP_OFFSET(15, LPI_NO_SLEW, _, _, _, _, 0x7010), + LPI_PINGROUP_OFFSET(16, LPI_NO_SLEW, _, _, _, _, 0x5040), + LPI_PINGROUP_OFFSET(17, LPI_NO_SLEW, _, _, _, _, 0x5050), + + /* The function names of the PDM GPIOs are derived from SDM670 */ + LPI_PINGROUP_OFFSET(18, LPI_NO_SLEW, pdm_clk, mclk0, _, _, 0x8000), + LPI_PINGROUP_OFFSET(19, LPI_NO_SLEW, pdm_sync, _, _, _, 0x8010), + LPI_PINGROUP_OFFSET(20, LPI_NO_SLEW, pdm_tx, _, _, _, 0x8020), + LPI_PINGROUP_OFFSET(21, LPI_NO_SLEW, pdm_rx, _, _, _, 0x8030), + LPI_PINGROUP_OFFSET(22, LPI_NO_SLEW, comp_rx, _, _, _, 0x8040), + LPI_PINGROUP_OFFSET(23, LPI_NO_SLEW, pdm_rx, _, _, _, 0x8050), + LPI_PINGROUP_OFFSET(24, LPI_NO_SLEW, comp_rx, _, _, _, 0x8060), + LPI_PINGROUP_OFFSET(25, LPI_NO_SLEW, pdm_rx, _, _, _, 0x8070), + LPI_PINGROUP_OFFSET(26, LPI_NO_SLEW, dmic1_clk, _, _, _, 0x9000), + LPI_PINGROUP_OFFSET(27, LPI_NO_SLEW, dmic1_data, _, _, _, 0x9010), + LPI_PINGROUP_OFFSET(28, LPI_NO_SLEW, dmic2_clk, _, _, _, 0xa000), + LPI_PINGROUP_OFFSET(29, LPI_NO_SLEW, dmic2_data, _, _, _, 0xa010), + + LPI_PINGROUP_OFFSET(30, LPI_NO_SLEW, _, _, _, _, 0xb000), + LPI_PINGROUP_OFFSET(31, LPI_NO_SLEW, _, _, _, _, 0xb010), +}; + +const struct lpi_function sdm660_lpi_pinctrl_functions[] = { + LPI_FUNCTION(comp_rx), + LPI_FUNCTION(dmic1_clk), + LPI_FUNCTION(dmic1_data), + LPI_FUNCTION(dmic2_clk), + LPI_FUNCTION(dmic2_data), + LPI_FUNCTION(mclk0), + LPI_FUNCTION(pdm_tx), + LPI_FUNCTION(pdm_clk), + LPI_FUNCTION(pdm_rx), + LPI_FUNCTION(pdm_sync), +}; + +static const struct lpi_pinctrl_variant_data sdm660_lpi_pinctrl_data = { + .pins = sdm660_lpi_pinctrl_pins, + .npins = ARRAY_SIZE(sdm660_lpi_pinctrl_pins), + .groups = sdm660_lpi_pinctrl_groups, + .ngroups = ARRAY_SIZE(sdm660_lpi_pinctrl_groups), + .functions = sdm660_lpi_pinctrl_functions, + .nfunctions = ARRAY_SIZE(sdm660_lpi_pinctrl_functions), + .flags = LPI_FLAG_SLEW_RATE_SAME_REG | LPI_FLAG_USE_PREDEFINED_PIN_OFFSET +}; + +static const struct of_device_id sdm660_lpi_pinctrl_of_match[] = { + { + .compatible = "qcom,sdm660-lpass-lpi-pinctrl", + .data = &sdm660_lpi_pinctrl_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, sdm660_lpi_pinctrl_of_match); + +static struct platform_driver sdm660_lpi_pinctrl_driver = { + .driver = { + .name = "qcom-sdm660-lpass-lpi-pinctrl", + .of_match_table = sdm660_lpi_pinctrl_of_match, + }, + .probe = lpi_pinctrl_probe, + .remove = lpi_pinctrl_remove, +}; +module_platform_driver(sdm660_lpi_pinctrl_driver); + +MODULE_AUTHOR("Richard Acayan <mailingradian@gmail.com>"); +MODULE_DESCRIPTION("QTI SDM660 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); -- 2.51.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v5 3/3] pinctrl: qcom: Add SDM660 LPASS LPI TLMM 2025-09-03 13:39 ` [PATCH v5 3/3] pinctrl: qcom: Add SDM660 LPASS LPI TLMM Nickolay Goppen @ 2025-09-03 21:23 ` Richard Acayan 0 siblings, 0 replies; 6+ messages in thread From: Richard Acayan @ 2025-09-03 21:23 UTC (permalink / raw) To: Nickolay Goppen Cc: Bjorn Andersson, Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, linux-gpio, linux-kernel, devicetree, ~postmarketos/upstreaming, linux, Nickolay Goppen On Wed, Sep 03, 2025 at 04:39:03PM +0300, Nickolay Goppen wrote: > From: Richard Acayan <mailingradian@gmail.com> > > The Snapdragon 660 has a Low-Power Island (LPI) TLMM for configuring > pins related to audio. Add the driver for this. > Also, this driver uses predefined pin_offsets for each pin taken from > downstream driver, which does not follow the usual 0x1000 distance > between pins and uses an array with predefined offsets that do not > follow any regular pattern [1]. > > [1] https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/LA.UM.7.2.c27-07400-sdm660.0/drivers/pinctrl/qcom/pinctrl-lpi.c#L107 > > Signed-off-by: Richard Acayan <mailingradian@gmail.com> > Co-developed-by: Nickolay Goppen <setotau@mainlining.org> > Signed-off-by: Nickolay Goppen <setotau@mainlining.org> > --- (snip) > +const struct lpi_pingroup sdm660_lpi_pinctrl_groups[] = { > + LPI_PINGROUP_OFFSET(0, LPI_NO_SLEW, _, _, _, _, 0x0000), > + LPI_PINGROUP_OFFSET(1, LPI_NO_SLEW, _, _, _, _, 0x1000), > + LPI_PINGROUP_OFFSET(2, LPI_NO_SLEW, _, _, _, _, 0x2000), > + LPI_PINGROUP_OFFSET(3, LPI_NO_SLEW, _, _, _, _, 0x2010), > + LPI_PINGROUP_OFFSET(4, LPI_NO_SLEW, _, _, _, _, 0x3000), > + LPI_PINGROUP_OFFSET(5, LPI_NO_SLEW, _, _, _, _, 0x3010), > + LPI_PINGROUP_OFFSET(6, LPI_NO_SLEW, _, _, _, _, 0x4000), > + LPI_PINGROUP_OFFSET(7, LPI_NO_SLEW, _, _, _, _, 0x4010), > + LPI_PINGROUP_OFFSET(8, LPI_NO_SLEW, _, _, _, _, 0x5000), > + LPI_PINGROUP_OFFSET(9, LPI_NO_SLEW, _, _, _, _, 0x5010), > + LPI_PINGROUP_OFFSET(10, LPI_NO_SLEW, _, _, _, _, 0x5020), > + LPI_PINGROUP_OFFSET(11, LPI_NO_SLEW, _, _, _, _, 0x5030), > + LPI_PINGROUP_OFFSET(12, LPI_NO_SLEW, _, _, _, _, 0x6000), > + LPI_PINGROUP_OFFSET(13, LPI_NO_SLEW, _, _, _, _, 0x6010), > + LPI_PINGROUP_OFFSET(14, LPI_NO_SLEW, _, _, _, _, 0x7000), > + LPI_PINGROUP_OFFSET(15, LPI_NO_SLEW, _, _, _, _, 0x7010), > + LPI_PINGROUP_OFFSET(16, LPI_NO_SLEW, _, _, _, _, 0x5040), > + LPI_PINGROUP_OFFSET(17, LPI_NO_SLEW, _, _, _, _, 0x5050), > + > + /* The function names of the PDM GPIOs are derived from SDM670 */ Not anymore, the names now match the other LPI drivers closer. This can be removed. ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-09-03 21:23 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-09-03 13:39 [PATCH v5 0/3] Add SDM660 LPASS LPI TLMM Nickolay Goppen 2025-09-03 13:39 ` [PATCH v5 1/3] pinctrl: qcom: lpass-lpi: Add ability to use custom pin offsets Nickolay Goppen 2025-09-03 13:39 ` [PATCH v5 2/3] dt-bindings: pinctrl: qcom: Add SDM660 LPI pinctrl Nickolay Goppen 2025-09-03 14:14 ` Krzysztof Kozlowski 2025-09-03 13:39 ` [PATCH v5 3/3] pinctrl: qcom: Add SDM660 LPASS LPI TLMM Nickolay Goppen 2025-09-03 21:23 ` Richard Acayan
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