* [PATCH] clk: at91: clk-master: Add check for divide by 3
@ 2025-09-08 20:07 Ryan.Wanner
2025-09-09 7:57 ` Nicolas Ferre
0 siblings, 1 reply; 3+ messages in thread
From: Ryan.Wanner @ 2025-09-08 20:07 UTC (permalink / raw)
To: mturquette, sboyd, nicolas.ferre, alexandre.belloni,
claudiu.beznea
Cc: linux-clk, linux-arm-kernel, linux-kernel, Ryan Wanner
From: Ryan Wanner <Ryan.Wanner@microchip.com>
A potential divider for the master clock is div/3. The register
configuration for div/3 is MASTER_PRES_MAX. The current bit shifting
method does not work for this case. Checking for MASTER_PRES_MAX will
ensure the correct decimal value is stored in the system.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
---
drivers/clk/at91/clk-master.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
index 7a544e429d34..d5ea2069ec83 100644
--- a/drivers/clk/at91/clk-master.c
+++ b/drivers/clk/at91/clk-master.c
@@ -580,6 +580,9 @@ clk_sama7g5_master_recalc_rate(struct clk_hw *hw,
{
struct clk_master *master = to_clk_master(hw);
+ if (master->div == MASTER_PRES_MAX)
+ return DIV_ROUND_CLOSEST_ULL(parent_rate, 3);
+
return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div));
}
--
2.43.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] clk: at91: clk-master: Add check for divide by 3
2025-09-08 20:07 [PATCH] clk: at91: clk-master: Add check for divide by 3 Ryan.Wanner
@ 2025-09-09 7:57 ` Nicolas Ferre
2025-09-15 14:54 ` Nicolas Ferre
0 siblings, 1 reply; 3+ messages in thread
From: Nicolas Ferre @ 2025-09-09 7:57 UTC (permalink / raw)
To: Ryan.Wanner, mturquette, sboyd, alexandre.belloni, claudiu.beznea
Cc: linux-clk, linux-arm-kernel, linux-kernel
On 08/09/2025 at 22:07, Ryan.Wanner@microchip.com wrote:
> From: Ryan Wanner <Ryan.Wanner@microchip.com>
>
> A potential divider for the master clock is div/3. The register
> configuration for div/3 is MASTER_PRES_MAX. The current bit shifting
> method does not work for this case. Checking for MASTER_PRES_MAX will
> ensure the correct decimal value is stored in the system.
>
> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Thanks Ryan, regards,
Nicolas
> ---
> drivers/clk/at91/clk-master.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
> index 7a544e429d34..d5ea2069ec83 100644
> --- a/drivers/clk/at91/clk-master.c
> +++ b/drivers/clk/at91/clk-master.c
> @@ -580,6 +580,9 @@ clk_sama7g5_master_recalc_rate(struct clk_hw *hw,
> {
> struct clk_master *master = to_clk_master(hw);
>
> + if (master->div == MASTER_PRES_MAX)
> + return DIV_ROUND_CLOSEST_ULL(parent_rate, 3);
> +
> return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div));
> }
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] clk: at91: clk-master: Add check for divide by 3
2025-09-09 7:57 ` Nicolas Ferre
@ 2025-09-15 14:54 ` Nicolas Ferre
0 siblings, 0 replies; 3+ messages in thread
From: Nicolas Ferre @ 2025-09-15 14:54 UTC (permalink / raw)
To: Ryan.Wanner, mturquette, sboyd, alexandre.belloni, claudiu.beznea
Cc: linux-clk, linux-arm-kernel, linux-kernel
On 09/09/2025 at 09:57, Nicolas Ferre wrote:
> On 08/09/2025 at 22:07, Ryan.Wanner@microchip.com wrote:
>> From: Ryan Wanner <Ryan.Wanner@microchip.com>
>>
>> A potential divider for the master clock is div/3. The register
>> configuration for div/3 is MASTER_PRES_MAX. The current bit shifting
>> method does not work for this case. Checking for MASTER_PRES_MAX will
>> ensure the correct decimal value is stored in the system.
>>
>> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
>
> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Added to clk-microchip, on its way upstream.
Thanks, regards,
Nicolas
> Thanks Ryan, regards,
> Nicolas
>
>> ---
>> drivers/clk/at91/clk-master.c | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
>> index 7a544e429d34..d5ea2069ec83 100644
>> --- a/drivers/clk/at91/clk-master.c
>> +++ b/drivers/clk/at91/clk-master.c
>> @@ -580,6 +580,9 @@ clk_sama7g5_master_recalc_rate(struct clk_hw *hw,
>> {
>> struct clk_master *master = to_clk_master(hw);
>>
>> + if (master->div == MASTER_PRES_MAX)
>> + return DIV_ROUND_CLOSEST_ULL(parent_rate, 3);
>> +
>> return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div));
>> }
>>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2025-09-15 14:55 UTC | newest]
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2025-09-08 20:07 [PATCH] clk: at91: clk-master: Add check for divide by 3 Ryan.Wanner
2025-09-09 7:57 ` Nicolas Ferre
2025-09-15 14:54 ` Nicolas Ferre
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