From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E442EEA6; Tue, 9 Sep 2025 04:41:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757392891; cv=none; b=dTbsAaVuhxIQ84Wdqt2e3siA6aCGu1Poq2ssSsga4uAdoEH1gcaAVzFqSXuxuJxVPMCzgqJE58JPEpFnbj/M+rYEWkGpCzZ4tm1kaihIr8pIuP6BKqoYOS3OwGYLsMyjAslN35gb8Iih6xVfSn+0kk4BgGTpNrD87cR7TOhaS6I= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757392891; c=relaxed/simple; bh=jsXYq76Iv0Csr8xnWpcRC7BgYLsHqoZ3kp51sOKDCVE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XZEtopeVdoEELdAXSDdNSd7jrunk1NDRVoR+XUODtzMTAOTYQBgl0uE1p02XkmlFhjAGKmhfRr03QPzu/69232o6wnsgIwsjGFfr/RtlnLauZDUZQT5xHzjJhYe7ha9V/k9Ud++c6t3dP+hdYxkaxeUmCcxumsQIIavTSXfHZEc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=k+8h1a2Q; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="k+8h1a2Q" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTP id 5894fO2D3944852; Mon, 8 Sep 2025 23:41:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1757392884; bh=hg/6V1DrIAFitVq1xSCS16pIBKnsixz0Nh0utF/XxZM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=k+8h1a2QUCRm34hBPZ/fQ0Z05+Av19GTdAUvaPTHdkLJ9HZTRpQuIwoQ0yswwvCxt 3Z1h5388BT4g6yXKZQuRixLydzRo5f/sfjNS+y3P5FlHZvbY0LEAM237bo2NC7OZsg SE2+YETspZsQ4yrKYEdfWaBoZvwCfIxb3HocQVVM= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 5894fO5b089313 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Mon, 8 Sep 2025 23:41:24 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Mon, 8 Sep 2025 23:41:23 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Mon, 8 Sep 2025 23:41:23 -0500 Received: from akashdeep-HP-Z2-Tower-G5-Workstation.dhcp.ti.com (akashdeep-hp-z2-tower-g5-workstation.dhcp.ti.com [10.24.68.177]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 5894fAkD2012008; Mon, 8 Sep 2025 23:41:18 -0500 From: Akashdeep Kaur To: , , , , , , , , , , , , , , CC: , Subject: [PATCH v6 1/4] arm64: dts: ti: k3-am62p5-sk: Remove the unused cfg in USB1_DRVVBUS Date: Tue, 9 Sep 2025 10:11:05 +0530 Message-ID: <20250909044108.2541534-2-a-kaur@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250909044108.2541534-1-a-kaur@ti.com> References: <20250909044108.2541534-1-a-kaur@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea After the SoC has entered the DeepSleep low power mode, USB1 can be used to wakeup the SoC based on USB events triggered by USB devices. This requires that the pin corresponding to the Type-A connector remains pulled up even after the SoC has entered the DeepSleep low power mode. For that, either DeepSleep pullup configuration can be selected or the pin can have the same configuration that it had when SoC was in active mode. Remove the unnecessary DeepSleep state configuration from USB1_DRVBUS pin, as the DeepSleep control bit is not set and the active configuration is sufficient to keep the pin pulled up. This simplifies the setup and removes redundant configuration. This reverts commit 115290c112952db27009668aa7ae2f29920704f0. Tested-by: Kendall Willis Reviewed-by: Dhruva Gole Signed-off-by: Akashdeep Kaur --- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index 899da7896563..e8f0ac2c55e2 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -360,7 +360,7 @@ AM62PX_IOPAD(0x01b0, PIN_OUTPUT, 2) /* (G20) MCASP0_ACLKR.UART1_TXD */ main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins = < - AM62PX_IOPAD(0x0258, PIN_INPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP, 0) /* (G21) USB1_DRVVBUS */ + AM62PX_IOPAD(0x0258, PIN_INPUT, 0) /* (G21) USB1_DRVVBUS */ >; }; -- 2.34.1