Re: [PATCH v2 2/4] arm64: dts: rockchip: Add USB2.0 PHY for RK3368

Vladimir Oltean
2026-02-12T16:55:55Z

On Tue, Sep 09, 2025 at 09:29:56PM +0800, WeiHao Li wrote:
> RK3368 has one USB2.0 PHY with two ports, This adds device tree node for
> it.
>
> Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
> ---
> arch/arm64/boot/dts/rockchip/rk3368.dtsi | 29 ++++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> index 1b21787269..b09e431a64 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> @@ -766,11 +766,40 @@ cru: clock-controller@ff760000 {
> grf: syscon@ff770000 {
> compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
> reg = <0x0 0xff770000 0x0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;

This introduces a device tree warning. You cannot mix nodes with no unit
address (io-domains) with nodes with a unit address (usb2-phy@700) on
the same hierarchical level. You have to pick a format and stick to it.

>
> io_domains: io-domains {
> compatible = "rockchip,rk3368-io-voltage-domain";
> status = "disabled";
> };
> +
> + u2phy: usb2-phy@700 {
> + compatible = "rockchip,rk3368-usb2phy";
> + reg = <0x700 0x2c>;
> + clocks = <&cru SCLK_OTGPHY0>;
> + clock-names = "phyclk";
> + clock-output-names = "usb480m_phy";
> + #clock-cells = <0>;
> + status = "disabled";
> +
> + u2phy_otg: otg-port {
> + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "otg-bvalid", "otg-id",
> + "linestate";
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> +
> + u2phy_host: host-port {
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "linestate";
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> + };
> };
>
> wdt: watchdog@ff800000 {
> --
> 2.47.2
>
>