[PATCH v2 03/23] clk: tegra30: add CSI pad clock gates

Svyatoslav Ryhel
2025-09-06T13:54:08Z

Tegra30 has CSI pad bits in both PLLD and PLLD2 clocks that are required
for the correct work of the CSI block. Add CSI pad A and pad B clock gates
with PLLD/PLLD2 parents, respectively. Add plld2 spinlock, like one plld
has to be used for clock gate registration.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
---
drivers/clk/tegra/clk-tegra30.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index ca738bc64615..61fe527ee6c1 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -154,6 +154,7 @@ static unsigned long input_freq;

static DEFINE_SPINLOCK(cml_lock);
static DEFINE_SPINLOCK(pll_d_lock);
+static DEFINE_SPINLOCK(pll_d2_lock);

#define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \
_clk_num, _gate_flags, _clk_id) \
@@ -859,7 +860,7 @@ static void __init tegra30_pll_init(void)

/* PLLD2 */
clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,
- &pll_d2_params, NULL);
+ &pll_d2_params, &pll_d2_lock);
clks[TEGRA30_CLK_PLL_D2] = clk;

/* PLLD2_OUT0 */
@@ -1008,6 +1009,16 @@ static void __init tegra30_periph_clk_init(void)
0, 48, periph_clk_enb_refcnt);
clks[TEGRA30_CLK_DSIA] = clk;

+ /* csia_pad */
+ clk = clk_register_gate(NULL, "csia_pad", "pll_d", CLK_SET_RATE_PARENT,
+ clk_base + PLLD_BASE, 26, 0, &pll_d_lock);
+ clks[TEGRA30_CLK_CSIA_PAD] = clk;
+
+ /* csib_pad */
+ clk = clk_register_gate(NULL, "csib_pad", "pll_d2", CLK_SET_RATE_PARENT,
+ clk_base + PLLD2_BASE, 26, 0, &pll_d2_lock);
+ clks[TEGRA30_CLK_CSIB_PAD] = clk;
+
/* csus */
clk = tegra_clk_register_periph_gate("csus", "vi_sensor", 0,
clk_base, 0, TEGRA30_CLK_CSUS,
--
2.48.1