From: Bjorn Helgaas <helgaas@kernel.org>
To: Chen Wang <unicornxw@gmail.com>
Cc: kwilczynski@kernel.org, u.kleine-koenig@baylibre.com,
aou@eecs.berkeley.edu, alex@ghiti.fr, arnd@arndb.de,
bwawrzyn@cisco.com, bhelgaas@google.com,
unicorn_wang@outlook.com, conor+dt@kernel.org,
18255117159@163.com, inochiama@gmail.com, kishon@kernel.org,
krzk+dt@kernel.org, lpieralisi@kernel.org, mani@kernel.org,
palmer@dabbelt.com, paul.walmsley@sifive.com, robh@kernel.org,
s-vadapalli@ti.com, tglx@linutronix.de,
thomas.richard@bootlin.com, sycamoremoon376@gmail.com,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org,
sophgo@lists.linux.dev, rabenda.cn@gmail.com,
chao.wei@sophgo.com, xiaoguang.xing@sophgo.com,
fengchun.li@sophgo.com
Subject: Re: [PATCH v2 2/7] PCI: cadence: Check pcie-ops before using it.
Date: Wed, 10 Sep 2025 09:23:21 -0500 [thread overview]
Message-ID: <20250910142321.GA1533672@bhelgaas> (raw)
In-Reply-To: <18aba25b853d00caf10cc784093c0b91fdc1747d.1757467895.git.unicorn_wang@outlook.com>
Drop period at end of subject.
On Wed, Sep 10, 2025 at 10:08:16AM +0800, Chen Wang wrote:
> From: Chen Wang <unicorn_wang@outlook.com>
>
> ops of struct cdns_pcie may be NULL, direct use
> will result in a null pointer error.
>
> Add checking of pcie->ops before using it for new
> driver that may not supply pcie->ops.
>
> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
> ---
> drivers/pci/controller/cadence/pcie-cadence-host.c | 2 +-
> drivers/pci/controller/cadence/pcie-cadence.c | 4 ++--
> drivers/pci/controller/cadence/pcie-cadence.h | 6 +++---
> 3 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
> index 59a4631de79f..fffd63d6665e 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> @@ -531,7 +531,7 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
> cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(0), addr1);
> cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(0), desc1);
>
> - if (pcie->ops->cpu_addr_fixup)
> + if (pcie->ops && pcie->ops->cpu_addr_fixup)
> cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr);
>
> addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(12) |
> diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c
> index 70a19573440e..61806bbd8aa3 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence.c
> @@ -92,7 +92,7 @@ void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn,
> cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), desc1);
>
> /* Set the CPU address */
> - if (pcie->ops->cpu_addr_fixup)
> + if (pcie->ops && pcie->ops->cpu_addr_fixup)
> cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr);
>
> addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) |
> @@ -123,7 +123,7 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie,
> }
>
> /* Set the CPU address */
> - if (pcie->ops->cpu_addr_fixup)
> + if (pcie->ops && pcie->ops->cpu_addr_fixup)
> cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr);
>
> addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(17) |
> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
> index 1d81c4bf6c6d..2f07ba661bda 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence.h
> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
> @@ -468,7 +468,7 @@ static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg)
>
> static inline int cdns_pcie_start_link(struct cdns_pcie *pcie)
> {
> - if (pcie->ops->start_link)
> + if (pcie->ops && pcie->ops->start_link)
> return pcie->ops->start_link(pcie);
>
> return 0;
> @@ -476,13 +476,13 @@ static inline int cdns_pcie_start_link(struct cdns_pcie *pcie)
>
> static inline void cdns_pcie_stop_link(struct cdns_pcie *pcie)
> {
> - if (pcie->ops->stop_link)
> + if (pcie->ops && pcie->ops->stop_link)
> pcie->ops->stop_link(pcie);
> }
>
> static inline bool cdns_pcie_link_up(struct cdns_pcie *pcie)
> {
> - if (pcie->ops->link_up)
> + if (pcie->ops && pcie->ops->link_up)
> return pcie->ops->link_up(pcie);
>
> return true;
> --
> 2.34.1
>
next prev parent reply other threads:[~2025-09-10 14:23 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-10 2:07 [PATCH v2 0/7] Add PCIe support to Sophgo SG2042 SoC Chen Wang
2025-09-10 2:07 ` [PATCH v2 1/7] dt-bindings: pci: Add Sophgo SG2042 PCIe host Chen Wang
2025-09-10 2:08 ` [PATCH v2 2/7] PCI: cadence: Check pcie-ops before using it Chen Wang
2025-09-10 14:23 ` Bjorn Helgaas [this message]
2025-09-10 2:08 ` [PATCH v2 3/7] PCI: sg2042: Add Sophgo SG2042 PCIe driver Chen Wang
2025-09-10 2:56 ` Inochi Amaoto
2025-09-10 3:20 ` Chen Wang
2025-09-11 17:03 ` Manivannan Sadhasivam
2025-09-12 2:47 ` Inochi Amaoto
2025-09-10 14:34 ` Bjorn Helgaas
2025-09-11 0:09 ` Chen Wang
2025-09-11 16:17 ` Mingcong Bai
2025-09-12 0:52 ` Chen Wang
2025-09-10 2:09 ` [PATCH v2 4/7] riscv: sophgo: dts: add PCIe controllers for SG2042 Chen Wang
2025-09-10 2:09 ` [PATCH v2 5/7] riscv: sophgo: dts: enable PCIe for PioneerBox Chen Wang
2025-09-10 2:10 ` [PATCH v2 6/7] riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.X Chen Wang
2025-09-10 2:10 ` [PATCH v2 7/7] riscv: sophgo: dts: enable PCIe for SG2042_EVB_V2.0 Chen Wang
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