Re: [PATCH v11 03/23] cxl/pci: Remove unnecessary CXL Endpoint handling helper functions

Dave Jiang
2025-08-28T15:28:26Z

On 8/26/25 6:35 PM, Terry Bowman wrote:
> The CXL driver's cxl_handle_endpoint_cor_ras()/cxl_handle_endpoint_ras()
> are unnecessary helper functions used only for Endpoints. Remove these
> functions as they are not common for all CXL devices and do not provide
> value for EP handling.
>
> Rename __cxl_handle_ras to cxl_handle_ras() and __cxl_handle_cor_ras()
> to cxl_handle_cor_ras().
>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>

>
> ---
>
> Changes in v10->v11:
> - None
> ---
> drivers/cxl/core/ras.c | 22 ++++++----------------
> 1 file changed, 6 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c
> index c4f0fa7e40aa..544a0d8773fa 100644
> --- a/drivers/cxl/core/ras.c
> +++ b/drivers/cxl/core/ras.c
> @@ -200,7 +200,7 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host)
> }
> EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL");
>
> -static void __cxl_handle_cor_ras(struct cxl_dev_state *cxlds, void __iomem *ras_base)
> +static void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, void __iomem *ras_base)
> {
> void __iomem *addr;
> u32 status;
> @@ -236,14 +236,14 @@ static void header_log_copy(void __iomem *ras_base, u32 *log)
> static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds,
> struct cxl_dport *dport)
> {
> - return __cxl_handle_cor_ras(cxlds, dport->regs.ras);
> + return cxl_handle_cor_ras(cxlds, dport->regs.ras);
> }
>
> /*
> * Log the state of the RAS status registers and prepare them to log the
> * next error status. Return 1 if reset needed.
> */
> -static bool __cxl_handle_ras(struct cxl_dev_state *cxlds, void __iomem *ras_base)
> +static bool cxl_handle_ras(struct cxl_dev_state *cxlds, void __iomem *ras_base)
> {
> u32 hl[CXL_HEADERLOG_SIZE_U32];
> void __iomem *addr;
> @@ -279,7 +279,7 @@ static bool __cxl_handle_ras(struct cxl_dev_state *cxlds, void __iomem *ras_base
> static bool cxl_handle_rdport_ras(struct cxl_dev_state *cxlds,
> struct cxl_dport *dport)
> {
> - return __cxl_handle_ras(cxlds, dport->regs.ras);
> + return cxl_handle_ras(cxlds, dport->regs.ras);
> }
>
> /*
> @@ -355,16 +355,6 @@ static void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds)
> cxl_handle_rdport_ras(cxlds, dport);
> }
>
> -static void cxl_handle_endpoint_cor_ras(struct cxl_dev_state *cxlds)
> -{
> - return __cxl_handle_cor_ras(cxlds, cxlds->regs.ras);
> -}
> -
> -static bool cxl_handle_endpoint_ras(struct cxl_dev_state *cxlds)
> -{
> - return __cxl_handle_ras(cxlds, cxlds->regs.ras);
> -}
> -
> void cxl_cor_error_detected(struct pci_dev *pdev)
> {
> struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
> @@ -381,7 +371,7 @@ void cxl_cor_error_detected(struct pci_dev *pdev)
> if (cxlds->rcd)
> cxl_handle_rdport_errors(cxlds);
>
> - cxl_handle_endpoint_cor_ras(cxlds);
> + cxl_handle_cor_ras(cxlds, cxlds->regs.ras);
> }
> }
> EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL");
> @@ -410,7 +400,7 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,
> * chance the situation is recoverable dump the status of the RAS
> * capability registers and bounce the active state of the memdev.
> */
> - ue = cxl_handle_endpoint_ras(cxlds);
> + ue = cxl_handle_ras(cxlds, cxlds->regs.ras);
> }
>
>