[PATCH v11 23/23] CXL/PCI: Disable CXL protocol error interrupts during CXL Port cleanup

Terry Bowman
2025-08-27T01:40:08Z

During CXL device cleanup the CXL PCIe Port device interrupts remain
enabled. This potentially allows unnecessary interrupt processing on
behalf of the CXL errors while the device is destroyed.

Disable CXL protocol errors by setting the CXL devices' AER mask register.

Introduce pci_aer_mask_internal_errors() similar to pci_aer_unmask_internal_errors().

Introduce cxl_mask_proto_interrupts() to call pci_aer_mask_internal_errors().
Add calls to cxl_mask_proto_interrupts() within CXL Port teardown for CXL
Root Ports, CXL Downstream Switch Ports, CXL Upstream Switch Ports, and CXL
Endpoints. Follow the same "bottom-up" approach used during CXL Port
teardown.

Implement cxl_mask_proto_interrupts() in a header file to avoid introducing
Kconfig ifdefs in cxl/core/port.c.

Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>

---
Changes in v10->v11:
- Removed guard() cxl_mask_proto_interrupts(). RP was blocking during
testing. (Terry)
---
drivers/cxl/core/core.h | 2 ++
drivers/cxl/core/port.c | 6 ++++++
drivers/cxl/core/ras.c | 8 ++++++++
drivers/pci/pcie/cxl_aer.c | 21 +++++++++++++++++++++
include/linux/aer.h | 2 ++
5 files changed, 39 insertions(+)

diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h
index 7e66fbb07b8a..385bfd38b778 100644
--- a/drivers/cxl/core/core.h
+++ b/drivers/cxl/core/core.h
@@ -157,6 +157,7 @@ void cxl_cor_error_detected(struct device *dev);
pci_ers_result_t cxl_error_detected(struct device *dev);
void cxl_port_cor_error_detected(struct device *dev);
pci_ers_result_t cxl_port_error_detected(struct device *dev);
+void cxl_mask_proto_interrupts(struct device *dev);
#else
static inline int cxl_ras_init(void)
{
@@ -186,6 +187,7 @@ static inline pci_ers_result_t cxl_port_error_detected(struct device *dev)
{
return PCI_ERS_RESULT_NONE;
}
+static inline void cxl_mask_proto_interrupts(struct device *dev) { }
#endif // CONFIG_CXL_RAS

int cxl_gpf_port_setup(struct cxl_dport *dport);
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 085c8620a797..bb326dc95d5f 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -1428,6 +1428,9 @@ EXPORT_SYMBOL_NS_GPL(cxl_endpoint_autoremove, "CXL");
*/
static void delete_switch_port(struct cxl_port *port)
{
+ cxl_mask_proto_interrupts(port->uport_dev);
+ cxl_mask_proto_interrupts(port->parent_dport->dport_dev);
+
devm_release_action(port->dev.parent, cxl_unlink_parent_dport, port);
devm_release_action(port->dev.parent, cxl_unlink_uport, port);
devm_release_action(port->dev.parent, unregister_port, port);
@@ -1441,6 +1444,7 @@ static void reap_dports(struct cxl_port *port)
device_lock_assert(&port->dev);

xa_for_each(&port->dports, index, dport) {
+ cxl_mask_proto_interrupts(dport->dport_dev);
devm_release_action(&port->dev, cxl_dport_unlink, dport);
devm_release_action(&port->dev, cxl_dport_remove, dport);
devm_kfree(&port->dev, dport);
@@ -1471,6 +1475,8 @@ static void cxl_detach_ep(void *data)
{
struct cxl_memdev *cxlmd = data;

+ cxl_mask_proto_interrupts(cxlmd->cxlds->dev);
+
for (int i = cxlmd->depth - 1; i >= 1; i--) {
struct cxl_port *port, *parent_port;
struct detach_ctx ctx = {
diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c
index 90ea0dfb942f..564144c2d23f 100644
--- a/drivers/cxl/core/ras.c
+++ b/drivers/cxl/core/ras.c
@@ -137,6 +137,14 @@ static void cxl_unmask_proto_interrupts(struct device *dev)
pci_aer_unmask_internal_errors(pdev);
}

+void cxl_mask_proto_interrupts(struct device *dev)
+{
+ struct pci_dev *pdev = to_pci_dev(dev);
+
+ pci_aer_mask_internal_errors(pdev);
+}
+EXPORT_SYMBOL_NS_GPL(cxl_mask_proto_interrupts, "CXL");
+
#ifdef CONFIG_CXL_RCH_RAS
static void cxl_dport_map_rch_aer(struct cxl_dport *dport)
{
diff --git a/drivers/pci/pcie/cxl_aer.c b/drivers/pci/pcie/cxl_aer.c
index 6eeff0b78b47..2de2d9e7934b 100644
--- a/drivers/pci/pcie/cxl_aer.c
+++ b/drivers/pci/pcie/cxl_aer.c
@@ -46,6 +46,27 @@ void pci_aer_unmask_internal_errors(struct pci_dev *dev)
}
EXPORT_SYMBOL_NS_GPL(pci_aer_unmask_internal_errors, "CXL");

+/**
+ * pci_aer_mask_internal_errors - mask internal errors
+ * @dev: pointer to the pcie_dev data structure
+ *
+ * Masks internal errors in the Uncorrectable and Correctable Error
+ * Mask registers.
+ *
+ * Note: AER must be enabled and supported by the device which must be
+ * checked in advance, e.g. with pcie_aer_is_native().
+ */
+void pci_aer_mask_internal_errors(struct pci_dev *dev)
+{
+ int aer = dev->aer_cap;
+
+ pci_clear_and_set_config_dword(dev, aer + PCI_ERR_UNCOR_MASK,
+ 0, PCI_ERR_UNC_INTN);
+ pci_clear_and_set_config_dword(dev, aer + PCI_ERR_COR_MASK,
+ 0, PCI_ERR_COR_INTERNAL);
+}
+EXPORT_SYMBOL_NS_GPL(pci_aer_mask_internal_errors, "CXL");
+
bool cxl_error_is_native(struct pci_dev *dev)
{
struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
diff --git a/include/linux/aer.h b/include/linux/aer.h
index 4e2fc55f2497..82264221ad09 100644
--- a/include/linux/aer.h
+++ b/include/linux/aer.h
@@ -83,12 +83,14 @@ void cxl_register_proto_err_work(struct work_struct *work);
void cxl_unregister_proto_err_work(void);
bool cxl_error_is_native(struct pci_dev *dev);
void pci_aer_unmask_internal_errors(struct pci_dev *dev);
+void pci_aer_mask_internal_errors(struct pci_dev *dev);
#else
static inline int cxl_proto_err_kfifo_get(struct cxl_proto_err_work_data *wd) { return 0; }
static inline void cxl_register_proto_err_work(struct work_struct *work) { }
static inline void cxl_unregister_proto_err_work(void) { }
static inline bool cxl_error_is_native(struct pci_dev *dev) { return false; }
static inline void pci_aer_unmask_internal_errors(struct pci_dev *dev) { }
+static inline void pci_aer_mask_internal_errors(struct pci_dev *dev) { }
#endif

void pci_print_aer(struct pci_dev *dev, int aer_severity,
--
2.51.0.rc2.21.ge5ab6b3e5a