Re: [PATCH v11 08/23] PCI/CXL: Introduce pcie_is_cxl()

Jonathan Cameron
2025-09-10T13:10:49Z

On Tue, 26 Aug 2025 20:35:23 -0500
Terry Bowman <terry.bowman@amd.com> wrote:

> CXL and AER drivers need the ability to identify CXL devices.
>
> Introduce set_pcie_cxl() with logic checking for CXL.mem or CXL.cache
> status in the CXL Flexbus DVSEC status register. The CXL Flexbus DVSEC
> presence is used because it is required for all the CXL PCIe devices.[1]
>
> Add boolean 'struct pci_dev::is_cxl' with the purpose to cache the CXL
> CXL.cache and CXl.mem status.
>
> In the case the device is an EP or USP, call set_pcie_cxl() on behalf of
> the parent downstream device. This will make certain the correct state
> is cached.
>
> Add function pcie_is_cxl() to return 'struct pci_dev::is_cxl'.
>
> [1] CXL 3.1 Spec, 8.1.1 PCIe Designated Vendor-Specific Extended
> Capability (DVSEC) ID Assignment, Table 8-2
>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Reviewed-by: Ira Weiny <ira.weiny@intel.com>
> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Trivial comment inline.

> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index b03244d55aea..252c06402b13 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -1274,6 +1274,9 @@
>
> /* CXL 3.2 8.1.8: PCIe DVSEC for Flex Bus Port */
> #define PCI_DVSEC_CXL_FLEXBUS_PORT 7
> +#define PCI_DVSEC_CXL_FLEXBUS_STATUS_OFFSET 0xE
> +#define PCI_DVSEC_CXL_FLEXBUS_STATUS_CACHE_MASK BIT(0)
> +#define PCI_DVSEC_CXL_FLEXBUS_STATUS_MEM_MASK BIT(2)
>
Whilst there is some logic in using tabs, the existing content
of this file uses spaces between define and name - even when indent is
large enough a tab gives same answer. We should stick to that local style.

> /* CXL 3.2 8.1.9: Register Locator DVSEC */
> #define PCI_DVSEC_CXL_REG_LOCATOR 8