Re: [PATCH v11 10/23] CXL/AER: Update PCI class code check to use FIELD_GET()

Jonathan Cameron
2025-08-29T16:03:25Z

On Tue, 26 Aug 2025 20:35:25 -0500
Terry Bowman <terry.bowman@amd.com> wrote:

> Update the AER driver's is_cxl_mem_dev() to use FIELD_GET() while checking
> for a CXL Endpoint class code.
>
> Introduce a genmask bitmask for checking PCI class codes and locate in
> include/uapi/linux/pci_regs.h.
>
> Update the function documentation to reference the latest CXL
> specification.
>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>

In general I like this change, but maybe we should make a broader use of
it even in this introductory patch. E.g. use FIELD_PREP()
in cxl_mem_pci_tbl() and perhaps add a define for the mask
of the programming interface as well?

Maybe use it in pci_ids.h (which raises the question of whether
it's in the right place) for PCI_CLASS_BRIDGE_PCI_NORMAL / SUBTRACTIVE
and the various USB definitions that include the programming interface.

Perhaps wider use is something for a follow up, but nice to at least
use it everywhere relevant in the CXL code to make the justification stronger
from the start.

>
> ---
> Changes in v10->v11:
> - Add #include <linux/bitfield.h> to cxl_ras.c

I think you missed and hit wrong file!

> - Removed line wrapping at "(CXL 3.2, 8.1.12.1)".
> ---
> drivers/pci/pcie/aer.c | 1 +
> drivers/pci/pcie/rch_aer.c | 6 +++---
> include/uapi/linux/pci_regs.h | 2 ++
> 3 files changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
> index 1b5f5b0cdc4f..ed1de9256898 100644
> --- a/drivers/pci/pcie/aer.c
> +++ b/drivers/pci/pcie/aer.c
> @@ -30,6 +30,7 @@
> #include <linux/kfifo.h>
> #include <linux/ratelimit.h>
> #include <linux/slab.h>
> +#include <linux/bitfield.h>

This seems unrelated as no use of new stuff in here.
Also, looks from what I can see here to be alphabetical order.

> #include <acpi/apei.h>
> #include <acpi/ghes.h>
> #include <ras/ras_event.h>
> diff --git a/drivers/pci/pcie/rch_aer.c b/drivers/pci/pcie/rch_aer.c
> index bfe071eebf67..c3e2d4cbe8cc 100644
> --- a/drivers/pci/pcie/rch_aer.c
> +++ b/drivers/pci/pcie/rch_aer.c
> @@ -17,10 +17,10 @@ static bool is_cxl_mem_dev(struct pci_dev *dev)
> return false;
>
> /*
> - * CXL Memory Devices must have the 502h class code set (CXL
> - * 3.0, 8.1.12.1).
> + * CXL Memory Devices must have the 502h class code set
> + * (CXL 3.2, 8.1.12.1).
> */
> - if ((dev->class >> 8) != PCI_CLASS_MEMORY_CXL)
> + if (FIELD_GET(PCI_CLASS_CODE_MASK, dev->class) != PCI_CLASS_MEMORY_CXL)
> return false;
>
> return true;
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index 252c06402b13..c7b635f6cf36 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -73,6 +73,8 @@
> #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
> #define PCI_CLASS_DEVICE 0x0a /* Device class */
>
> +#define PCI_CLASS_CODE_MASK __GENMASK(23, 8)
> +
> #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
> #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
> #define PCI_HEADER_TYPE 0x0e /* 8 bits */