From: Jonathan Cameron <jonathan.cameron@huawei.com>
To: Terry Bowman <terry.bowman@amd.com>
Cc: <dave@stgolabs.net>, <dave.jiang@intel.com>,
<alison.schofield@intel.com>, <dan.j.williams@intel.com>,
<bhelgaas@google.com>, <shiju.jose@huawei.com>,
<ming.li@zohomail.com>, <Smita.KoralahalliChannabasappa@amd.com>,
<rrichter@amd.com>, <dan.carpenter@linaro.org>,
<PradeepVineshReddy.Kodamati@amd.com>, <lukas@wunner.de>,
<Benjamin.Cheatham@amd.com>,
<sathyanarayanan.kuppuswamy@linux.intel.com>,
<linux-cxl@vger.kernel.org>, <alucerop@amd.com>,
<ira.weiny@intel.com>, <linux-kernel@vger.kernel.org>,
<linux-pci@vger.kernel.org>
Subject: Re: [PATCH v11 18/23] PCI/AER: Dequeue forwarded CXL error
Date: Wed, 10 Sep 2025 14:29:06 +0100 [thread overview]
Message-ID: <20250910142906.000079d6@huawei.com> (raw)
In-Reply-To: <20250827013539.903682-19-terry.bowman@amd.com>
On Tue, 26 Aug 2025 20:35:33 -0500
Terry Bowman <terry.bowman@amd.com> wrote:
> The AER driver is now designed to forward CXL protocol errors to the CXL
> driver. Update the CXL driver with functionality to dequeue the forwarded
> CXL error from the kfifo. Also, update the CXL driver to begin the protocol
> error handling processing using the work received from the FIFO.
>
> Update function cxl_proto_err_work_fn() to dequeue work forwarded by the
> AER service driver. This will begin the CXL protocol error processing with
> a call to cxl_handle_proto_error().
>
> Introduce logic to take the SBDF values from 'struct cxl_proto_error_info'
> and use in discovering the erring PCI device. The call to pci_get_domain_bus_and_slot()
> will return a reference counted 'struct pci_dev *'. This will serve as
> reference count to prevent releasing the CXL Endpoint's mapped RAS while
> handling the error. Use scope base __free() to put the reference count.
> This will change when adding support for CXL port devices in the future.
>
> Implement cxl_handle_proto_error() to differentiate between Restricted CXL
> Host (RCH) protocol errors and CXL virtual host (VH) protocol errors.
> Maintain the existing RCH handling. Export the AER driver's pcie_walk_rcec()
> allowing the CXL driver to walk the RCEC's secondary bus.
>
> VH correctable error (CE) processing will call the CXL CE handler. VH
> uncorrectable errors (UCE) will call cxl_do_recovery(), implemented as a
> stub for now and to be updated in future patch. Export pci_aer_clean_fatal_status()
> and pci_clean_device_status() used to clean up AER status after handling.
>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
One additional comment.
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index d775ed37a79b..2c9827690cb3 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -2328,6 +2328,7 @@ void pcie_clear_device_status(struct pci_dev *dev)
> pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta);
> pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta);
> }
> +EXPORT_SYMBOL_NS_GPL(pcie_clear_device_status, "CXL");
Not seeing this as CXL specific. I don't think the namespace is appropriate.
> #endif
next prev parent reply other threads:[~2025-09-10 13:29 UTC|newest]
Thread overview: 89+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-27 1:35 [PATCH v11 00/23] Enable CXL PCIe Port Protocol Error handling and logging Terry Bowman
2025-08-27 1:35 ` [PATCH v11 01/23] cxl: Remove ifdef blocks of CONFIG_PCIEAER_CXL from core/pci.c Terry Bowman
2025-08-27 1:35 ` [PATCH v11 02/23] CXL/AER: Remove CONFIG_PCIEAER_CXL and replace with CONFIG_CXL_RAS Terry Bowman
2025-08-29 15:24 ` Jonathan Cameron
2025-08-29 18:16 ` Sathyanarayanan Kuppuswamy
2025-08-27 1:35 ` [PATCH v11 03/23] cxl/pci: Remove unnecessary CXL Endpoint handling helper functions Terry Bowman
2025-08-28 15:28 ` Dave Jiang
2025-08-27 1:35 ` [PATCH v11 04/23] cxl/pci: Remove unnecessary CXL RCH " Terry Bowman
2025-08-28 8:35 ` Alejandro Lucero Palau
2025-08-28 17:32 ` Dave Jiang
2025-08-27 1:35 ` [PATCH v11 05/23] cxl: Move CXL driver RCH error handling into CONFIG_CXL_RCH_RAS conditional block Terry Bowman
2025-08-28 8:57 ` Alejandro Lucero Palau
2025-09-10 16:43 ` Bowman, Terry
2025-08-29 15:33 ` Jonathan Cameron
2025-09-11 17:48 ` Bowman, Terry
2025-09-11 19:41 ` Dave Jiang
2025-09-15 13:32 ` Bowman, Terry
2025-08-27 1:35 ` [PATCH v11 06/23] CXL/AER: Introduce rch_aer.c into AER driver for handling CXL RCH errors Terry Bowman
2025-08-28 20:53 ` Dave Jiang
2025-08-29 8:39 ` Lukas Wunner
2025-09-10 17:01 ` Bowman, Terry
2025-09-10 17:26 ` Dave Jiang
2025-09-12 13:59 ` Bowman, Terry
2025-09-12 19:09 ` Lukas Wunner
2025-09-10 16:56 ` Bowman, Terry
2025-09-10 12:43 ` Jonathan Cameron
2025-08-27 1:35 ` [PATCH v11 07/23] CXL/PCI: Move CXL DVSEC definitions into uapi/linux/pci_regs.h Terry Bowman
2025-08-27 14:51 ` Lukas Wunner
2025-08-29 15:42 ` Jonathan Cameron
2025-08-29 15:47 ` Jonathan Cameron
2025-08-28 21:07 ` Dave Jiang
2025-09-10 18:11 ` Bowman, Terry
2025-09-10 20:06 ` Dave Jiang
2025-08-27 1:35 ` [PATCH v11 08/23] PCI/CXL: Introduce pcie_is_cxl() Terry Bowman
2025-08-28 8:18 ` Alejandro Lucero Palau
2025-09-10 16:24 ` Bowman, Terry
2025-09-11 3:48 ` Lukas Wunner
2025-09-10 13:10 ` Jonathan Cameron
2025-08-27 1:35 ` [PATCH v11 09/23] PCI/AER: Report CXL or PCIe bus error type in trace logging Terry Bowman
2025-08-27 7:37 ` Lukas Wunner
2025-09-10 15:26 ` Bowman, Terry
2025-09-10 15:33 ` Lukas Wunner
2025-09-11 5:07 ` Lukas Wunner
2025-08-27 1:35 ` [PATCH v11 10/23] CXL/AER: Update PCI class code check to use FIELD_GET() Terry Bowman
2025-08-29 16:03 ` Jonathan Cameron
2025-09-11 18:18 ` Bowman, Terry
2025-08-27 1:35 ` [PATCH v11 11/23] cxl/pci: Update RAS handler interfaces to also support CXL Ports Terry Bowman
2025-08-27 1:35 ` [PATCH v11 12/23] cxl/pci: Log message if RAS registers are unmapped Terry Bowman
2025-08-27 1:35 ` [PATCH v11 13/23] cxl/pci: Unify CXL trace logging for CXL Endpoints and CXL Ports Terry Bowman
2025-08-27 11:55 ` Shiju Jose
2025-08-29 16:06 ` Jonathan Cameron
2025-08-27 1:35 ` [PATCH v11 14/23] cxl/pci: Update cxl_handle_cor_ras() to return early if no RAS errors Terry Bowman
2025-08-27 1:35 ` [PATCH v11 15/23] cxl/pci: Map CXL Endpoint Port and CXL Switch Port RAS registers Terry Bowman
2025-08-28 23:05 ` Dave Jiang
2025-09-10 18:40 ` Bowman, Terry
2025-08-27 1:35 ` [PATCH v11 16/23] cxl/pci: Introduce CXL Endpoint protocol error handlers Terry Bowman
2025-08-27 7:48 ` Lukas Wunner
2025-09-10 13:23 ` Jonathan Cameron
2025-08-27 1:35 ` [PATCH v11 17/23] CXL/AER: Introduce cxl_aer.c into AER driver for forwarding CXL errors Terry Bowman
2025-08-27 7:56 ` Lukas Wunner
2025-08-27 1:35 ` [PATCH v11 18/23] PCI/AER: Dequeue forwarded CXL error Terry Bowman
2025-08-29 0:43 ` Dave Jiang
2025-08-29 7:10 ` Lukas Wunner
2025-09-16 15:18 ` Bowman, Terry
2025-09-11 14:33 ` Bowman, Terry
2025-09-11 15:41 ` Dave Jiang
2025-09-11 16:47 ` Bowman, Terry
2025-09-11 19:45 ` Dave Jiang
2025-09-10 13:29 ` Jonathan Cameron [this message]
2025-08-27 1:35 ` [PATCH v11 19/23] CXL/PCI: Introduce CXL Port protocol error handlers Terry Bowman
2025-08-30 0:17 ` Dave Jiang
2025-08-27 1:35 ` [PATCH v11 20/23] CXL/PCI: Export and rename merge_result() to pci_ers_merge_result() Terry Bowman
2025-08-27 8:04 ` Lukas Wunner
2025-09-10 15:57 ` Bowman, Terry
2025-09-11 3:44 ` Lukas Wunner
2025-08-27 12:19 ` kernel test robot
2025-08-27 1:35 ` [PATCH v11 21/23] CXL/PCI: Introduce CXL uncorrectable protocol error recovery Terry Bowman
2025-09-03 22:30 ` Dave Jiang
2025-09-11 19:19 ` Bowman, Terry
2025-09-11 19:48 ` Dave Jiang
2025-09-10 13:33 ` Jonathan Cameron
2025-08-27 1:35 ` [PATCH v11 22/23] CXL/PCI: Enable CXL protocol errors during CXL Port probe Terry Bowman
2025-09-03 23:23 ` Dave Jiang
2025-08-27 1:35 ` [PATCH v11 23/23] CXL/PCI: Disable CXL protocol error interrupts during CXL Port cleanup Terry Bowman
2025-09-10 15:07 ` Gregory Price
2025-09-11 20:19 ` Bowman, Terry
2025-08-29 0:07 ` [PATCH v11 00/23] Enable CXL PCIe Port Protocol Error handling and logging Dave Jiang
2025-09-23 3:29 ` Gregory Price
2025-09-23 9:21 ` Srinivasulu Thanneeru
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