Re: [PATCH 2/2] dmaengine: dw-edma: Add non-LL mode

[Bjorn Helgaas <helgaas@kernel.org>]

On Thu, Sep 11, 2025 at 11:42:31AM +0000, Verma, Devendra wrote:
> > -----Original Message-----
> > From: Bjorn Helgaas <helgaas@kernel.org>

> > On Wed, Sep 10, 2025 at 12:30:39PM +0000, Verma, Devendra wrote:
> > > > From: Bjorn Helgaas <helgaas@kernel.org>
> >
> > [redundant headers removed]
> >
> > > > On Fri, Sep 05, 2025 at 03:46:59PM +0530, Devendra K Verma wrote:
> > > > > AMD MDB IP supports Linked List (LL) mode as well as non-LL mode.
> > > > > The current code does not have the mechanisms to enable the DMA
> > > > > transactions using the non-LL mode. The following two cases are
> > > > > added with this patch:
> >
> > > > > +static u64 dw_edma_get_phys_addr(struct pci_dev *pdev,
> > > > > +                              struct dw_edma_pcie_data *pdata,
> > > > > +                              enum pci_barno bar) {
> > > > > +     if (pdev->vendor == PCI_VENDOR_ID_XILINX)
> > > > > +             return pdata->phys_addr;
> > > > > +     return pci_bus_address(pdev, bar);
> > > >
> > > > This doesn't seem right.  pci_bus_address() returns pci_bus_addr_t,
> > > > so pdata->phys_addr should also be a pci_bus_addr_t, and the
> > > > function should return pci_bus_addr_t.
> > > >
> > > > A pci_bus_addr_t is not a "phys_addr"; it is an address that is
> > > > valid on the PCI side of a PCI host bridge, which may be different
> > > > than the CPU physical address on the CPU side of the bridge because
> > > > of things like IOMMUs.
> > > >
> > > > Seems like the struct dw_edma_region.paddr should be renamed to
> > > > something like "bus_addr" and made into a pci_bus_addr_t.
> > >
> > > In case of AMD, it is not an address that is accessible from host via
> > > PCI, it is the device side DDR offset of physical address which is not
> > > known to host,that is why the VSEC capability is used to let know host
> > > of the DDR offset to correctly programming the LLP of DMA controller.
> > > Without programming the LLP controller will not know from where to
> > > start reading the LL for DMA processing. DMA controller requires the
> > > physical address of LL present on its side of DDR.
> >
> > I guess "device side DDR offset" means this Xilinx device has some
> > DDR internal to the PCI device, and the CPU cannot access it via a
> > BAR?
> 
> The host can access the DDR internal to the PCI device via BAR, but
> it involves an iATU translation. The host can use the virtual /
> physical address to access that DDR.  The issue is not with the host
> rather DMA controller which does not understand the physical address
> provided by the host, eg, the address returned by pci_bus_addr(pdev,
> barno).

Does this mean dw_edma_get_phys_addr() depends on iATU programming
done by the PCI controller driver?  Is it possible for that driver to
change the iATU programming after dw_edma_get_phys_addr() in a way
that breaks this?

Bjorn