Re: [PATCH 2/7] clk: samsung: Add clock PLL support for ARTPEC-9 SoC

[kernel test robot <lkp@intel.com>]

Hi Ravi,

kernel test robot noticed the following build errors:

[auto build test ERROR on krzk/for-next]
[also build test ERROR on clk/clk-next next-20250917]
[cannot apply to robh/for-next linus/master v6.17-rc6]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Ravi-Patel/dt-bindings-clock-Add-ARTPEC-9-clock-controller/20250917-165346
base:   https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git for-next
patch link:    https://lore.kernel.org/r/20250917085005.89819-3-ravi.patel%40samsung.com
patch subject: [PATCH 2/7] clk: samsung: Add clock PLL support for ARTPEC-9 SoC
config: arm-s5pv210_defconfig (https://download.01.org/0day-ci/archive/20250918/202509181955.NgLJ2aBv-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 15.1.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250918/202509181955.NgLJ2aBv-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202509181955.NgLJ2aBv-lkp@intel.com/

All errors (new ones prefixed by >>):

   arm-linux-gnueabi-ld: drivers/clk/samsung/clk-pll.o: in function `samsung_a9fraco_recalc_rate':
>> drivers/clk/samsung/clk-pll.c:1508:(.text+0xcc): undefined reference to `__aeabi_uldivmod'


vim +1508 drivers/clk/samsung/clk-pll.c

  1490	
  1491	static unsigned long samsung_a9fraco_recalc_rate(struct clk_hw *hw,
  1492							 unsigned long parent_rate)
  1493	{
  1494		struct samsung_clk_pll *pll = to_clk_pll(hw);
  1495		u32 pll_con0, pll_con5;
  1496		u64 mdiv, pdiv, sdiv, kdiv;
  1497		u64 fvco = parent_rate;
  1498	
  1499		pll_con0 = readl_relaxed(pll->con_reg);
  1500		pll_con5 = readl_relaxed(pll->con_reg + PLLA9FRACO_PLL_CON5_DIV_FRAC);
  1501		mdiv = (pll_con0 >> PLLA9FRACO_MDIV_SHIFT) & PLLA9FRACO_MDIV_MASK;
  1502		pdiv = (pll_con0 >> PLLA9FRACO_PDIV_SHIFT) & PLLA9FRACO_PDIV_MASK;
  1503		sdiv = (pll_con0 >> PLLA9FRACO_SDIV_SHIFT) & PLLA9FRACO_SDIV_MASK;
  1504		kdiv = (pll_con5 & PLLA9FRACO_KDIV_MASK);
  1505	
  1506		/* fvco = fref * (M + K/2^24) / p * (S+1) */
  1507		fvco *= mdiv;
> 1508		fvco = ((fvco << 24) + kdiv) / ((pdiv * (sdiv + 1)) << 24);
  1509	
  1510		return (unsigned long)fvco;
  1511	}
  1512	

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