From: "Chang S. Bae" <chang.seok.bae@intel.com>
To: linux-kernel@vger.kernel.org
Cc: x86@kernel.org, tglx@linutronix.de, mingo@redhat.com,
bp@alien8.de, dave.hansen@linux.intel.com, chao.gao@intel.com,
abusse@amazon.de, tony.luck@intel.com, chang.seok.bae@intel.com
Subject: [PATCH v6 1/7] x86/cpu/topology: Make primary thread mask available with SMP=n
Date: Sun, 21 Sep 2025 15:48:35 -0700 [thread overview]
Message-ID: <20250921224841.3545-2-chang.seok.bae@intel.com> (raw)
In-Reply-To: <20250921224841.3545-1-chang.seok.bae@intel.com>
cpu_primary_thread_mask is only defined when CONFIG_SMP=y. However, even
in UP kernels there is always exactly one CPU, which can reasonably be
treated as the primary thread.
Historically, topology_is_primary_thread() always returned true with
CONFIG_SMP=n. A recent commit:
4b455f59945aa ("cpu/SMT: Provide a default topology_is_primary_thread()")
replaced it with a generic implementation with the note:
"When disabling SMT, the primary thread of the SMT will remain
enabled/active. Architectures that have a special primary thread (e.g.
x86) need to override this function. ..."
For consistency and clarity, make the primary thread mask available
regardless of SMP, similar to cpu_possible_mask and cpu_present_mask.
Move __cpu_primary_thread_mask into common code to prevent build issues.
Let cpu_mark_primary_thread() configure the mask even for UP kernels,
alongside other masks. Then, topology_is_primary_thread() can
consistently reference it.
Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
---
V5 -> V6: Collect Tony's review tag
V4 -> V5: New patch
Preparatory patch to set up the mask correctly before its new use in
patch3.
---
arch/x86/include/asm/topology.h | 12 ++++++------
arch/x86/kernel/cpu/topology.c | 4 ----
arch/x86/kernel/cpu/topology_common.c | 3 +++
arch/x86/kernel/smpboot.c | 3 ---
4 files changed, 9 insertions(+), 13 deletions(-)
diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h
index 6c79ee7c0957..281252af6e9d 100644
--- a/arch/x86/include/asm/topology.h
+++ b/arch/x86/include/asm/topology.h
@@ -218,6 +218,12 @@ static inline unsigned int topology_amd_nodes_per_pkg(void)
return __amd_nodes_per_pkg;
}
+#else /* CONFIG_SMP */
+static inline int topology_phys_to_logical_pkg(unsigned int pkg) { return 0; }
+static inline int topology_max_smt_threads(void) { return 1; }
+static inline unsigned int topology_amd_nodes_per_pkg(void) { return 1; }
+#endif /* !CONFIG_SMP */
+
extern struct cpumask __cpu_primary_thread_mask;
#define cpu_primary_thread_mask ((const struct cpumask *)&__cpu_primary_thread_mask)
@@ -231,12 +237,6 @@ static inline bool topology_is_primary_thread(unsigned int cpu)
}
#define topology_is_primary_thread topology_is_primary_thread
-#else /* CONFIG_SMP */
-static inline int topology_phys_to_logical_pkg(unsigned int pkg) { return 0; }
-static inline int topology_max_smt_threads(void) { return 1; }
-static inline unsigned int topology_amd_nodes_per_pkg(void) { return 1; }
-#endif /* !CONFIG_SMP */
-
static inline void arch_fix_phys_package_id(int num, u32 slot)
{
}
diff --git a/arch/x86/kernel/cpu/topology.c b/arch/x86/kernel/cpu/topology.c
index e35ccdc84910..f083023f7dd9 100644
--- a/arch/x86/kernel/cpu/topology.c
+++ b/arch/x86/kernel/cpu/topology.c
@@ -75,15 +75,11 @@ bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
return phys_id == (u64)cpuid_to_apicid[cpu];
}
-#ifdef CONFIG_SMP
static void cpu_mark_primary_thread(unsigned int cpu, unsigned int apicid)
{
if (!(apicid & (__max_threads_per_core - 1)))
cpumask_set_cpu(cpu, &__cpu_primary_thread_mask);
}
-#else
-static inline void cpu_mark_primary_thread(unsigned int cpu, unsigned int apicid) { }
-#endif
/*
* Convert the APIC ID to a domain level ID by masking out the low bits
diff --git a/arch/x86/kernel/cpu/topology_common.c b/arch/x86/kernel/cpu/topology_common.c
index b5a5e1411469..71625795d711 100644
--- a/arch/x86/kernel/cpu/topology_common.c
+++ b/arch/x86/kernel/cpu/topology_common.c
@@ -16,6 +16,9 @@ EXPORT_SYMBOL_GPL(x86_topo_system);
unsigned int __amd_nodes_per_pkg __ro_after_init;
EXPORT_SYMBOL_GPL(__amd_nodes_per_pkg);
+/* CPUs which are the primary SMT threads */
+struct cpumask __cpu_primary_thread_mask __read_mostly;
+
void topology_set_dom(struct topo_scan *tscan, enum x86_topology_domains dom,
unsigned int shift, unsigned int ncpus)
{
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index eb289abece23..6b43417bf270 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -103,9 +103,6 @@ EXPORT_PER_CPU_SYMBOL(cpu_core_map);
DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map);
EXPORT_PER_CPU_SYMBOL(cpu_die_map);
-/* CPUs which are the primary SMT threads */
-struct cpumask __cpu_primary_thread_mask __read_mostly;
-
/* Representing CPUs for which sibling maps can be computed */
static cpumask_var_t cpu_sibling_setup_mask;
--
2.48.1
next prev parent reply other threads:[~2025-09-21 22:48 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-21 22:48 [PATCH v6 0/7] x86: Support for Intel Microcode Staging Feature Chang S. Bae
2025-09-21 22:48 ` Chang S. Bae [this message]
2025-10-15 16:52 ` [tip: x86/microcode] x86/cpu/topology: Make primary thread mask available with SMP=n tip-bot2 for Chang S. Bae
2025-09-21 22:48 ` [PATCH v6 2/7] x86/microcode: Introduce staging step to reduce late-loading time Chang S. Bae
2025-10-15 16:52 ` [tip: x86/microcode] " tip-bot2 for Chang S. Bae
2025-09-21 22:48 ` [PATCH v6 3/7] x86/microcode/intel: Establish staging control logic Chang S. Bae
2025-10-13 13:42 ` Borislav Petkov
2025-10-13 21:16 ` Chang S. Bae
2025-10-15 16:52 ` [tip: x86/microcode] " tip-bot2 for Chang S. Bae
2025-09-21 22:48 ` [PATCH v6 4/7] x86/microcode/intel: Define staging state struct Chang S. Bae
2025-10-15 16:52 ` [tip: x86/microcode] " tip-bot2 for Chang S. Bae
2025-09-21 22:48 ` [PATCH v6 5/7] x86/microcode/intel: Implement staging handler Chang S. Bae
2025-10-15 16:52 ` [tip: x86/microcode] " tip-bot2 for Chang S. Bae
2025-09-21 22:48 ` [PATCH v6 6/7] x86/microcode/intel: Support mailbox transfer Chang S. Bae
2025-10-15 16:52 ` [tip: x86/microcode] " tip-bot2 for Chang S. Bae
2025-09-21 22:48 ` [PATCH v6 7/7] x86/microcode/intel: Enable staging when available Chang S. Bae
2025-10-15 16:52 ` [tip: x86/microcode] " tip-bot2 for Chang S. Bae
2025-09-22 13:09 ` [PATCH v6 0/7] x86: Support for Intel Microcode Staging Feature Borislav Petkov
2025-09-22 19:53 ` Chang S. Bae
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