From: Priscilla Lam <prl@amazon.com>
To: <maz@kernel.org>
Cc: <christoffer.dall@arm.com>, <dwmw@amazon.co.uk>,
<graf@amazon.com>, <gurugubs@amazon.com>, <jgrall@amazon.co.uk>,
<joey.gouly@arm.com>, <kvmarm@lists.linux.dev>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <oliver.upton@linux.dev>,
<prl@amazon.com>, <suzuki.poulose@arm.com>,
<yuzenghui@huawei.com>
Subject: Re: [PATCH] KVM: arm64: Implement KVM_TRANSLATE ioctl for arm64
Date: Wed, 24 Sep 2025 22:21:08 -0700 [thread overview]
Message-ID: <20250925052108.27351-1-prl@amazon.com> (raw)
In-Reply-To: 86ecrx1px2.wl-maz@kernel.org
On 9/23/25, 2:26 AM, "Marc Zyngier" <maz@kernel.org> wrote:
> A guest doing this is a sure indication that it is completely broken,
> and will fail on actual HW, because it clearly ignores small
> insignificant details such as *ordering*.
>
> My other question still remains: why can't you perform this page table
> walk in userspace? It is actually much safer to do so because you can
> stop other vcpus while inspecting the PTs, and avoid a vcpu playing
> tricks behind your back -- something the in-kernel PTW doesn't try to
> avoid.
In our case, this comes from the Windows TPM driver using ldp32 to read
static adjacent CRB fields where ordering doesn't matter, but I agree
that a guest relying on this kind of translation is problematic. We'll
drop this KVM_TRANSLATE implementation and pursue a different approach
instead.
Thanks,
Priscilla
prev parent reply other threads:[~2025-09-25 5:21 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-22 20:24 [PATCH] KVM: arm64: Implement KVM_TRANSLATE ioctl for arm64 Priscilla Lam
2025-09-22 23:27 ` Oliver Upton
2025-09-23 8:03 ` Marc Zyngier
2025-09-23 8:29 ` Priscilla Lam
2025-09-23 8:39 ` Alexander Graf
2025-09-23 9:02 ` David Woodhouse
2025-09-23 18:05 ` Christoffer Dall
2025-09-23 9:25 ` Marc Zyngier
2025-09-25 5:21 ` Priscilla Lam [this message]
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