Re: [RFC 3/5] pinctrl: add polarfire soc iomux0 pinmux driver

Linus Walleij
2025-10-13T11:02:49Z

On Wed, Oct 1, 2025 at 5:45 PM Conor Dooley <conor@kernel.org> wrote:

> They're not actually package pins at all that are being configured here,
> it's internal routing inside the FPGA. It does operate on a function
> level, but I don't think there's a neat mapping to the pinctrl subsystem
> which (AFAIU) considers functions to contain groups, which in turn
> contain pins. I suppose it could be thought of that, for example, spi0
> is actually a function containing 4 (or 5, don't ask - or do if you want
> to read a rant about pointlessly confusing design) "pins" in 1 group.
>
> If I could just work in terms of functions only, and avoid groups or
> pins at all, feels (to me ofc) like it'd maybe match the purpose of this
> aspect of the hardware better.

What I would ask myself is whether the abstraction fits the bill,
like if there is a natural set of functions in the silicon, then the code
should reflect that.

When it comes to those:

+static const struct pinctrl_pin_desc mpfs_iomux0_pinctrl_pins[] = {
+ PINCTRL_PIN(0, "spi0"),
+ PINCTRL_PIN(1, "spi1"),

At least be careful with the nouns used: are they really "pins"?
Should they be described as "pins"?

Maybe it is best to come up with some custom struct if not?

Yours,
Linus Walleij