* [PATCH v3 phy 00/17] Lynx 28G improvements part 1
@ 2025-09-26 18:04 Vladimir Oltean
2025-09-26 18:04 ` [PATCH v3 phy 01/17] phy: lynx-28g: remove LYNX_28G_ prefix from register names Vladimir Oltean
` (16 more replies)
0 siblings, 17 replies; 26+ messages in thread
From: Vladimir Oltean @ 2025-09-26 18:04 UTC (permalink / raw)
To: linux-phy
Cc: Ioana Ciornei, Vinod Koul, Kishon Vijay Abraham I, Josua Mayer,
linux-kernel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
devicetree
This is the first part in upstreaming a set of around 100 patches that
were developed in NXP's vendor Linux Factory kernel over the course of
several years.
This part is mainly concerned with correcting some historical mistakes
which make extending the driver more difficult:
- the register naming scheme forces us to modify a single register field
per lynx_28g_lane_rmw() call - leads to inefficient code
- lynx_28g_lane_set_sgmii(), lynx_28g_lane_set_10gbaser() are unfit for
their required roles when the current SerDes protocol is 25GBase-R.
They are replaced with a better structured approach.
- USXGMII and 10GBase-R have different protocol converters, and should
be treated separately by the SerDes driver.
- Lane power management does not really power down the lanes.
- Consumer drivers using phy_exit() would cause the kernel to hang.
- The 3 instances of this SerDes block, as seen on NXP LX2160A, need to
be differentiated somehow, because otherwise, the driver cannot reject
a configuration which is unsupported by the hardware. The proposal is
to do that based on compatible string.
In addition to the above, a new feature is also added in patch 14/17:
25GBase-R. Code allowing this mode to be used is also necessary in the
Ethernet MAC and PCS drivers - not present here.
The set grew in size (sorry!) from v1 here:
https://lore.kernel.org/lkml/20250904154402.300032-1-vladimir.oltean@nxp.com/
due to Josua's request for a device tree binding where individual lanes
have their own OF nodes. This seems to be the right moment to make that
change.
It also grew in size from v2 due to Josua's request to avoid unbounded
loops waiting for lane resets/halts/stops to complete:
https://lore.kernel.org/lkml/d0c8bbf8-a0c5-469f-a148-de2235948c0f@solid-run.com/
Detailed change log in individual patches. Thanks to Josua, Rob, Conor,
Krzysztof, Ioana who provided feedback on the previous version, and I
hope it has all been addressed.
Cc: Rob Herring <robh@kernel.org>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Ioana Ciornei (2):
phy: lynx-28g: configure more equalization params for 1GbE and 10GbE
phy: lynx-28g: add support for 25GBASER
Vladimir Oltean (15):
phy: lynx-28g: remove LYNX_28G_ prefix from register names
phy: lynx-28g: don't concatenate lynx_28g_lane_rmw() argument "reg"
with "val" and "mask"
phy: lynx-28g: use FIELD_GET() and FIELD_PREP()
phy: lynx-28g: convert iowrite32() calls with magic values to macros
phy: lynx-28g: restructure protocol configuration register accesses
phy: lynx-28g: make lynx_28g_set_lane_mode() more systematic
phy: lynx-28g: refactor lane->interface to lane->mode
phy: lynx-28g: distinguish between 10GBASE-R and USXGMII
phy: lynx-28g: use "dev" argument more in lynx_28g_probe()
phy: lynx-28g: improve lynx_28g_probe() sequence
dt-bindings: phy: lynx-28g: add compatible strings per SerDes and
instantiation
phy: lynx-28g: probe on per-SoC and per-instance compatible strings
phy: lynx-28g: use timeouts when waiting for lane halt and reset
phy: lynx-28g: truly power the lanes up or down
phy: lynx-28g: implement phy_exit() operation
.../devicetree/bindings/phy/fsl,lynx-28g.yaml | 159 +-
drivers/phy/freescale/phy-fsl-lynx-28g.c | 1505 +++++++++++++----
2 files changed, 1366 insertions(+), 298 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v3 phy 01/17] phy: lynx-28g: remove LYNX_28G_ prefix from register names
2025-09-26 18:04 [PATCH v3 phy 00/17] Lynx 28G improvements part 1 Vladimir Oltean
@ 2025-09-26 18:04 ` Vladimir Oltean
2025-09-26 18:04 ` [PATCH v3 phy 02/17] phy: lynx-28g: don't concatenate lynx_28g_lane_rmw() argument "reg" with "val" and "mask" Vladimir Oltean
` (15 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Vladimir Oltean @ 2025-09-26 18:04 UTC (permalink / raw)
To: linux-phy
Cc: Ioana Ciornei, Vinod Koul, Kishon Vijay Abraham I, Josua Mayer,
linux-kernel
Currently, in macros such as lynx_28g_lane_rmw(), the driver has
macros which concatenate the LYNX_28G_ prefix with the "val" and "mask"
arguments. This is done to shorten function calls and not have to spell
out LYNX_28G_ everywhere.
But outside of lynx_28g_lane_rmw(), lynx_28g_lane_read() and
lynx_28g_pll_read(), this is not done, leading to an inconsistency in
the code.
Also, the concatenation itself has the disadvantage that searching the
arguments of these functions as full words (like N_RATE_QUARTER) leads
us nowhere, since the real macro definition is LNaTGCR0_N_RATE_QUARTER.
Some maintainers want register definitions in drivers to contain the
driver name as a prefix, but here, this has the disadvantages listed
above, so just remove that prefix.
The only change made here is the removal of LYNX_28G_.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
v1->v3: none
drivers/phy/freescale/phy-fsl-lynx-28g.c | 248 +++++++++++------------
1 file changed, 124 insertions(+), 124 deletions(-)
diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
index c20d2636c5e9..4e8d2c56d702 100644
--- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
+++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
@@ -12,99 +12,99 @@
#define LYNX_28G_NUM_PLL 2
/* General registers per SerDes block */
-#define LYNX_28G_PCC8 0x10a0
-#define LYNX_28G_PCC8_SGMII 0x1
-#define LYNX_28G_PCC8_SGMII_DIS 0x0
+#define PCC8 0x10a0
+#define PCC8_SGMII 0x1
+#define PCC8_SGMII_DIS 0x0
-#define LYNX_28G_PCCC 0x10b0
-#define LYNX_28G_PCCC_10GBASER 0x9
-#define LYNX_28G_PCCC_USXGMII 0x1
-#define LYNX_28G_PCCC_SXGMII_DIS 0x0
+#define PCCC 0x10b0
+#define PCCC_10GBASER 0x9
+#define PCCC_USXGMII 0x1
+#define PCCC_SXGMII_DIS 0x0
-#define LYNX_28G_LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1))
+#define LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1))
/* Per PLL registers */
-#define LYNX_28G_PLLnRSTCTL(pll) (0x400 + (pll) * 0x100 + 0x0)
-#define LYNX_28G_PLLnRSTCTL_DIS(rstctl) (((rstctl) & BIT(24)) >> 24)
-#define LYNX_28G_PLLnRSTCTL_LOCK(rstctl) (((rstctl) & BIT(23)) >> 23)
-
-#define LYNX_28G_PLLnCR0(pll) (0x400 + (pll) * 0x100 + 0x4)
-#define LYNX_28G_PLLnCR0_REFCLK_SEL(cr0) (((cr0) & GENMASK(20, 16)))
-#define LYNX_28G_PLLnCR0_REFCLK_SEL_100MHZ 0x0
-#define LYNX_28G_PLLnCR0_REFCLK_SEL_125MHZ 0x10000
-#define LYNX_28G_PLLnCR0_REFCLK_SEL_156MHZ 0x20000
-#define LYNX_28G_PLLnCR0_REFCLK_SEL_150MHZ 0x30000
-#define LYNX_28G_PLLnCR0_REFCLK_SEL_161MHZ 0x40000
-
-#define LYNX_28G_PLLnCR1(pll) (0x400 + (pll) * 0x100 + 0x8)
-#define LYNX_28G_PLLnCR1_FRATE_SEL(cr1) (((cr1) & GENMASK(28, 24)))
-#define LYNX_28G_PLLnCR1_FRATE_5G_10GVCO 0x0
-#define LYNX_28G_PLLnCR1_FRATE_5G_25GVCO 0x10000000
-#define LYNX_28G_PLLnCR1_FRATE_10G_20GVCO 0x6000000
+#define PLLnRSTCTL(pll) (0x400 + (pll) * 0x100 + 0x0)
+#define PLLnRSTCTL_DIS(rstctl) (((rstctl) & BIT(24)) >> 24)
+#define PLLnRSTCTL_LOCK(rstctl) (((rstctl) & BIT(23)) >> 23)
+
+#define PLLnCR0(pll) (0x400 + (pll) * 0x100 + 0x4)
+#define PLLnCR0_REFCLK_SEL(cr0) (((cr0) & GENMASK(20, 16)))
+#define PLLnCR0_REFCLK_SEL_100MHZ 0x0
+#define PLLnCR0_REFCLK_SEL_125MHZ 0x10000
+#define PLLnCR0_REFCLK_SEL_156MHZ 0x20000
+#define PLLnCR0_REFCLK_SEL_150MHZ 0x30000
+#define PLLnCR0_REFCLK_SEL_161MHZ 0x40000
+
+#define PLLnCR1(pll) (0x400 + (pll) * 0x100 + 0x8)
+#define PLLnCR1_FRATE_SEL(cr1) (((cr1) & GENMASK(28, 24)))
+#define PLLnCR1_FRATE_5G_10GVCO 0x0
+#define PLLnCR1_FRATE_5G_25GVCO 0x10000000
+#define PLLnCR1_FRATE_10G_20GVCO 0x6000000
/* Per SerDes lane registers */
/* Lane a General Control Register */
-#define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0)
-#define LYNX_28G_LNaGCR0_PROTO_SEL_MSK GENMASK(7, 3)
-#define LYNX_28G_LNaGCR0_PROTO_SEL_SGMII 0x8
-#define LYNX_28G_LNaGCR0_PROTO_SEL_XFI 0x50
-#define LYNX_28G_LNaGCR0_IF_WIDTH_MSK GENMASK(2, 0)
-#define LYNX_28G_LNaGCR0_IF_WIDTH_10_BIT 0x0
-#define LYNX_28G_LNaGCR0_IF_WIDTH_20_BIT 0x2
+#define LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0)
+#define LNaGCR0_PROTO_SEL_MSK GENMASK(7, 3)
+#define LNaGCR0_PROTO_SEL_SGMII 0x8
+#define LNaGCR0_PROTO_SEL_XFI 0x50
+#define LNaGCR0_IF_WIDTH_MSK GENMASK(2, 0)
+#define LNaGCR0_IF_WIDTH_10_BIT 0x0
+#define LNaGCR0_IF_WIDTH_20_BIT 0x2
/* Lane a Tx Reset Control Register */
-#define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20)
-#define LYNX_28G_LNaTRSTCTL_HLT_REQ BIT(27)
-#define LYNX_28G_LNaTRSTCTL_RST_DONE BIT(30)
-#define LYNX_28G_LNaTRSTCTL_RST_REQ BIT(31)
+#define LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20)
+#define LNaTRSTCTL_HLT_REQ BIT(27)
+#define LNaTRSTCTL_RST_DONE BIT(30)
+#define LNaTRSTCTL_RST_REQ BIT(31)
/* Lane a Tx General Control Register */
-#define LYNX_28G_LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24)
-#define LYNX_28G_LNaTGCR0_USE_PLLF 0x0
-#define LYNX_28G_LNaTGCR0_USE_PLLS BIT(28)
-#define LYNX_28G_LNaTGCR0_USE_PLL_MSK BIT(28)
-#define LYNX_28G_LNaTGCR0_N_RATE_FULL 0x0
-#define LYNX_28G_LNaTGCR0_N_RATE_HALF 0x1000000
-#define LYNX_28G_LNaTGCR0_N_RATE_QUARTER 0x2000000
-#define LYNX_28G_LNaTGCR0_N_RATE_MSK GENMASK(26, 24)
+#define LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24)
+#define LNaTGCR0_USE_PLLF 0x0
+#define LNaTGCR0_USE_PLLS BIT(28)
+#define LNaTGCR0_USE_PLL_MSK BIT(28)
+#define LNaTGCR0_N_RATE_FULL 0x0
+#define LNaTGCR0_N_RATE_HALF 0x1000000
+#define LNaTGCR0_N_RATE_QUARTER 0x2000000
+#define LNaTGCR0_N_RATE_MSK GENMASK(26, 24)
-#define LYNX_28G_LNaTECR0(lane) (0x800 + (lane) * 0x100 + 0x30)
+#define LNaTECR0(lane) (0x800 + (lane) * 0x100 + 0x30)
/* Lane a Rx Reset Control Register */
-#define LYNX_28G_LNaRRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x40)
-#define LYNX_28G_LNaRRSTCTL_HLT_REQ BIT(27)
-#define LYNX_28G_LNaRRSTCTL_RST_DONE BIT(30)
-#define LYNX_28G_LNaRRSTCTL_RST_REQ BIT(31)
-#define LYNX_28G_LNaRRSTCTL_CDR_LOCK BIT(12)
+#define LNaRRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x40)
+#define LNaRRSTCTL_HLT_REQ BIT(27)
+#define LNaRRSTCTL_RST_DONE BIT(30)
+#define LNaRRSTCTL_RST_REQ BIT(31)
+#define LNaRRSTCTL_CDR_LOCK BIT(12)
/* Lane a Rx General Control Register */
-#define LYNX_28G_LNaRGCR0(lane) (0x800 + (lane) * 0x100 + 0x44)
-#define LYNX_28G_LNaRGCR0_USE_PLLF 0x0
-#define LYNX_28G_LNaRGCR0_USE_PLLS BIT(28)
-#define LYNX_28G_LNaRGCR0_USE_PLL_MSK BIT(28)
-#define LYNX_28G_LNaRGCR0_N_RATE_MSK GENMASK(26, 24)
-#define LYNX_28G_LNaRGCR0_N_RATE_FULL 0x0
-#define LYNX_28G_LNaRGCR0_N_RATE_HALF 0x1000000
-#define LYNX_28G_LNaRGCR0_N_RATE_QUARTER 0x2000000
-#define LYNX_28G_LNaRGCR0_N_RATE_MSK GENMASK(26, 24)
-
-#define LYNX_28G_LNaRGCR1(lane) (0x800 + (lane) * 0x100 + 0x48)
-
-#define LYNX_28G_LNaRECR0(lane) (0x800 + (lane) * 0x100 + 0x50)
-#define LYNX_28G_LNaRECR1(lane) (0x800 + (lane) * 0x100 + 0x54)
-#define LYNX_28G_LNaRECR2(lane) (0x800 + (lane) * 0x100 + 0x58)
-
-#define LYNX_28G_LNaRSCCR0(lane) (0x800 + (lane) * 0x100 + 0x74)
-
-#define LYNX_28G_LNaPSS(lane) (0x1000 + (lane) * 0x4)
-#define LYNX_28G_LNaPSS_TYPE(pss) (((pss) & GENMASK(30, 24)) >> 24)
-#define LYNX_28G_LNaPSS_TYPE_SGMII 0x4
-#define LYNX_28G_LNaPSS_TYPE_XFI 0x28
-
-#define LYNX_28G_SGMIIaCR1(lane) (0x1804 + (lane) * 0x10)
-#define LYNX_28G_SGMIIaCR1_SGPCS_EN BIT(11)
-#define LYNX_28G_SGMIIaCR1_SGPCS_DIS 0x0
-#define LYNX_28G_SGMIIaCR1_SGPCS_MSK BIT(11)
+#define LNaRGCR0(lane) (0x800 + (lane) * 0x100 + 0x44)
+#define LNaRGCR0_USE_PLLF 0x0
+#define LNaRGCR0_USE_PLLS BIT(28)
+#define LNaRGCR0_USE_PLL_MSK BIT(28)
+#define LNaRGCR0_N_RATE_MSK GENMASK(26, 24)
+#define LNaRGCR0_N_RATE_FULL 0x0
+#define LNaRGCR0_N_RATE_HALF 0x1000000
+#define LNaRGCR0_N_RATE_QUARTER 0x2000000
+#define LNaRGCR0_N_RATE_MSK GENMASK(26, 24)
+
+#define LNaRGCR1(lane) (0x800 + (lane) * 0x100 + 0x48)
+
+#define LNaRECR0(lane) (0x800 + (lane) * 0x100 + 0x50)
+#define LNaRECR1(lane) (0x800 + (lane) * 0x100 + 0x54)
+#define LNaRECR2(lane) (0x800 + (lane) * 0x100 + 0x58)
+
+#define LNaRSCCR0(lane) (0x800 + (lane) * 0x100 + 0x74)
+
+#define LNaPSS(lane) (0x1000 + (lane) * 0x4)
+#define LNaPSS_TYPE(pss) (((pss) & GENMASK(30, 24)) >> 24)
+#define LNaPSS_TYPE_SGMII 0x4
+#define LNaPSS_TYPE_XFI 0x28
+
+#define SGMIIaCR1(lane) (0x1804 + (lane) * 0x10)
+#define SGMIIaCR1_SGPCS_EN BIT(11)
+#define SGMIIaCR1_SGPCS_DIS 0x0
+#define SGMIIaCR1_SGPCS_MSK BIT(11)
struct lynx_28g_priv;
@@ -150,19 +150,19 @@ static void lynx_28g_rmw(struct lynx_28g_priv *priv, unsigned long off,
}
#define lynx_28g_lane_rmw(lane, reg, val, mask) \
- lynx_28g_rmw((lane)->priv, LYNX_28G_##reg(lane->id), \
- LYNX_28G_##reg##_##val, LYNX_28G_##reg##_##mask)
+ lynx_28g_rmw((lane)->priv, reg(lane->id), \
+ reg##_##val, reg##_##mask)
#define lynx_28g_lane_read(lane, reg) \
- ioread32((lane)->priv->base + LYNX_28G_##reg((lane)->id))
+ ioread32((lane)->priv->base + reg((lane)->id))
#define lynx_28g_pll_read(pll, reg) \
- ioread32((pll)->priv->base + LYNX_28G_##reg((pll)->id))
+ ioread32((pll)->priv->base + reg((pll)->id))
static bool lynx_28g_supports_interface(struct lynx_28g_priv *priv, int intf)
{
int i;
for (i = 0; i < LYNX_28G_NUM_PLL; i++) {
- if (LYNX_28G_PLLnRSTCTL_DIS(priv->pll[i].rstctl))
+ if (PLLnRSTCTL_DIS(priv->pll[i].rstctl))
continue;
if (test_bit(intf, priv->pll[i].supported))
@@ -181,7 +181,7 @@ static struct lynx_28g_pll *lynx_28g_pll_get(struct lynx_28g_priv *priv,
for (i = 0; i < LYNX_28G_NUM_PLL; i++) {
pll = &priv->pll[i];
- if (LYNX_28G_PLLnRSTCTL_DIS(pll->rstctl))
+ if (PLLnRSTCTL_DIS(pll->rstctl))
continue;
if (test_bit(intf, pll->supported))
@@ -199,9 +199,9 @@ static void lynx_28g_lane_set_nrate(struct lynx_28g_lane *lane,
struct lynx_28g_pll *pll,
phy_interface_t intf)
{
- switch (LYNX_28G_PLLnCR1_FRATE_SEL(pll->cr1)) {
- case LYNX_28G_PLLnCR1_FRATE_5G_10GVCO:
- case LYNX_28G_PLLnCR1_FRATE_5G_25GVCO:
+ switch (PLLnCR1_FRATE_SEL(pll->cr1)) {
+ case PLLnCR1_FRATE_5G_10GVCO:
+ case PLLnCR1_FRATE_5G_25GVCO:
switch (intf) {
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_1000BASEX:
@@ -212,7 +212,7 @@ static void lynx_28g_lane_set_nrate(struct lynx_28g_lane *lane,
break;
}
break;
- case LYNX_28G_PLLnCR1_FRATE_10G_20GVCO:
+ case PLLnCR1_FRATE_10G_20GVCO:
switch (intf) {
case PHY_INTERFACE_MODE_10GBASER:
case PHY_INTERFACE_MODE_USXGMII:
@@ -242,20 +242,20 @@ static void lynx_28g_lane_set_pll(struct lynx_28g_lane *lane,
static void lynx_28g_cleanup_lane(struct lynx_28g_lane *lane)
{
- u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane);
struct lynx_28g_priv *priv = lane->priv;
+ u32 lane_offset = LNa_PCC_OFFSET(lane);
/* Cleanup the protocol configuration registers of the current protocol */
switch (lane->interface) {
case PHY_INTERFACE_MODE_10GBASER:
- lynx_28g_rmw(priv, LYNX_28G_PCCC,
- LYNX_28G_PCCC_SXGMII_DIS << lane_offset,
+ lynx_28g_rmw(priv, PCCC,
+ PCCC_SXGMII_DIS << lane_offset,
GENMASK(3, 0) << lane_offset);
break;
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_1000BASEX:
- lynx_28g_rmw(priv, LYNX_28G_PCC8,
- LYNX_28G_PCC8_SGMII_DIS << lane_offset,
+ lynx_28g_rmw(priv, PCC8,
+ PCC8_SGMII_DIS << lane_offset,
GENMASK(3, 0) << lane_offset);
break;
default:
@@ -265,15 +265,15 @@ static void lynx_28g_cleanup_lane(struct lynx_28g_lane *lane)
static void lynx_28g_lane_set_sgmii(struct lynx_28g_lane *lane)
{
- u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane);
+ u32 lane_offset = LNa_PCC_OFFSET(lane);
struct lynx_28g_priv *priv = lane->priv;
struct lynx_28g_pll *pll;
lynx_28g_cleanup_lane(lane);
/* Setup the lane to run in SGMII */
- lynx_28g_rmw(priv, LYNX_28G_PCC8,
- LYNX_28G_PCC8_SGMII << lane_offset,
+ lynx_28g_rmw(priv, PCC8,
+ PCC8_SGMII << lane_offset,
GENMASK(3, 0) << lane_offset);
/* Setup the protocol select and SerDes parallel interface width */
@@ -295,25 +295,25 @@ static void lynx_28g_lane_set_sgmii(struct lynx_28g_lane *lane)
lynx_28g_lane_rmw(lane, SGMIIaCR1, SGPCS_EN, SGPCS_MSK);
/* Configure the appropriate equalization parameters for the protocol */
- iowrite32(0x00808006, priv->base + LYNX_28G_LNaTECR0(lane->id));
- iowrite32(0x04310000, priv->base + LYNX_28G_LNaRGCR1(lane->id));
- iowrite32(0x9f800000, priv->base + LYNX_28G_LNaRECR0(lane->id));
- iowrite32(0x001f0000, priv->base + LYNX_28G_LNaRECR1(lane->id));
- iowrite32(0x00000000, priv->base + LYNX_28G_LNaRECR2(lane->id));
- iowrite32(0x00000000, priv->base + LYNX_28G_LNaRSCCR0(lane->id));
+ iowrite32(0x00808006, priv->base + LNaTECR0(lane->id));
+ iowrite32(0x04310000, priv->base + LNaRGCR1(lane->id));
+ iowrite32(0x9f800000, priv->base + LNaRECR0(lane->id));
+ iowrite32(0x001f0000, priv->base + LNaRECR1(lane->id));
+ iowrite32(0x00000000, priv->base + LNaRECR2(lane->id));
+ iowrite32(0x00000000, priv->base + LNaRSCCR0(lane->id));
}
static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane)
{
- u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane);
struct lynx_28g_priv *priv = lane->priv;
+ u32 lane_offset = LNa_PCC_OFFSET(lane);
struct lynx_28g_pll *pll;
lynx_28g_cleanup_lane(lane);
/* Enable the SXGMII lane */
- lynx_28g_rmw(priv, LYNX_28G_PCCC,
- LYNX_28G_PCCC_10GBASER << lane_offset,
+ lynx_28g_rmw(priv, PCCC,
+ PCCC_10GBASER << lane_offset,
GENMASK(3, 0) << lane_offset);
/* Setup the protocol select and SerDes parallel interface width */
@@ -335,12 +335,12 @@ static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane)
lynx_28g_lane_rmw(lane, SGMIIaCR1, SGPCS_DIS, SGPCS_MSK);
/* Configure the appropriate equalization parameters for the protocol */
- iowrite32(0x10808307, priv->base + LYNX_28G_LNaTECR0(lane->id));
- iowrite32(0x10000000, priv->base + LYNX_28G_LNaRGCR1(lane->id));
- iowrite32(0x00000000, priv->base + LYNX_28G_LNaRECR0(lane->id));
- iowrite32(0x001f0000, priv->base + LYNX_28G_LNaRECR1(lane->id));
- iowrite32(0x81000020, priv->base + LYNX_28G_LNaRECR2(lane->id));
- iowrite32(0x00002000, priv->base + LYNX_28G_LNaRSCCR0(lane->id));
+ iowrite32(0x10808307, priv->base + LNaTECR0(lane->id));
+ iowrite32(0x10000000, priv->base + LNaRGCR1(lane->id));
+ iowrite32(0x00000000, priv->base + LNaRECR0(lane->id));
+ iowrite32(0x001f0000, priv->base + LNaRECR1(lane->id));
+ iowrite32(0x81000020, priv->base + LNaRECR2(lane->id));
+ iowrite32(0x00002000, priv->base + LNaRSCCR0(lane->id));
}
static int lynx_28g_power_off(struct phy *phy)
@@ -359,8 +359,8 @@ static int lynx_28g_power_off(struct phy *phy)
do {
trstctl = lynx_28g_lane_read(lane, LNaTRSTCTL);
rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
- } while ((trstctl & LYNX_28G_LNaTRSTCTL_HLT_REQ) ||
- (rrstctl & LYNX_28G_LNaRRSTCTL_HLT_REQ));
+ } while ((trstctl & LNaTRSTCTL_HLT_REQ) ||
+ (rrstctl & LNaRRSTCTL_HLT_REQ));
lane->powered_up = false;
@@ -383,8 +383,8 @@ static int lynx_28g_power_on(struct phy *phy)
do {
trstctl = lynx_28g_lane_read(lane, LNaTRSTCTL);
rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
- } while (!(trstctl & LYNX_28G_LNaTRSTCTL_RST_DONE) ||
- !(rrstctl & LYNX_28G_LNaRRSTCTL_RST_DONE));
+ } while (!(trstctl & LNaTRSTCTL_RST_DONE) ||
+ !(rrstctl & LNaRRSTCTL_RST_DONE));
lane->powered_up = true;
@@ -495,17 +495,17 @@ static void lynx_28g_pll_read_configuration(struct lynx_28g_priv *priv)
pll->cr0 = lynx_28g_pll_read(pll, PLLnCR0);
pll->cr1 = lynx_28g_pll_read(pll, PLLnCR1);
- if (LYNX_28G_PLLnRSTCTL_DIS(pll->rstctl))
+ if (PLLnRSTCTL_DIS(pll->rstctl))
continue;
- switch (LYNX_28G_PLLnCR1_FRATE_SEL(pll->cr1)) {
- case LYNX_28G_PLLnCR1_FRATE_5G_10GVCO:
- case LYNX_28G_PLLnCR1_FRATE_5G_25GVCO:
+ switch (PLLnCR1_FRATE_SEL(pll->cr1)) {
+ case PLLnCR1_FRATE_5G_10GVCO:
+ case PLLnCR1_FRATE_5G_25GVCO:
/* 5GHz clock net */
__set_bit(PHY_INTERFACE_MODE_1000BASEX, pll->supported);
__set_bit(PHY_INTERFACE_MODE_SGMII, pll->supported);
break;
- case LYNX_28G_PLLnCR1_FRATE_10G_20GVCO:
+ case PLLnCR1_FRATE_10G_20GVCO:
/* 10.3125GHz clock net */
__set_bit(PHY_INTERFACE_MODE_10GBASER, pll->supported);
break;
@@ -536,11 +536,11 @@ static void lynx_28g_cdr_lock_check(struct work_struct *work)
}
rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
- if (!(rrstctl & LYNX_28G_LNaRRSTCTL_CDR_LOCK)) {
+ if (!(rrstctl & LNaRRSTCTL_CDR_LOCK)) {
lynx_28g_lane_rmw(lane, LNaRRSTCTL, RST_REQ, RST_REQ);
do {
rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
- } while (!(rrstctl & LYNX_28G_LNaRRSTCTL_RST_DONE));
+ } while (!(rrstctl & LNaRRSTCTL_RST_DONE));
}
mutex_unlock(&lane->phy->mutex);
@@ -554,12 +554,12 @@ static void lynx_28g_lane_read_configuration(struct lynx_28g_lane *lane)
u32 pss, protocol;
pss = lynx_28g_lane_read(lane, LNaPSS);
- protocol = LYNX_28G_LNaPSS_TYPE(pss);
+ protocol = LNaPSS_TYPE(pss);
switch (protocol) {
- case LYNX_28G_LNaPSS_TYPE_SGMII:
+ case LNaPSS_TYPE_SGMII:
lane->interface = PHY_INTERFACE_MODE_SGMII;
break;
- case LYNX_28G_LNaPSS_TYPE_XFI:
+ case LNaPSS_TYPE_XFI:
lane->interface = PHY_INTERFACE_MODE_10GBASER;
break;
default:
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v3 phy 02/17] phy: lynx-28g: don't concatenate lynx_28g_lane_rmw() argument "reg" with "val" and "mask"
2025-09-26 18:04 [PATCH v3 phy 00/17] Lynx 28G improvements part 1 Vladimir Oltean
2025-09-26 18:04 ` [PATCH v3 phy 01/17] phy: lynx-28g: remove LYNX_28G_ prefix from register names Vladimir Oltean
@ 2025-09-26 18:04 ` Vladimir Oltean
2025-09-26 18:04 ` [PATCH v3 phy 03/17] phy: lynx-28g: use FIELD_GET() and FIELD_PREP() Vladimir Oltean
` (14 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Vladimir Oltean @ 2025-09-26 18:04 UTC (permalink / raw)
To: linux-phy
Cc: Ioana Ciornei, Vinod Koul, Kishon Vijay Abraham I, Josua Mayer,
linux-kernel
The last step in having lynx_28g_lane_rmw() arguments that fully point
to their definitions is the removal of the current concatenation logic,
by which e.g. "LNaTGCR0, N_RATE_QUARTER, N_RATE_MSK" is expanded to
"LNaTGCR0, LNaTGCR0_N_RATE_QUARTER, LNaTGCR0_N_RATE_MSK".
There are pros and cons to the above. An advantage is the impossibility
to mix up fields of one register with fields of another. For example
both LNaTGCR0 and LNaRGCR0 contain an N_RATE_QUARTER field (one for the
lane RX direction, one for the lane TX).
But the two notable disadvantages are:
1. the impossibility to write expressions such as logical OR between
multiple fields. Practically, this forces us to perform more accesses
to hardware registers than would otherwise be needed. See the LNaGCR0
access for example.
2. the necessity to invent fields that don't exist, like SGMIIaCR1_SGPCS_DIS,
in order to clear SGMIIaCR1_SGPCS_EN (the real field name). This is
confusing, because sometimes, fields that end with _DIS really exist,
and it's best to not invent new field names.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
v1->v3: none
drivers/phy/freescale/phy-fsl-lynx-28g.c | 60 +++++++++++++++---------
1 file changed, 38 insertions(+), 22 deletions(-)
diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
index 4e8d2c56d702..732ba65950f3 100644
--- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
+++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
@@ -103,7 +103,6 @@
#define SGMIIaCR1(lane) (0x1804 + (lane) * 0x10)
#define SGMIIaCR1_SGPCS_EN BIT(11)
-#define SGMIIaCR1_SGPCS_DIS 0x0
#define SGMIIaCR1_SGPCS_MSK BIT(11)
struct lynx_28g_priv;
@@ -150,8 +149,7 @@ static void lynx_28g_rmw(struct lynx_28g_priv *priv, unsigned long off,
}
#define lynx_28g_lane_rmw(lane, reg, val, mask) \
- lynx_28g_rmw((lane)->priv, reg(lane->id), \
- reg##_##val, reg##_##mask)
+ lynx_28g_rmw((lane)->priv, reg(lane->id), val, mask)
#define lynx_28g_lane_read(lane, reg) \
ioread32((lane)->priv->base + reg((lane)->id))
#define lynx_28g_pll_read(pll, reg) \
@@ -205,8 +203,12 @@ static void lynx_28g_lane_set_nrate(struct lynx_28g_lane *lane,
switch (intf) {
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_1000BASEX:
- lynx_28g_lane_rmw(lane, LNaTGCR0, N_RATE_QUARTER, N_RATE_MSK);
- lynx_28g_lane_rmw(lane, LNaRGCR0, N_RATE_QUARTER, N_RATE_MSK);
+ lynx_28g_lane_rmw(lane, LNaTGCR0,
+ LNaTGCR0_N_RATE_QUARTER,
+ LNaTGCR0_N_RATE_MSK);
+ lynx_28g_lane_rmw(lane, LNaRGCR0,
+ LNaRGCR0_N_RATE_QUARTER,
+ LNaRGCR0_N_RATE_MSK);
break;
default:
break;
@@ -216,8 +218,10 @@ static void lynx_28g_lane_set_nrate(struct lynx_28g_lane *lane,
switch (intf) {
case PHY_INTERFACE_MODE_10GBASER:
case PHY_INTERFACE_MODE_USXGMII:
- lynx_28g_lane_rmw(lane, LNaTGCR0, N_RATE_FULL, N_RATE_MSK);
- lynx_28g_lane_rmw(lane, LNaRGCR0, N_RATE_FULL, N_RATE_MSK);
+ lynx_28g_lane_rmw(lane, LNaTGCR0, LNaTGCR0_N_RATE_FULL,
+ LNaTGCR0_N_RATE_MSK);
+ lynx_28g_lane_rmw(lane, LNaRGCR0, LNaRGCR0_N_RATE_FULL,
+ LNaRGCR0_N_RATE_MSK);
break;
default:
break;
@@ -232,11 +236,15 @@ static void lynx_28g_lane_set_pll(struct lynx_28g_lane *lane,
struct lynx_28g_pll *pll)
{
if (pll->id == 0) {
- lynx_28g_lane_rmw(lane, LNaTGCR0, USE_PLLF, USE_PLL_MSK);
- lynx_28g_lane_rmw(lane, LNaRGCR0, USE_PLLF, USE_PLL_MSK);
+ lynx_28g_lane_rmw(lane, LNaTGCR0, LNaTGCR0_USE_PLLF,
+ LNaTGCR0_USE_PLL_MSK);
+ lynx_28g_lane_rmw(lane, LNaRGCR0, LNaRGCR0_USE_PLLF,
+ LNaRGCR0_USE_PLL_MSK);
} else {
- lynx_28g_lane_rmw(lane, LNaTGCR0, USE_PLLS, USE_PLL_MSK);
- lynx_28g_lane_rmw(lane, LNaRGCR0, USE_PLLS, USE_PLL_MSK);
+ lynx_28g_lane_rmw(lane, LNaTGCR0, LNaTGCR0_USE_PLLS,
+ LNaTGCR0_USE_PLL_MSK);
+ lynx_28g_lane_rmw(lane, LNaRGCR0, LNaRGCR0_USE_PLLS,
+ LNaRGCR0_USE_PLL_MSK);
}
}
@@ -277,8 +285,9 @@ static void lynx_28g_lane_set_sgmii(struct lynx_28g_lane *lane)
GENMASK(3, 0) << lane_offset);
/* Setup the protocol select and SerDes parallel interface width */
- lynx_28g_lane_rmw(lane, LNaGCR0, PROTO_SEL_SGMII, PROTO_SEL_MSK);
- lynx_28g_lane_rmw(lane, LNaGCR0, IF_WIDTH_10_BIT, IF_WIDTH_MSK);
+ lynx_28g_lane_rmw(lane, LNaGCR0,
+ LNaGCR0_PROTO_SEL_SGMII | LNaGCR0_IF_WIDTH_10_BIT,
+ LNaGCR0_PROTO_SEL_MSK | LNaGCR0_IF_WIDTH_MSK);
/* Find the PLL that works with this interface type */
pll = lynx_28g_pll_get(priv, PHY_INTERFACE_MODE_SGMII);
@@ -292,7 +301,8 @@ static void lynx_28g_lane_set_sgmii(struct lynx_28g_lane *lane)
lynx_28g_lane_set_nrate(lane, pll, PHY_INTERFACE_MODE_SGMII);
/* Enable the SGMII PCS */
- lynx_28g_lane_rmw(lane, SGMIIaCR1, SGPCS_EN, SGPCS_MSK);
+ lynx_28g_lane_rmw(lane, SGMIIaCR1, SGMIIaCR1_SGPCS_EN,
+ SGMIIaCR1_SGPCS_MSK);
/* Configure the appropriate equalization parameters for the protocol */
iowrite32(0x00808006, priv->base + LNaTECR0(lane->id));
@@ -317,8 +327,9 @@ static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane)
GENMASK(3, 0) << lane_offset);
/* Setup the protocol select and SerDes parallel interface width */
- lynx_28g_lane_rmw(lane, LNaGCR0, PROTO_SEL_XFI, PROTO_SEL_MSK);
- lynx_28g_lane_rmw(lane, LNaGCR0, IF_WIDTH_20_BIT, IF_WIDTH_MSK);
+ lynx_28g_lane_rmw(lane, LNaGCR0,
+ LNaGCR0_PROTO_SEL_XFI | LNaGCR0_IF_WIDTH_20_BIT,
+ LNaGCR0_PROTO_SEL_MSK | LNaGCR0_IF_WIDTH_MSK);
/* Find the PLL that works with this interface type */
pll = lynx_28g_pll_get(priv, PHY_INTERFACE_MODE_10GBASER);
@@ -332,7 +343,7 @@ static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane)
lynx_28g_lane_set_nrate(lane, pll, PHY_INTERFACE_MODE_10GBASER);
/* Disable the SGMII PCS */
- lynx_28g_lane_rmw(lane, SGMIIaCR1, SGPCS_DIS, SGPCS_MSK);
+ lynx_28g_lane_rmw(lane, SGMIIaCR1, 0, SGMIIaCR1_SGPCS_MSK);
/* Configure the appropriate equalization parameters for the protocol */
iowrite32(0x10808307, priv->base + LNaTECR0(lane->id));
@@ -352,8 +363,10 @@ static int lynx_28g_power_off(struct phy *phy)
return 0;
/* Issue a halt request */
- lynx_28g_lane_rmw(lane, LNaTRSTCTL, HLT_REQ, HLT_REQ);
- lynx_28g_lane_rmw(lane, LNaRRSTCTL, HLT_REQ, HLT_REQ);
+ lynx_28g_lane_rmw(lane, LNaTRSTCTL, LNaTRSTCTL_HLT_REQ,
+ LNaTRSTCTL_HLT_REQ);
+ lynx_28g_lane_rmw(lane, LNaRRSTCTL, LNaRRSTCTL_HLT_REQ,
+ LNaRRSTCTL_HLT_REQ);
/* Wait until the halting process is complete */
do {
@@ -376,8 +389,10 @@ static int lynx_28g_power_on(struct phy *phy)
return 0;
/* Issue a reset request on the lane */
- lynx_28g_lane_rmw(lane, LNaTRSTCTL, RST_REQ, RST_REQ);
- lynx_28g_lane_rmw(lane, LNaRRSTCTL, RST_REQ, RST_REQ);
+ lynx_28g_lane_rmw(lane, LNaTRSTCTL, LNaTRSTCTL_RST_REQ,
+ LNaTRSTCTL_RST_REQ);
+ lynx_28g_lane_rmw(lane, LNaRRSTCTL, LNaRRSTCTL_RST_REQ,
+ LNaRRSTCTL_RST_REQ);
/* Wait until the reset sequence is completed */
do {
@@ -537,7 +552,8 @@ static void lynx_28g_cdr_lock_check(struct work_struct *work)
rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
if (!(rrstctl & LNaRRSTCTL_CDR_LOCK)) {
- lynx_28g_lane_rmw(lane, LNaRRSTCTL, RST_REQ, RST_REQ);
+ lynx_28g_lane_rmw(lane, LNaRRSTCTL, LNaRRSTCTL_RST_REQ,
+ LNaRRSTCTL_RST_REQ);
do {
rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
} while (!(rrstctl & LNaRRSTCTL_RST_DONE));
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v3 phy 03/17] phy: lynx-28g: use FIELD_GET() and FIELD_PREP()
2025-09-26 18:04 [PATCH v3 phy 00/17] Lynx 28G improvements part 1 Vladimir Oltean
2025-09-26 18:04 ` [PATCH v3 phy 01/17] phy: lynx-28g: remove LYNX_28G_ prefix from register names Vladimir Oltean
2025-09-26 18:04 ` [PATCH v3 phy 02/17] phy: lynx-28g: don't concatenate lynx_28g_lane_rmw() argument "reg" with "val" and "mask" Vladimir Oltean
@ 2025-09-26 18:04 ` Vladimir Oltean
2025-09-26 18:04 ` [PATCH v3 phy 04/17] phy: lynx-28g: convert iowrite32() calls with magic values to macros Vladimir Oltean
` (13 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Vladimir Oltean @ 2025-09-26 18:04 UTC (permalink / raw)
To: linux-phy
Cc: Ioana Ciornei, Vinod Koul, Kishon Vijay Abraham I, Josua Mayer,
linux-kernel
Reduce the number of bit field definitions required in this driver (in
the worst case, a read form and a write form), by defining just the
mask, and using the FIELD_GET() and FIELD_PREP() API from
<linux/bitfield.h> with that.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
v1->v3: none
drivers/phy/freescale/phy-fsl-lynx-28g.c | 107 ++++++++++++-----------
1 file changed, 57 insertions(+), 50 deletions(-)
diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
index 732ba65950f3..414d9a4bcbb7 100644
--- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
+++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/* Copyright (c) 2021-2022 NXP. */
+#include <linux/bitfield.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/phy.h>
@@ -29,26 +30,26 @@
#define PLLnRSTCTL_LOCK(rstctl) (((rstctl) & BIT(23)) >> 23)
#define PLLnCR0(pll) (0x400 + (pll) * 0x100 + 0x4)
-#define PLLnCR0_REFCLK_SEL(cr0) (((cr0) & GENMASK(20, 16)))
+#define PLLnCR0_REFCLK_SEL GENMASK(20, 16)
#define PLLnCR0_REFCLK_SEL_100MHZ 0x0
-#define PLLnCR0_REFCLK_SEL_125MHZ 0x10000
-#define PLLnCR0_REFCLK_SEL_156MHZ 0x20000
-#define PLLnCR0_REFCLK_SEL_150MHZ 0x30000
-#define PLLnCR0_REFCLK_SEL_161MHZ 0x40000
+#define PLLnCR0_REFCLK_SEL_125MHZ 0x1
+#define PLLnCR0_REFCLK_SEL_156MHZ 0x2
+#define PLLnCR0_REFCLK_SEL_150MHZ 0x3
+#define PLLnCR0_REFCLK_SEL_161MHZ 0x4
#define PLLnCR1(pll) (0x400 + (pll) * 0x100 + 0x8)
-#define PLLnCR1_FRATE_SEL(cr1) (((cr1) & GENMASK(28, 24)))
+#define PLLnCR1_FRATE_SEL GENMASK(28, 24)
#define PLLnCR1_FRATE_5G_10GVCO 0x0
-#define PLLnCR1_FRATE_5G_25GVCO 0x10000000
-#define PLLnCR1_FRATE_10G_20GVCO 0x6000000
+#define PLLnCR1_FRATE_5G_25GVCO 0x10
+#define PLLnCR1_FRATE_10G_20GVCO 0x6
/* Per SerDes lane registers */
/* Lane a General Control Register */
#define LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0)
-#define LNaGCR0_PROTO_SEL_MSK GENMASK(7, 3)
-#define LNaGCR0_PROTO_SEL_SGMII 0x8
-#define LNaGCR0_PROTO_SEL_XFI 0x50
-#define LNaGCR0_IF_WIDTH_MSK GENMASK(2, 0)
+#define LNaGCR0_PROTO_SEL GENMASK(7, 3)
+#define LNaGCR0_PROTO_SEL_SGMII 0x1
+#define LNaGCR0_PROTO_SEL_XFI 0xa
+#define LNaGCR0_IF_WIDTH GENMASK(2, 0)
#define LNaGCR0_IF_WIDTH_10_BIT 0x0
#define LNaGCR0_IF_WIDTH_20_BIT 0x2
@@ -60,13 +61,13 @@
/* Lane a Tx General Control Register */
#define LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24)
+#define LNaTGCR0_USE_PLL BIT(28)
#define LNaTGCR0_USE_PLLF 0x0
-#define LNaTGCR0_USE_PLLS BIT(28)
-#define LNaTGCR0_USE_PLL_MSK BIT(28)
+#define LNaTGCR0_USE_PLLS 0x1
+#define LNaTGCR0_N_RATE GENMASK(26, 24)
#define LNaTGCR0_N_RATE_FULL 0x0
-#define LNaTGCR0_N_RATE_HALF 0x1000000
-#define LNaTGCR0_N_RATE_QUARTER 0x2000000
-#define LNaTGCR0_N_RATE_MSK GENMASK(26, 24)
+#define LNaTGCR0_N_RATE_HALF 0x1
+#define LNaTGCR0_N_RATE_QUARTER 0x2
#define LNaTECR0(lane) (0x800 + (lane) * 0x100 + 0x30)
@@ -79,14 +80,13 @@
/* Lane a Rx General Control Register */
#define LNaRGCR0(lane) (0x800 + (lane) * 0x100 + 0x44)
+#define LNaRGCR0_USE_PLL BIT(28)
#define LNaRGCR0_USE_PLLF 0x0
-#define LNaRGCR0_USE_PLLS BIT(28)
-#define LNaRGCR0_USE_PLL_MSK BIT(28)
-#define LNaRGCR0_N_RATE_MSK GENMASK(26, 24)
+#define LNaRGCR0_USE_PLLS 0x1
+#define LNaRGCR0_N_RATE GENMASK(26, 24)
#define LNaRGCR0_N_RATE_FULL 0x0
-#define LNaRGCR0_N_RATE_HALF 0x1000000
-#define LNaRGCR0_N_RATE_QUARTER 0x2000000
-#define LNaRGCR0_N_RATE_MSK GENMASK(26, 24)
+#define LNaRGCR0_N_RATE_HALF 0x1
+#define LNaRGCR0_N_RATE_QUARTER 0x2
#define LNaRGCR1(lane) (0x800 + (lane) * 0x100 + 0x48)
@@ -97,13 +97,12 @@
#define LNaRSCCR0(lane) (0x800 + (lane) * 0x100 + 0x74)
#define LNaPSS(lane) (0x1000 + (lane) * 0x4)
-#define LNaPSS_TYPE(pss) (((pss) & GENMASK(30, 24)) >> 24)
+#define LNaPSS_TYPE GENMASK(30, 24)
#define LNaPSS_TYPE_SGMII 0x4
#define LNaPSS_TYPE_XFI 0x28
#define SGMIIaCR1(lane) (0x1804 + (lane) * 0x10)
#define SGMIIaCR1_SGPCS_EN BIT(11)
-#define SGMIIaCR1_SGPCS_MSK BIT(11)
struct lynx_28g_priv;
@@ -197,18 +196,18 @@ static void lynx_28g_lane_set_nrate(struct lynx_28g_lane *lane,
struct lynx_28g_pll *pll,
phy_interface_t intf)
{
- switch (PLLnCR1_FRATE_SEL(pll->cr1)) {
+ switch (FIELD_GET(PLLnCR1_FRATE_SEL, pll->cr1)) {
case PLLnCR1_FRATE_5G_10GVCO:
case PLLnCR1_FRATE_5G_25GVCO:
switch (intf) {
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_1000BASEX:
lynx_28g_lane_rmw(lane, LNaTGCR0,
- LNaTGCR0_N_RATE_QUARTER,
- LNaTGCR0_N_RATE_MSK);
+ FIELD_PREP(LNaTGCR0_N_RATE, LNaTGCR0_N_RATE_QUARTER),
+ LNaTGCR0_N_RATE);
lynx_28g_lane_rmw(lane, LNaRGCR0,
- LNaRGCR0_N_RATE_QUARTER,
- LNaRGCR0_N_RATE_MSK);
+ FIELD_PREP(LNaRGCR0_N_RATE, LNaRGCR0_N_RATE_QUARTER),
+ LNaRGCR0_N_RATE);
break;
default:
break;
@@ -218,10 +217,12 @@ static void lynx_28g_lane_set_nrate(struct lynx_28g_lane *lane,
switch (intf) {
case PHY_INTERFACE_MODE_10GBASER:
case PHY_INTERFACE_MODE_USXGMII:
- lynx_28g_lane_rmw(lane, LNaTGCR0, LNaTGCR0_N_RATE_FULL,
- LNaTGCR0_N_RATE_MSK);
- lynx_28g_lane_rmw(lane, LNaRGCR0, LNaRGCR0_N_RATE_FULL,
- LNaRGCR0_N_RATE_MSK);
+ lynx_28g_lane_rmw(lane, LNaTGCR0,
+ FIELD_PREP(LNaTGCR0_N_RATE, LNaTGCR0_N_RATE_FULL),
+ LNaTGCR0_N_RATE);
+ lynx_28g_lane_rmw(lane, LNaRGCR0,
+ FIELD_PREP(LNaRGCR0_N_RATE, LNaRGCR0_N_RATE_FULL),
+ LNaRGCR0_N_RATE);
break;
default:
break;
@@ -236,15 +237,19 @@ static void lynx_28g_lane_set_pll(struct lynx_28g_lane *lane,
struct lynx_28g_pll *pll)
{
if (pll->id == 0) {
- lynx_28g_lane_rmw(lane, LNaTGCR0, LNaTGCR0_USE_PLLF,
- LNaTGCR0_USE_PLL_MSK);
- lynx_28g_lane_rmw(lane, LNaRGCR0, LNaRGCR0_USE_PLLF,
- LNaRGCR0_USE_PLL_MSK);
+ lynx_28g_lane_rmw(lane, LNaTGCR0,
+ FIELD_PREP(LNaTGCR0_USE_PLL, LNaTGCR0_USE_PLLF),
+ LNaTGCR0_USE_PLL);
+ lynx_28g_lane_rmw(lane, LNaRGCR0,
+ FIELD_PREP(LNaRGCR0_USE_PLL, LNaRGCR0_USE_PLLF),
+ LNaRGCR0_USE_PLL);
} else {
- lynx_28g_lane_rmw(lane, LNaTGCR0, LNaTGCR0_USE_PLLS,
- LNaTGCR0_USE_PLL_MSK);
- lynx_28g_lane_rmw(lane, LNaRGCR0, LNaRGCR0_USE_PLLS,
- LNaRGCR0_USE_PLL_MSK);
+ lynx_28g_lane_rmw(lane, LNaTGCR0,
+ FIELD_PREP(LNaTGCR0_USE_PLL, LNaTGCR0_USE_PLLS),
+ LNaTGCR0_USE_PLL);
+ lynx_28g_lane_rmw(lane, LNaRGCR0,
+ FIELD_PREP(LNaRGCR0_USE_PLL, LNaRGCR0_USE_PLLS),
+ LNaRGCR0_USE_PLL);
}
}
@@ -286,8 +291,9 @@ static void lynx_28g_lane_set_sgmii(struct lynx_28g_lane *lane)
/* Setup the protocol select and SerDes parallel interface width */
lynx_28g_lane_rmw(lane, LNaGCR0,
- LNaGCR0_PROTO_SEL_SGMII | LNaGCR0_IF_WIDTH_10_BIT,
- LNaGCR0_PROTO_SEL_MSK | LNaGCR0_IF_WIDTH_MSK);
+ FIELD_PREP(LNaGCR0_PROTO_SEL, LNaGCR0_PROTO_SEL_SGMII) |
+ FIELD_PREP(LNaGCR0_IF_WIDTH, LNaGCR0_IF_WIDTH_10_BIT),
+ LNaGCR0_PROTO_SEL | LNaGCR0_IF_WIDTH);
/* Find the PLL that works with this interface type */
pll = lynx_28g_pll_get(priv, PHY_INTERFACE_MODE_SGMII);
@@ -302,7 +308,7 @@ static void lynx_28g_lane_set_sgmii(struct lynx_28g_lane *lane)
/* Enable the SGMII PCS */
lynx_28g_lane_rmw(lane, SGMIIaCR1, SGMIIaCR1_SGPCS_EN,
- SGMIIaCR1_SGPCS_MSK);
+ SGMIIaCR1_SGPCS_EN);
/* Configure the appropriate equalization parameters for the protocol */
iowrite32(0x00808006, priv->base + LNaTECR0(lane->id));
@@ -328,8 +334,9 @@ static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane)
/* Setup the protocol select and SerDes parallel interface width */
lynx_28g_lane_rmw(lane, LNaGCR0,
- LNaGCR0_PROTO_SEL_XFI | LNaGCR0_IF_WIDTH_20_BIT,
- LNaGCR0_PROTO_SEL_MSK | LNaGCR0_IF_WIDTH_MSK);
+ FIELD_PREP(LNaGCR0_PROTO_SEL, LNaGCR0_PROTO_SEL_XFI) |
+ FIELD_PREP(LNaGCR0_IF_WIDTH, LNaGCR0_IF_WIDTH_20_BIT),
+ LNaGCR0_PROTO_SEL | LNaGCR0_IF_WIDTH);
/* Find the PLL that works with this interface type */
pll = lynx_28g_pll_get(priv, PHY_INTERFACE_MODE_10GBASER);
@@ -343,7 +350,7 @@ static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane)
lynx_28g_lane_set_nrate(lane, pll, PHY_INTERFACE_MODE_10GBASER);
/* Disable the SGMII PCS */
- lynx_28g_lane_rmw(lane, SGMIIaCR1, 0, SGMIIaCR1_SGPCS_MSK);
+ lynx_28g_lane_rmw(lane, SGMIIaCR1, 0, SGMIIaCR1_SGPCS_EN);
/* Configure the appropriate equalization parameters for the protocol */
iowrite32(0x10808307, priv->base + LNaTECR0(lane->id));
@@ -513,7 +520,7 @@ static void lynx_28g_pll_read_configuration(struct lynx_28g_priv *priv)
if (PLLnRSTCTL_DIS(pll->rstctl))
continue;
- switch (PLLnCR1_FRATE_SEL(pll->cr1)) {
+ switch (FIELD_GET(PLLnCR1_FRATE_SEL, pll->cr1)) {
case PLLnCR1_FRATE_5G_10GVCO:
case PLLnCR1_FRATE_5G_25GVCO:
/* 5GHz clock net */
@@ -570,7 +577,7 @@ static void lynx_28g_lane_read_configuration(struct lynx_28g_lane *lane)
u32 pss, protocol;
pss = lynx_28g_lane_read(lane, LNaPSS);
- protocol = LNaPSS_TYPE(pss);
+ protocol = FIELD_GET(LNaPSS_TYPE, pss);
switch (protocol) {
case LNaPSS_TYPE_SGMII:
lane->interface = PHY_INTERFACE_MODE_SGMII;
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v3 phy 04/17] phy: lynx-28g: convert iowrite32() calls with magic values to macros
2025-09-26 18:04 [PATCH v3 phy 00/17] Lynx 28G improvements part 1 Vladimir Oltean
` (2 preceding siblings ...)
2025-09-26 18:04 ` [PATCH v3 phy 03/17] phy: lynx-28g: use FIELD_GET() and FIELD_PREP() Vladimir Oltean
@ 2025-09-26 18:04 ` Vladimir Oltean
2025-09-26 18:04 ` [PATCH v3 phy 05/17] phy: lynx-28g: restructure protocol configuration register accesses Vladimir Oltean
` (12 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Vladimir Oltean @ 2025-09-26 18:04 UTC (permalink / raw)
To: linux-phy
Cc: Ioana Ciornei, Vinod Koul, Kishon Vijay Abraham I, Josua Mayer,
linux-kernel
The driver will need to become more careful with the values it writes to
the TX and RX equalization registers. As a preliminary step, convert the
magic numbers to macros defining the register field meanings.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
v2->v3: none
v1->v2: remove duplicate LNaRSCCR0_SMP_AUTOZ_D1F definition
drivers/phy/freescale/phy-fsl-lynx-28g.c | 102 ++++++++++++++++++++---
1 file changed, 90 insertions(+), 12 deletions(-)
diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
index 414d9a4bcbb7..684cafb3d3e1 100644
--- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
+++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
@@ -70,6 +70,12 @@
#define LNaTGCR0_N_RATE_QUARTER 0x2
#define LNaTECR0(lane) (0x800 + (lane) * 0x100 + 0x30)
+#define LNaTECR0_EQ_TYPE GENMASK(30, 28)
+#define LNaTECR0_EQ_SGN_PREQ BIT(23)
+#define LNaTECR0_EQ_PREQ GENMASK(19, 16)
+#define LNaTECR0_EQ_SGN_POST1Q BIT(15)
+#define LNaTECR0_EQ_POST1Q GENMASK(12, 8)
+#define LNaTECR0_EQ_AMP_RED GENMASK(5, 0)
/* Lane a Rx Reset Control Register */
#define LNaRRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x40)
@@ -89,12 +95,56 @@
#define LNaRGCR0_N_RATE_QUARTER 0x2
#define LNaRGCR1(lane) (0x800 + (lane) * 0x100 + 0x48)
+#define LNaRGCR1_RX_ORD_ELECIDLE BIT(31)
+#define LNaRGCR1_DATA_LOST_FLT BIT(30)
+#define LNaRGCR1_DATA_LOST BIT(29)
+#define LNaRGCR1_IDLE_CONFIG BIT(28)
+#define LNaRGCR1_ENTER_IDLE_FLT_SEL GENMASK(26, 24)
+#define LNaRGCR1_EXIT_IDLE_FLT_SEL GENMASK(22, 20)
+#define LNaRGCR1_DATA_LOST_TH_SEL GENMASK(18, 16)
+#define LNaRGCR1_EXT_REC_CLK_SEL GENMASK(10, 8)
+#define LNaRGCR1_WAKE_TX_DIS BIT(5)
+#define LNaRGCR1_PHY_RDY BIT(4)
+#define LNaRGCR1_CHANGE_RX_CLK BIT(3)
+#define LNaRGCR1_PWR_MGT GENMASK(2, 0)
#define LNaRECR0(lane) (0x800 + (lane) * 0x100 + 0x50)
+#define LNaRECR0_EQ_GAINK2_HF_OV_EN BIT(31)
+#define LNaRECR0_EQ_GAINK2_HF_OV GENMASK(28, 24)
+#define LNaRECR0_EQ_GAINK3_MF_OV_EN BIT(23)
+#define LNaRECR0_EQ_GAINK3_MF_OV GENMASK(20, 16)
+#define LNaRECR0_EQ_GAINK4_LF_OV_EN BIT(7)
+#define LNaRECR0_EQ_GAINK4_LF_DIS BIT(6)
+#define LNaRECR0_EQ_GAINK4_LF_OV GENMASK(4, 0)
+
#define LNaRECR1(lane) (0x800 + (lane) * 0x100 + 0x54)
+#define LNaRECR1_EQ_BLW_OV_EN BIT(31)
+#define LNaRECR1_EQ_BLW_OV GENMASK(28, 24)
+#define LNaRECR1_EQ_OFFSET_OV_EN BIT(23)
+#define LNaRECR1_EQ_OFFSET_OV GENMASK(21, 16)
+
#define LNaRECR2(lane) (0x800 + (lane) * 0x100 + 0x58)
+#define LNaRECR2_EQ_OFFSET_RNG_DBL BIT(31)
+#define LNaRECR2_EQ_BOOST GENMASK(29, 28)
+#define LNaRECR2_EQ_BLW_SEL GENMASK(25, 24)
+#define LNaRECR2_EQ_ZERO GENMASK(17, 16)
+#define LNaRECR2_EQ_IND GENMASK(13, 12)
+#define LNaRECR2_EQ_BIN_DATA_AVG_TC GENMASK(5, 4)
+#define LNaRECR2_SPARE_IN GENMASK(1, 0)
#define LNaRSCCR0(lane) (0x800 + (lane) * 0x100 + 0x74)
+#define LNaRSCCR0_SMP_OFF_EN BIT(31)
+#define LNaRSCCR0_SMP_OFF_OV_EN BIT(30)
+#define LNaRSCCR0_SMP_MAN_OFF_EN BIT(29)
+#define LNaRSCCR0_SMP_OFF_RNG_OV_EN BIT(27)
+#define LNaRSCCR0_SMP_OFF_RNG_4X_OV BIT(25)
+#define LNaRSCCR0_SMP_OFF_RNG_2X_OV BIT(24)
+#define LNaRSCCR0_SMP_AUTOZ_PD BIT(23)
+#define LNaRSCCR0_SMP_AUTOZ_CTRL GENMASK(19, 16)
+#define LNaRSCCR0_SMP_AUTOZ_D1R GENMASK(13, 12)
+#define LNaRSCCR0_SMP_AUTOZ_D1F GENMASK(9, 8)
+#define LNaRSCCR0_SMP_AUTOZ_EG1R GENMASK(5, 4)
+#define LNaRSCCR0_SMP_AUTOZ_EG1F GENMASK(1, 0)
#define LNaPSS(lane) (0x1000 + (lane) * 0x4)
#define LNaPSS_TYPE GENMASK(30, 24)
@@ -104,6 +154,12 @@
#define SGMIIaCR1(lane) (0x1804 + (lane) * 0x10)
#define SGMIIaCR1_SGPCS_EN BIT(11)
+enum lynx_28g_eq_type {
+ EQ_TYPE_NO_EQ = 0,
+ EQ_TYPE_2TAP = 1,
+ EQ_TYPE_3TAP = 2,
+};
+
struct lynx_28g_priv;
struct lynx_28g_pll {
@@ -151,6 +207,8 @@ static void lynx_28g_rmw(struct lynx_28g_priv *priv, unsigned long off,
lynx_28g_rmw((lane)->priv, reg(lane->id), val, mask)
#define lynx_28g_lane_read(lane, reg) \
ioread32((lane)->priv->base + reg((lane)->id))
+#define lynx_28g_lane_write(lane, reg, val) \
+ iowrite32(val, (lane)->priv->base + reg((lane)->id))
#define lynx_28g_pll_read(pll, reg) \
ioread32((pll)->priv->base + reg((pll)->id))
@@ -311,12 +369,22 @@ static void lynx_28g_lane_set_sgmii(struct lynx_28g_lane *lane)
SGMIIaCR1_SGPCS_EN);
/* Configure the appropriate equalization parameters for the protocol */
- iowrite32(0x00808006, priv->base + LNaTECR0(lane->id));
- iowrite32(0x04310000, priv->base + LNaRGCR1(lane->id));
- iowrite32(0x9f800000, priv->base + LNaRECR0(lane->id));
- iowrite32(0x001f0000, priv->base + LNaRECR1(lane->id));
- iowrite32(0x00000000, priv->base + LNaRECR2(lane->id));
- iowrite32(0x00000000, priv->base + LNaRSCCR0(lane->id));
+ lynx_28g_lane_write(lane, LNaTECR0,
+ LNaTECR0_EQ_SGN_PREQ | LNaTECR0_EQ_SGN_POST1Q |
+ FIELD_PREP(LNaTECR0_EQ_AMP_RED, 6));
+ lynx_28g_lane_write(lane, LNaRGCR1,
+ FIELD_PREP(LNaRGCR1_ENTER_IDLE_FLT_SEL, 4) |
+ FIELD_PREP(LNaRGCR1_EXIT_IDLE_FLT_SEL, 3) |
+ LNaRGCR1_DATA_LOST_FLT);
+ lynx_28g_lane_write(lane, LNaRECR0,
+ LNaRECR0_EQ_GAINK2_HF_OV_EN |
+ FIELD_PREP(LNaRECR0_EQ_GAINK2_HF_OV, 31) |
+ LNaRECR0_EQ_GAINK3_MF_OV_EN |
+ FIELD_PREP(LNaRECR0_EQ_GAINK3_MF_OV, 0));
+ lynx_28g_lane_write(lane, LNaRECR1,
+ FIELD_PREP(LNaRECR1_EQ_OFFSET_OV, 31));
+ lynx_28g_lane_write(lane, LNaRECR2, 0);
+ lynx_28g_lane_write(lane, LNaRSCCR0, 0);
}
static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane)
@@ -353,12 +421,22 @@ static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane)
lynx_28g_lane_rmw(lane, SGMIIaCR1, 0, SGMIIaCR1_SGPCS_EN);
/* Configure the appropriate equalization parameters for the protocol */
- iowrite32(0x10808307, priv->base + LNaTECR0(lane->id));
- iowrite32(0x10000000, priv->base + LNaRGCR1(lane->id));
- iowrite32(0x00000000, priv->base + LNaRECR0(lane->id));
- iowrite32(0x001f0000, priv->base + LNaRECR1(lane->id));
- iowrite32(0x81000020, priv->base + LNaRECR2(lane->id));
- iowrite32(0x00002000, priv->base + LNaRSCCR0(lane->id));
+ lynx_28g_lane_write(lane, LNaTECR0,
+ FIELD_PREP(LNaTECR0_EQ_TYPE, EQ_TYPE_2TAP) |
+ LNaTECR0_EQ_SGN_PREQ |
+ FIELD_PREP(LNaTECR0_EQ_PREQ, 0) |
+ LNaTECR0_EQ_SGN_POST1Q |
+ FIELD_PREP(LNaTECR0_EQ_POST1Q, 3) |
+ FIELD_PREP(LNaTECR0_EQ_AMP_RED, 7));
+ lynx_28g_lane_write(lane, LNaRGCR1, LNaRGCR1_IDLE_CONFIG);
+ lynx_28g_lane_write(lane, LNaRECR0, 0);
+ lynx_28g_lane_write(lane, LNaRECR1, FIELD_PREP(LNaRECR1_EQ_OFFSET_OV, 31));
+ lynx_28g_lane_write(lane, LNaRECR2,
+ LNaRECR2_EQ_OFFSET_RNG_DBL |
+ FIELD_PREP(LNaRECR2_EQ_BLW_SEL, 1) |
+ FIELD_PREP(LNaRECR2_EQ_BIN_DATA_AVG_TC, 2));
+ lynx_28g_lane_write(lane, LNaRSCCR0,
+ FIELD_PREP(LNaRSCCR0_SMP_AUTOZ_D1R, 2));
}
static int lynx_28g_power_off(struct phy *phy)
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v3 phy 05/17] phy: lynx-28g: restructure protocol configuration register accesses
2025-09-26 18:04 [PATCH v3 phy 00/17] Lynx 28G improvements part 1 Vladimir Oltean
` (3 preceding siblings ...)
2025-09-26 18:04 ` [PATCH v3 phy 04/17] phy: lynx-28g: convert iowrite32() calls with magic values to macros Vladimir Oltean
@ 2025-09-26 18:04 ` Vladimir Oltean
2025-09-26 18:04 ` [PATCH v3 phy 06/17] phy: lynx-28g: make lynx_28g_set_lane_mode() more systematic Vladimir Oltean
` (11 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Vladimir Oltean @ 2025-09-26 18:04 UTC (permalink / raw)
To: linux-phy
Cc: Ioana Ciornei, Vinod Koul, Kishon Vijay Abraham I, Josua Mayer,
linux-kernel
Eliminate the need to calculate a lane_offset manually, and generate
some macros which access the protocol converter corresponding to the
correct lane in the PCC* registers.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
v1->v3: none
drivers/phy/freescale/phy-fsl-lynx-28g.c | 55 ++++++++++++++----------
1 file changed, 33 insertions(+), 22 deletions(-)
diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
index 684cafb3d3e1..41a346ac38e2 100644
--- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
+++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
@@ -12,17 +12,32 @@
#define LYNX_28G_NUM_LANE 8
#define LYNX_28G_NUM_PLL 2
+#define LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1))
+
/* General registers per SerDes block */
#define PCC8 0x10a0
-#define PCC8_SGMII 0x1
-#define PCC8_SGMII_DIS 0x0
+#define PCC8_SGMIInCFG(lane, x) (((x) & GENMASK(2, 0)) << LNa_PCC_OFFSET(lane))
+#define PCC8_SGMIInCFG_EN(lane) PCC8_SGMIInCFG(lane, 1)
+#define PCC8_SGMIInCFG_MSK(lane) PCC8_SGMIInCFG(lane, GENMASK(2, 0))
+#define PCC8_SGMIIn_KX(lane, x) ((((x) << 3) & BIT(3)) << LNa_PCC_OFFSET(lane))
+#define PCC8_SGMIIn_KX_MSK(lane) PCC8_SGMIIn_KX(lane, 1)
+#define PCC8_MSK(lane) PCC8_SGMIInCFG_MSK(lane) | \
+ PCC8_SGMIIn_KX_MSK(lane)
#define PCCC 0x10b0
-#define PCCC_10GBASER 0x9
-#define PCCC_USXGMII 0x1
-#define PCCC_SXGMII_DIS 0x0
-
-#define LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1))
+#define PCCC_SXGMIInCFG(lane, x) (((x) & GENMASK(2, 0)) << LNa_PCC_OFFSET(lane))
+#define PCCC_SXGMIInCFG_EN(lane) PCCC_SXGMIInCFG(lane, 1)
+#define PCCC_SXGMIInCFG_MSK(lane) PCCC_SXGMIInCFG(lane, GENMASK(2, 0))
+#define PCCC_SXGMIInCFG_XFI(lane, x) ((((x) << 3) & BIT(3)) << LNa_PCC_OFFSET(lane))
+#define PCCC_SXGMIInCFG_XFI_MSK(lane) PCCC_SXGMIInCFG_XFI(lane, 1)
+#define PCCC_MSK(lane) PCCC_SXGMIInCFG_MSK(lane) | \
+ PCCC_SXGMIInCFG_XFI_MSK(lane)
+
+#define PCCD 0x10b4
+#define PCCD_E25GnCFG(lane, x) (((x) & GENMASK(2, 0)) << LNa_PCCD_OFFSET(lane))
+#define PCCD_E25GnCFG_EN(lane) PCCD_E25GnCFG(lane, 1)
+#define PCCD_E25GnCFG_MSK(lane) PCCD_E25GnCFG(lane, GENMASK(2, 0))
+#define PCCD_MSK(lane) PCCD_E25GnCFG_MSK(lane)
/* Per PLL registers */
#define PLLnRSTCTL(pll) (0x400 + (pll) * 0x100 + 0x0)
@@ -314,20 +329,21 @@ static void lynx_28g_lane_set_pll(struct lynx_28g_lane *lane,
static void lynx_28g_cleanup_lane(struct lynx_28g_lane *lane)
{
struct lynx_28g_priv *priv = lane->priv;
- u32 lane_offset = LNa_PCC_OFFSET(lane);
/* Cleanup the protocol configuration registers of the current protocol */
switch (lane->interface) {
case PHY_INTERFACE_MODE_10GBASER:
- lynx_28g_rmw(priv, PCCC,
- PCCC_SXGMII_DIS << lane_offset,
- GENMASK(3, 0) << lane_offset);
+ /* Cleanup the protocol configuration registers */
+ lynx_28g_rmw(priv, PCCC, 0, PCCC_MSK(lane));
break;
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_1000BASEX:
- lynx_28g_rmw(priv, PCC8,
- PCC8_SGMII_DIS << lane_offset,
- GENMASK(3, 0) << lane_offset);
+ /* Cleanup the protocol configuration registers */
+ lynx_28g_rmw(priv, PCC8, 0, PCC8_MSK(lane));
+
+ /* Disable the SGMII PCS */
+ lynx_28g_lane_rmw(lane, SGMIIaCR1, 0, SGMIIaCR1_SGPCS_EN);
+
break;
default:
break;
@@ -336,16 +352,13 @@ static void lynx_28g_cleanup_lane(struct lynx_28g_lane *lane)
static void lynx_28g_lane_set_sgmii(struct lynx_28g_lane *lane)
{
- u32 lane_offset = LNa_PCC_OFFSET(lane);
struct lynx_28g_priv *priv = lane->priv;
struct lynx_28g_pll *pll;
lynx_28g_cleanup_lane(lane);
/* Setup the lane to run in SGMII */
- lynx_28g_rmw(priv, PCC8,
- PCC8_SGMII << lane_offset,
- GENMASK(3, 0) << lane_offset);
+ lynx_28g_rmw(priv, PCC8, PCC8_SGMIInCFG_EN(lane), PCC8_MSK(lane));
/* Setup the protocol select and SerDes parallel interface width */
lynx_28g_lane_rmw(lane, LNaGCR0,
@@ -390,15 +403,13 @@ static void lynx_28g_lane_set_sgmii(struct lynx_28g_lane *lane)
static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane)
{
struct lynx_28g_priv *priv = lane->priv;
- u32 lane_offset = LNa_PCC_OFFSET(lane);
struct lynx_28g_pll *pll;
lynx_28g_cleanup_lane(lane);
/* Enable the SXGMII lane */
- lynx_28g_rmw(priv, PCCC,
- PCCC_10GBASER << lane_offset,
- GENMASK(3, 0) << lane_offset);
+ lynx_28g_rmw(priv, PCCC, PCCC_SXGMIInCFG_EN(lane) |
+ PCCC_SXGMIInCFG_XFI(lane, 1), PCCC_MSK(lane));
/* Setup the protocol select and SerDes parallel interface width */
lynx_28g_lane_rmw(lane, LNaGCR0,
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v3 phy 06/17] phy: lynx-28g: make lynx_28g_set_lane_mode() more systematic
2025-09-26 18:04 [PATCH v3 phy 00/17] Lynx 28G improvements part 1 Vladimir Oltean
` (4 preceding siblings ...)
2025-09-26 18:04 ` [PATCH v3 phy 05/17] phy: lynx-28g: restructure protocol configuration register accesses Vladimir Oltean
@ 2025-09-26 18:04 ` Vladimir Oltean
2025-09-26 18:04 ` [PATCH v3 phy 07/17] phy: lynx-28g: refactor lane->interface to lane->mode Vladimir Oltean
` (10 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Vladimir Oltean @ 2025-09-26 18:04 UTC (permalink / raw)
To: linux-phy
Cc: Ioana Ciornei, Vinod Koul, Kishon Vijay Abraham I, Josua Mayer,
linux-kernel
The current approach of transitioning from one SerDes protocol to
another in lynx_28g_set_lane_mode() is too poetic.
Because the driver only supports 1GbE and 10GbE, it only modifies those
registers which it knows are different between these two modes. However,
that is hardly extensible for 25GbE, 40GbE, backplane modes, etc.
We need something more systematic to make sure that all lane and
protocol converter registers are written to consistent values, no matter
what was the source lane mode.
For that, we need to introduce tables with register field values, for
each supported lane mode.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
v2->v3: none
v1->v2: fix LNaGCR0_PROTO_SEL | LNaGCR0_IF_WIDTH access by using
FIELD_PREP()
drivers/phy/freescale/phy-fsl-lynx-28g.c | 659 +++++++++++++++++------
1 file changed, 496 insertions(+), 163 deletions(-)
diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
index 41a346ac38e2..65eb00938b72 100644
--- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
+++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
@@ -12,32 +12,32 @@
#define LYNX_28G_NUM_LANE 8
#define LYNX_28G_NUM_PLL 2
-#define LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1))
-
-/* General registers per SerDes block */
+/* SoC IP wrapper for protocol converters */
#define PCC8 0x10a0
-#define PCC8_SGMIInCFG(lane, x) (((x) & GENMASK(2, 0)) << LNa_PCC_OFFSET(lane))
-#define PCC8_SGMIInCFG_EN(lane) PCC8_SGMIInCFG(lane, 1)
-#define PCC8_SGMIInCFG_MSK(lane) PCC8_SGMIInCFG(lane, GENMASK(2, 0))
-#define PCC8_SGMIIn_KX(lane, x) ((((x) << 3) & BIT(3)) << LNa_PCC_OFFSET(lane))
-#define PCC8_SGMIIn_KX_MSK(lane) PCC8_SGMIIn_KX(lane, 1)
-#define PCC8_MSK(lane) PCC8_SGMIInCFG_MSK(lane) | \
- PCC8_SGMIIn_KX_MSK(lane)
+#define PCC8_SGMIIa_KX BIT(3)
+#define PCC8_SGMIIa_CFG BIT(0)
#define PCCC 0x10b0
-#define PCCC_SXGMIInCFG(lane, x) (((x) & GENMASK(2, 0)) << LNa_PCC_OFFSET(lane))
-#define PCCC_SXGMIInCFG_EN(lane) PCCC_SXGMIInCFG(lane, 1)
-#define PCCC_SXGMIInCFG_MSK(lane) PCCC_SXGMIInCFG(lane, GENMASK(2, 0))
-#define PCCC_SXGMIInCFG_XFI(lane, x) ((((x) << 3) & BIT(3)) << LNa_PCC_OFFSET(lane))
-#define PCCC_SXGMIInCFG_XFI_MSK(lane) PCCC_SXGMIInCFG_XFI(lane, 1)
-#define PCCC_MSK(lane) PCCC_SXGMIInCFG_MSK(lane) | \
- PCCC_SXGMIInCFG_XFI_MSK(lane)
+#define PCCC_SXGMIIn_XFI BIT(3)
+#define PCCC_SXGMIIn_CFG BIT(0)
#define PCCD 0x10b4
-#define PCCD_E25GnCFG(lane, x) (((x) & GENMASK(2, 0)) << LNa_PCCD_OFFSET(lane))
-#define PCCD_E25GnCFG_EN(lane) PCCD_E25GnCFG(lane, 1)
-#define PCCD_E25GnCFG_MSK(lane) PCCD_E25GnCFG(lane, GENMASK(2, 0))
-#define PCCD_MSK(lane) PCCD_E25GnCFG_MSK(lane)
+#define PCCD_E25Gn_CFG BIT(0)
+
+#define PCCE 0x10b8
+#define PCCE_E40Gn_LRV BIT(3)
+#define PCCE_E40Gn_CFG BIT(0)
+#define PCCE_E50Gn_LRV BIT(3)
+#define PCCE_E50GnCFG BIT(0)
+#define PCCE_E100Gn_LRV BIT(3)
+#define PCCE_E100Gn_CFG BIT(0)
+
+#define SGMII_CFG(id) (28 - (id) * 4) /* Offset into PCC8 */
+#define SXGMII_CFG(id) (28 - (id) * 4) /* Offset into PCCC */
+#define E25G_CFG(id) (28 - (id) * 4) /* Offset into PCCD */
+#define E40G_CFG(id) (28 - (id) * 4) /* Offset into PCCE */
+#define E50G_CFG(id) (20 - (id) * 4) /* Offset into PCCE */
+#define E100G_CFG(id) (12 - (id) * 4) /* Offset into PCCE */
/* Per PLL registers */
#define PLLnRSTCTL(pll) (0x400 + (pll) * 0x100 + 0x0)
@@ -92,6 +92,10 @@
#define LNaTECR0_EQ_POST1Q GENMASK(12, 8)
#define LNaTECR0_EQ_AMP_RED GENMASK(5, 0)
+#define LNaTECR1(lane) (0x800 + (lane) * 0x100 + 0x34)
+#define LNaTECR1_EQ_ADPT_EQ_DRVR_DIS BIT(31)
+#define LNaTECR1_EQ_ADPT_EQ GENMASK(29, 24)
+
/* Lane a Rx Reset Control Register */
#define LNaRRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x40)
#define LNaRRSTCTL_HLT_REQ BIT(27)
@@ -147,6 +151,21 @@
#define LNaRECR2_EQ_BIN_DATA_AVG_TC GENMASK(5, 4)
#define LNaRECR2_SPARE_IN GENMASK(1, 0)
+#define LNaRECR3(lane) (0x800 + (lane) * 0x100 + 0x5c)
+#define LNaRECR3_EQ_SNAP_START BIT(31)
+#define LNaRECR3_EQ_SNAP_DONE BIT(30)
+#define LNaRECR3_EQ_GAINK2_HF_STAT GENMASK(28, 24)
+#define LNaRECR3_EQ_GAINK3_MF_STAT GENMASK(20, 16)
+#define LNaRECR3_SPARE_OUT GENMASK(13, 12)
+#define LNaRECR3_EQ_GAINK4_LF_STAT GENMASK(4, 0)
+
+#define LNaRECR4(lane) (0x800 + (lane) * 0x100 + 0x60)
+#define LNaRECR4_BLW_STAT GENMASK(28, 24)
+#define LNaRECR4_EQ_OFFSET_STAT GENMASK(21, 16)
+#define LNaRECR4_EQ_BIN_DATA_SEL GENMASK(15, 12)
+#define LNaRECR4_EQ_BIN_DATA GENMASK(8, 0) /* bit 9 is reserved */
+#define LNaRECR4_EQ_BIN_DATA_SGN BIT(8)
+
#define LNaRSCCR0(lane) (0x800 + (lane) * 0x100 + 0x74)
#define LNaRSCCR0_SMP_OFF_EN BIT(31)
#define LNaRSCCR0_SMP_OFF_OV_EN BIT(30)
@@ -161,20 +180,199 @@
#define LNaRSCCR0_SMP_AUTOZ_EG1R GENMASK(5, 4)
#define LNaRSCCR0_SMP_AUTOZ_EG1F GENMASK(1, 0)
+#define LNaTCSR0(lane) (0x800 + (lane) * 0x100 + 0xa0)
+#define LNaTCSR0_SD_STAT_OBS_EN BIT(31)
+#define LNaTCSR0_SD_LPBK_SEL GENMASK(29, 28)
+
#define LNaPSS(lane) (0x1000 + (lane) * 0x4)
#define LNaPSS_TYPE GENMASK(30, 24)
-#define LNaPSS_TYPE_SGMII 0x4
-#define LNaPSS_TYPE_XFI 0x28
+#define LNaPSS_TYPE_SGMII (PROTO_SEL_SGMII_BASEX_KX << 2)
+#define LNaPSS_TYPE_XFI (PROTO_SEL_XFI_10GBASER_KR_SXGMII << 2)
+#define LNaPSS_TYPE_40G ((PROTO_SEL_XFI_10GBASER_KR_SXGMII << 2) | 3)
+#define LNaPSS_TYPE_25G (PROTO_SEL_25G_50G_100G << 2)
+#define LNaPSS_TYPE_100G ((PROTO_SEL_25G_50G_100G << 2) | 2)
+/* MDEV_PORT is at the same bitfield address for all protocol converters */
+#define MDEV_PORT GENMASK(31, 27)
+
+#define SGMIIaCR0(lane) (0x1800 + (lane) * 0x10)
#define SGMIIaCR1(lane) (0x1804 + (lane) * 0x10)
#define SGMIIaCR1_SGPCS_EN BIT(11)
+#define ANLTaCR0(lane) (0x1a00 + (lane) * 0x10)
+#define ANLTaCR1(lane) (0x1a04 + (lane) * 0x10)
+
+#define SXGMIIaCR0(lane) (0x1a80 + (lane) * 0x10)
+#define SXGMIIaCR0_RST BIT(31)
+#define SXGMIIaCR0_PD BIT(30)
+
+#define SXGMIIaCR1(lane) (0x1a84 + (lane) * 0x10)
+
+#define E25GaCR0(lane) (0x1b00 + (lane) * 0x10)
+#define E25GaCR0_RST BIT(31)
+#define E25GaCR0_PD BIT(30)
+
+#define E25GaCR1(lane) (0x1b04 + (lane) * 0x10)
+
+#define E25GaCR2(lane) (0x1b08 + (lane) * 0x10)
+#define E25GaCR2_FEC_ENA BIT(23)
+#define E25GaCR2_FEC_ERR_ENA BIT(22)
+#define E25GaCR2_FEC91_ENA BIT(20)
+
+#define E40GaCR0(pcvt) (0x1b40 + (pcvt) * 0x20)
+#define E40GaCR1(pcvt) (0x1b44 + (pcvt) * 0x20)
+
+#define E50GaCR1(pcvt) (0x1b84 + (pcvt) * 0x10)
+
+#define E100GaCR1(pcvt) (0x1c04 + (pcvt) * 0x20)
+
+#define CR(x) ((x) * 4)
+
enum lynx_28g_eq_type {
EQ_TYPE_NO_EQ = 0,
EQ_TYPE_2TAP = 1,
EQ_TYPE_3TAP = 2,
};
+enum lynx_28g_proto_sel {
+ PROTO_SEL_PCIE = 0,
+ PROTO_SEL_SGMII_BASEX_KX = 1,
+ PROTO_SEL_SATA = 2,
+ PROTO_SEL_XAUI = 4,
+ PROTO_SEL_XFI_10GBASER_KR_SXGMII = 0xa,
+ PROTO_SEL_25G_50G_100G = 0x1a,
+};
+
+struct lynx_28g_proto_conf {
+ /* LNaGCR0 */
+ int proto_sel;
+ int if_width;
+ /* LNaTECR0 */
+ int teq_type;
+ int sgn_preq;
+ int ratio_preq;
+ int sgn_post1q;
+ int ratio_post1q;
+ int amp_red;
+ /* LNaTECR1 */
+ int adpt_eq;
+ /* LNaRGCR1 */
+ int enter_idle_flt_sel;
+ int exit_idle_flt_sel;
+ int data_lost_th_sel;
+ /* LNaRECR0 */
+ int gk2ovd;
+ int gk3ovd;
+ int gk4ovd;
+ int gk2ovd_en;
+ int gk3ovd_en;
+ int gk4ovd_en;
+ /* LNaRECR1 ? */
+ int eq_offset_ovd;
+ int eq_offset_ovd_en;
+ /* LNaRECR2 */
+ int eq_offset_rng_dbl;
+ int eq_blw_sel;
+ int eq_boost;
+ int spare_in;
+ /* LNaRSCCR0 */
+ int smp_autoz_d1r;
+ int smp_autoz_eg1r;
+};
+
+static const struct lynx_28g_proto_conf lynx_28g_proto_conf[PHY_INTERFACE_MODE_MAX] = {
+ [PHY_INTERFACE_MODE_SGMII] = {
+ .proto_sel = LNaGCR0_PROTO_SEL_SGMII,
+ .if_width = LNaGCR0_IF_WIDTH_10_BIT,
+ .teq_type = EQ_TYPE_NO_EQ,
+ .sgn_preq = 1,
+ .ratio_preq = 0,
+ .sgn_post1q = 1,
+ .ratio_post1q = 0,
+ .amp_red = 6,
+ .adpt_eq = 48,
+ .enter_idle_flt_sel = 4,
+ .exit_idle_flt_sel = 3,
+ .data_lost_th_sel = 1,
+ .gk2ovd = 0x1f,
+ .gk3ovd = 0,
+ .gk4ovd = 0,
+ .gk2ovd_en = 1,
+ .gk3ovd_en = 1,
+ .gk4ovd_en = 0,
+ .eq_offset_ovd = 0x1f,
+ .eq_offset_ovd_en = 0,
+ .eq_offset_rng_dbl = 0,
+ .eq_blw_sel = 0,
+ .eq_boost = 0,
+ .spare_in = 0,
+ .smp_autoz_d1r = 0,
+ .smp_autoz_eg1r = 0,
+ },
+ [PHY_INTERFACE_MODE_1000BASEX] = {
+ .proto_sel = LNaGCR0_PROTO_SEL_SGMII,
+ .if_width = LNaGCR0_IF_WIDTH_10_BIT,
+ .teq_type = EQ_TYPE_NO_EQ,
+ .sgn_preq = 1,
+ .ratio_preq = 0,
+ .sgn_post1q = 1,
+ .ratio_post1q = 0,
+ .amp_red = 6,
+ .adpt_eq = 48,
+ .enter_idle_flt_sel = 4,
+ .exit_idle_flt_sel = 3,
+ .data_lost_th_sel = 1,
+ .gk2ovd = 0x1f,
+ .gk3ovd = 0,
+ .gk4ovd = 0,
+ .gk2ovd_en = 1,
+ .gk3ovd_en = 1,
+ .gk4ovd_en = 0,
+ .eq_offset_ovd = 0x1f,
+ .eq_offset_ovd_en = 0,
+ .eq_offset_rng_dbl = 0,
+ .eq_blw_sel = 0,
+ .eq_boost = 0,
+ .spare_in = 0,
+ .smp_autoz_d1r = 0,
+ .smp_autoz_eg1r = 0,
+ },
+ [PHY_INTERFACE_MODE_10GBASER] = {
+ .proto_sel = LNaGCR0_PROTO_SEL_XFI,
+ .if_width = LNaGCR0_IF_WIDTH_20_BIT,
+ .teq_type = EQ_TYPE_2TAP,
+ .sgn_preq = 1,
+ .ratio_preq = 0,
+ .sgn_post1q = 1,
+ .ratio_post1q = 3,
+ .amp_red = 7,
+ .adpt_eq = 48,
+ .enter_idle_flt_sel = 0,
+ .exit_idle_flt_sel = 0,
+ .data_lost_th_sel = 0,
+ .gk2ovd = 0,
+ .gk3ovd = 0,
+ .gk4ovd = 0,
+ .gk2ovd_en = 0,
+ .gk3ovd_en = 0,
+ .gk4ovd_en = 0,
+ .eq_offset_ovd = 0x1f,
+ .eq_offset_ovd_en = 0,
+ .eq_offset_rng_dbl = 1,
+ .eq_blw_sel = 1,
+ .eq_boost = 0,
+ .spare_in = 0,
+ .smp_autoz_d1r = 2,
+ .smp_autoz_eg1r = 0,
+ },
+};
+
+struct lynx_pccr {
+ int offset;
+ int width;
+ int shift;
+};
+
struct lynx_28g_priv;
struct lynx_28g_pll {
@@ -218,6 +416,10 @@ static void lynx_28g_rmw(struct lynx_28g_priv *priv, unsigned long off,
iowrite32(tmp, reg);
}
+#define lynx_28g_read(priv, off) \
+ ioread32((priv)->base + (off))
+#define lynx_28g_write(priv, off, val) \
+ iowrite32(val, (priv)->base + (off))
#define lynx_28g_lane_rmw(lane, reg, val, mask) \
lynx_28g_rmw((lane)->priv, reg(lane->id), val, mask)
#define lynx_28g_lane_read(lane, reg) \
@@ -326,130 +528,6 @@ static void lynx_28g_lane_set_pll(struct lynx_28g_lane *lane,
}
}
-static void lynx_28g_cleanup_lane(struct lynx_28g_lane *lane)
-{
- struct lynx_28g_priv *priv = lane->priv;
-
- /* Cleanup the protocol configuration registers of the current protocol */
- switch (lane->interface) {
- case PHY_INTERFACE_MODE_10GBASER:
- /* Cleanup the protocol configuration registers */
- lynx_28g_rmw(priv, PCCC, 0, PCCC_MSK(lane));
- break;
- case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_1000BASEX:
- /* Cleanup the protocol configuration registers */
- lynx_28g_rmw(priv, PCC8, 0, PCC8_MSK(lane));
-
- /* Disable the SGMII PCS */
- lynx_28g_lane_rmw(lane, SGMIIaCR1, 0, SGMIIaCR1_SGPCS_EN);
-
- break;
- default:
- break;
- }
-}
-
-static void lynx_28g_lane_set_sgmii(struct lynx_28g_lane *lane)
-{
- struct lynx_28g_priv *priv = lane->priv;
- struct lynx_28g_pll *pll;
-
- lynx_28g_cleanup_lane(lane);
-
- /* Setup the lane to run in SGMII */
- lynx_28g_rmw(priv, PCC8, PCC8_SGMIInCFG_EN(lane), PCC8_MSK(lane));
-
- /* Setup the protocol select and SerDes parallel interface width */
- lynx_28g_lane_rmw(lane, LNaGCR0,
- FIELD_PREP(LNaGCR0_PROTO_SEL, LNaGCR0_PROTO_SEL_SGMII) |
- FIELD_PREP(LNaGCR0_IF_WIDTH, LNaGCR0_IF_WIDTH_10_BIT),
- LNaGCR0_PROTO_SEL | LNaGCR0_IF_WIDTH);
-
- /* Find the PLL that works with this interface type */
- pll = lynx_28g_pll_get(priv, PHY_INTERFACE_MODE_SGMII);
- if (unlikely(pll == NULL))
- return;
-
- /* Switch to the PLL that works with this interface type */
- lynx_28g_lane_set_pll(lane, pll);
-
- /* Choose the portion of clock net to be used on this lane */
- lynx_28g_lane_set_nrate(lane, pll, PHY_INTERFACE_MODE_SGMII);
-
- /* Enable the SGMII PCS */
- lynx_28g_lane_rmw(lane, SGMIIaCR1, SGMIIaCR1_SGPCS_EN,
- SGMIIaCR1_SGPCS_EN);
-
- /* Configure the appropriate equalization parameters for the protocol */
- lynx_28g_lane_write(lane, LNaTECR0,
- LNaTECR0_EQ_SGN_PREQ | LNaTECR0_EQ_SGN_POST1Q |
- FIELD_PREP(LNaTECR0_EQ_AMP_RED, 6));
- lynx_28g_lane_write(lane, LNaRGCR1,
- FIELD_PREP(LNaRGCR1_ENTER_IDLE_FLT_SEL, 4) |
- FIELD_PREP(LNaRGCR1_EXIT_IDLE_FLT_SEL, 3) |
- LNaRGCR1_DATA_LOST_FLT);
- lynx_28g_lane_write(lane, LNaRECR0,
- LNaRECR0_EQ_GAINK2_HF_OV_EN |
- FIELD_PREP(LNaRECR0_EQ_GAINK2_HF_OV, 31) |
- LNaRECR0_EQ_GAINK3_MF_OV_EN |
- FIELD_PREP(LNaRECR0_EQ_GAINK3_MF_OV, 0));
- lynx_28g_lane_write(lane, LNaRECR1,
- FIELD_PREP(LNaRECR1_EQ_OFFSET_OV, 31));
- lynx_28g_lane_write(lane, LNaRECR2, 0);
- lynx_28g_lane_write(lane, LNaRSCCR0, 0);
-}
-
-static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane)
-{
- struct lynx_28g_priv *priv = lane->priv;
- struct lynx_28g_pll *pll;
-
- lynx_28g_cleanup_lane(lane);
-
- /* Enable the SXGMII lane */
- lynx_28g_rmw(priv, PCCC, PCCC_SXGMIInCFG_EN(lane) |
- PCCC_SXGMIInCFG_XFI(lane, 1), PCCC_MSK(lane));
-
- /* Setup the protocol select and SerDes parallel interface width */
- lynx_28g_lane_rmw(lane, LNaGCR0,
- FIELD_PREP(LNaGCR0_PROTO_SEL, LNaGCR0_PROTO_SEL_XFI) |
- FIELD_PREP(LNaGCR0_IF_WIDTH, LNaGCR0_IF_WIDTH_20_BIT),
- LNaGCR0_PROTO_SEL | LNaGCR0_IF_WIDTH);
-
- /* Find the PLL that works with this interface type */
- pll = lynx_28g_pll_get(priv, PHY_INTERFACE_MODE_10GBASER);
- if (unlikely(pll == NULL))
- return;
-
- /* Switch to the PLL that works with this interface type */
- lynx_28g_lane_set_pll(lane, pll);
-
- /* Choose the portion of clock net to be used on this lane */
- lynx_28g_lane_set_nrate(lane, pll, PHY_INTERFACE_MODE_10GBASER);
-
- /* Disable the SGMII PCS */
- lynx_28g_lane_rmw(lane, SGMIIaCR1, 0, SGMIIaCR1_SGPCS_EN);
-
- /* Configure the appropriate equalization parameters for the protocol */
- lynx_28g_lane_write(lane, LNaTECR0,
- FIELD_PREP(LNaTECR0_EQ_TYPE, EQ_TYPE_2TAP) |
- LNaTECR0_EQ_SGN_PREQ |
- FIELD_PREP(LNaTECR0_EQ_PREQ, 0) |
- LNaTECR0_EQ_SGN_POST1Q |
- FIELD_PREP(LNaTECR0_EQ_POST1Q, 3) |
- FIELD_PREP(LNaTECR0_EQ_AMP_RED, 7));
- lynx_28g_lane_write(lane, LNaRGCR1, LNaRGCR1_IDLE_CONFIG);
- lynx_28g_lane_write(lane, LNaRECR0, 0);
- lynx_28g_lane_write(lane, LNaRECR1, FIELD_PREP(LNaRECR1_EQ_OFFSET_OV, 31));
- lynx_28g_lane_write(lane, LNaRECR2,
- LNaRECR2_EQ_OFFSET_RNG_DBL |
- FIELD_PREP(LNaRECR2_EQ_BLW_SEL, 1) |
- FIELD_PREP(LNaRECR2_EQ_BIN_DATA_AVG_TC, 2));
- lynx_28g_lane_write(lane, LNaRSCCR0,
- FIELD_PREP(LNaRSCCR0_SMP_AUTOZ_D1R, 2));
-}
-
static int lynx_28g_power_off(struct phy *phy)
{
struct lynx_28g_lane *lane = phy_get_drvdata(phy);
@@ -502,6 +580,268 @@ static int lynx_28g_power_on(struct phy *phy)
return 0;
}
+static int lynx_28g_get_pccr(phy_interface_t interface, int lane,
+ struct lynx_pccr *pccr)
+{
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ pccr->offset = PCC8;
+ pccr->width = 4;
+ pccr->shift = SGMII_CFG(lane);
+ break;
+ case PHY_INTERFACE_MODE_10GBASER:
+ pccr->offset = PCCC;
+ pccr->width = 4;
+ pccr->shift = SXGMII_CFG(lane);
+ break;
+ default:
+ return -EOPNOTSUPP;
+ }
+
+ return 0;
+}
+
+static int lynx_28g_get_pcvt_offset(int lane, phy_interface_t interface)
+{
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ return SGMIIaCR0(lane);
+ case PHY_INTERFACE_MODE_10GBASER:
+ return SXGMIIaCR0(lane);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int lynx_pccr_write(struct lynx_28g_lane *lane,
+ phy_interface_t interface, u32 val)
+{
+ struct lynx_28g_priv *priv = lane->priv;
+ struct lynx_pccr pccr;
+ u32 old, tmp, mask;
+ int err;
+
+ err = lynx_28g_get_pccr(interface, lane->id, &pccr);
+ if (err)
+ return err;
+
+ old = lynx_28g_read(priv, pccr.offset);
+ mask = GENMASK(pccr.width - 1, 0) << pccr.shift;
+ tmp = (old & ~mask) | (val << pccr.shift);
+ lynx_28g_write(priv, pccr.offset, tmp);
+
+ dev_dbg(&lane->phy->dev, "PCCR@0x%x: 0x%x -> 0x%x\n",
+ pccr.offset, old, tmp);
+
+ return 0;
+}
+
+static int lynx_pcvt_read(struct lynx_28g_lane *lane, phy_interface_t interface,
+ int cr, u32 *val)
+{
+ struct lynx_28g_priv *priv = lane->priv;
+ int offset;
+
+ offset = lynx_28g_get_pcvt_offset(lane->id, interface);
+ if (offset < 0)
+ return offset;
+
+ *val = lynx_28g_read(priv, offset + cr);
+
+ return 0;
+}
+
+static int lynx_pcvt_write(struct lynx_28g_lane *lane, phy_interface_t interface,
+ int cr, u32 val)
+{
+ struct lynx_28g_priv *priv = lane->priv;
+ int offset;
+
+ offset = lynx_28g_get_pcvt_offset(lane->id, interface);
+ if (offset < 0)
+ return offset;
+
+ lynx_28g_write(priv, offset + cr, val);
+
+ return 0;
+}
+
+static int lynx_pcvt_rmw(struct lynx_28g_lane *lane, phy_interface_t interface,
+ int cr, u32 val, u32 mask)
+{
+ int err;
+ u32 tmp;
+
+ err = lynx_pcvt_read(lane, interface, cr, &tmp);
+ if (err)
+ return err;
+
+ tmp &= ~mask;
+ tmp |= val;
+
+ return lynx_pcvt_write(lane, interface, cr, tmp);
+}
+
+static void lynx_28g_lane_remap_pll(struct lynx_28g_lane *lane,
+ phy_interface_t interface)
+{
+ struct lynx_28g_priv *priv = lane->priv;
+ struct lynx_28g_pll *pll;
+
+ /* Switch to the PLL that works with this interface type */
+ pll = lynx_28g_pll_get(priv, interface);
+ if (unlikely(pll == NULL))
+ return;
+
+ lynx_28g_lane_set_pll(lane, pll);
+
+ /* Choose the portion of clock net to be used on this lane */
+ lynx_28g_lane_set_nrate(lane, pll, interface);
+}
+
+static void lynx_28g_lane_change_proto_conf(struct lynx_28g_lane *lane,
+ phy_interface_t interface)
+{
+ const struct lynx_28g_proto_conf *conf = &lynx_28g_proto_conf[interface];
+
+ lynx_28g_lane_rmw(lane, LNaGCR0,
+ FIELD_PREP(LNaGCR0_PROTO_SEL, conf->proto_sel) |
+ FIELD_PREP(LNaGCR0_IF_WIDTH, conf->if_width),
+ LNaGCR0_PROTO_SEL | LNaGCR0_IF_WIDTH);
+
+ lynx_28g_lane_rmw(lane, LNaTECR0,
+ FIELD_PREP(LNaTECR0_EQ_TYPE, conf->teq_type) |
+ FIELD_PREP(LNaTECR0_EQ_SGN_PREQ, conf->sgn_preq) |
+ FIELD_PREP(LNaTECR0_EQ_PREQ, conf->ratio_preq) |
+ FIELD_PREP(LNaTECR0_EQ_SGN_POST1Q, conf->sgn_post1q) |
+ FIELD_PREP(LNaTECR0_EQ_POST1Q, conf->ratio_post1q) |
+ FIELD_PREP(LNaTECR0_EQ_AMP_RED, conf->amp_red),
+ LNaTECR0_EQ_TYPE |
+ LNaTECR0_EQ_SGN_PREQ |
+ LNaTECR0_EQ_PREQ |
+ LNaTECR0_EQ_SGN_POST1Q |
+ LNaTECR0_EQ_POST1Q |
+ LNaTECR0_EQ_AMP_RED);
+
+ lynx_28g_lane_rmw(lane, LNaTECR1,
+ FIELD_PREP(LNaTECR1_EQ_ADPT_EQ, conf->adpt_eq),
+ LNaTECR1_EQ_ADPT_EQ);
+
+ lynx_28g_lane_rmw(lane, LNaRGCR1,
+ FIELD_PREP(LNaRGCR1_ENTER_IDLE_FLT_SEL, conf->enter_idle_flt_sel) |
+ FIELD_PREP(LNaRGCR1_EXIT_IDLE_FLT_SEL, conf->exit_idle_flt_sel) |
+ FIELD_PREP(LNaRGCR1_DATA_LOST_TH_SEL, conf->data_lost_th_sel),
+ LNaRGCR1_ENTER_IDLE_FLT_SEL |
+ LNaRGCR1_EXIT_IDLE_FLT_SEL |
+ LNaRGCR1_DATA_LOST_TH_SEL);
+
+ lynx_28g_lane_rmw(lane, LNaRECR0,
+ FIELD_PREP(LNaRECR0_EQ_GAINK2_HF_OV_EN, conf->gk2ovd_en) |
+ FIELD_PREP(LNaRECR0_EQ_GAINK3_MF_OV_EN, conf->gk3ovd_en) |
+ FIELD_PREP(LNaRECR0_EQ_GAINK4_LF_OV_EN, conf->gk4ovd_en) |
+ FIELD_PREP(LNaRECR0_EQ_GAINK2_HF_OV, conf->gk2ovd) |
+ FIELD_PREP(LNaRECR0_EQ_GAINK3_MF_OV, conf->gk3ovd) |
+ FIELD_PREP(LNaRECR0_EQ_GAINK4_LF_OV, conf->gk4ovd),
+ LNaRECR0_EQ_GAINK2_HF_OV |
+ LNaRECR0_EQ_GAINK3_MF_OV |
+ LNaRECR0_EQ_GAINK4_LF_OV |
+ LNaRECR0_EQ_GAINK2_HF_OV_EN |
+ LNaRECR0_EQ_GAINK3_MF_OV_EN |
+ LNaRECR0_EQ_GAINK4_LF_OV_EN);
+
+ lynx_28g_lane_rmw(lane, LNaRECR1,
+ FIELD_PREP(LNaRECR1_EQ_OFFSET_OV, conf->eq_offset_ovd) |
+ FIELD_PREP(LNaRECR1_EQ_OFFSET_OV_EN, conf->eq_offset_ovd_en),
+ LNaRECR1_EQ_OFFSET_OV |
+ LNaRECR1_EQ_OFFSET_OV_EN);
+
+ lynx_28g_lane_rmw(lane, LNaRECR2,
+ FIELD_PREP(LNaRECR2_EQ_OFFSET_RNG_DBL, conf->eq_offset_rng_dbl) |
+ FIELD_PREP(LNaRECR2_EQ_BLW_SEL, conf->eq_blw_sel) |
+ FIELD_PREP(LNaRECR2_EQ_BOOST, conf->eq_boost) |
+ FIELD_PREP(LNaRECR2_SPARE_IN, conf->spare_in),
+ LNaRECR2_EQ_OFFSET_RNG_DBL |
+ LNaRECR2_EQ_BLW_SEL |
+ LNaRECR2_EQ_BOOST |
+ LNaRECR2_SPARE_IN);
+
+ lynx_28g_lane_rmw(lane, LNaRSCCR0,
+ FIELD_PREP(LNaRSCCR0_SMP_AUTOZ_D1R, conf->smp_autoz_d1r) |
+ FIELD_PREP(LNaRSCCR0_SMP_AUTOZ_EG1R, conf->smp_autoz_eg1r),
+ LNaRSCCR0_SMP_AUTOZ_D1R |
+ LNaRSCCR0_SMP_AUTOZ_EG1R);
+}
+
+static int lynx_28g_lane_disable_pcvt(struct lynx_28g_lane *lane,
+ phy_interface_t interface)
+{
+ struct lynx_28g_priv *priv = lane->priv;
+ int err;
+
+ spin_lock(&priv->pcc_lock);
+
+ err = lynx_pccr_write(lane, interface, 0);
+ if (err)
+ goto out;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ err = lynx_pcvt_rmw(lane, interface, CR(1), 0,
+ SGMIIaCR1_SGPCS_EN);
+ break;
+ default:
+ err = 0;
+ }
+
+out:
+ spin_unlock(&priv->pcc_lock);
+
+ return err;
+}
+
+static int lynx_28g_lane_enable_pcvt(struct lynx_28g_lane *lane,
+ phy_interface_t interface)
+{
+ struct lynx_28g_priv *priv = lane->priv;
+ u32 val;
+ int err;
+
+ spin_lock(&priv->pcc_lock);
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ err = lynx_pcvt_rmw(lane, interface, CR(1), SGMIIaCR1_SGPCS_EN,
+ SGMIIaCR1_SGPCS_EN);
+ break;
+ default:
+ err = 0;
+ }
+
+ val = 0;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ val |= PCC8_SGMIIa_CFG;
+ break;
+ case PHY_INTERFACE_MODE_10GBASER:
+ val |= PCCC_SXGMIIn_CFG | PCCC_SXGMIIn_XFI;
+ break;
+ default:
+ break;
+ }
+
+ err = lynx_pccr_write(lane, interface, val);
+
+ spin_unlock(&priv->pcc_lock);
+
+ return err;
+}
+
static int lynx_28g_set_mode(struct phy *phy, enum phy_mode mode, int submode)
{
struct lynx_28g_lane *lane = phy_get_drvdata(phy);
@@ -518,33 +858,26 @@ static int lynx_28g_set_mode(struct phy *phy, enum phy_mode mode, int submode)
if (!lynx_28g_supports_interface(priv, submode))
return -EOPNOTSUPP;
+ if (submode == lane->interface)
+ return 0;
+
/* If the lane is powered up, put the lane into the halt state while
* the reconfiguration is being done.
*/
if (powered_up)
lynx_28g_power_off(phy);
- spin_lock(&priv->pcc_lock);
-
- switch (submode) {
- case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_1000BASEX:
- lynx_28g_lane_set_sgmii(lane);
- break;
- case PHY_INTERFACE_MODE_10GBASER:
- lynx_28g_lane_set_10gbaser(lane);
- break;
- default:
- err = -EOPNOTSUPP;
+ err = lynx_28g_lane_disable_pcvt(lane, lane->interface);
+ if (err)
goto out;
- }
+
+ lynx_28g_lane_change_proto_conf(lane, submode);
+ lynx_28g_lane_remap_pll(lane, submode);
+ WARN_ON(lynx_28g_lane_enable_pcvt(lane, submode));
lane->interface = submode;
out:
- spin_unlock(&priv->pcc_lock);
-
- /* Power up the lane if necessary */
if (powered_up)
lynx_28g_power_on(phy);
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v3 phy 07/17] phy: lynx-28g: refactor lane->interface to lane->mode
2025-09-26 18:04 [PATCH v3 phy 00/17] Lynx 28G improvements part 1 Vladimir Oltean
` (5 preceding siblings ...)
2025-09-26 18:04 ` [PATCH v3 phy 06/17] phy: lynx-28g: make lynx_28g_set_lane_mode() more systematic Vladimir Oltean
@ 2025-09-26 18:04 ` Vladimir Oltean
2025-09-26 18:04 ` [PATCH v3 phy 08/17] phy: lynx-28g: distinguish between 10GBASE-R and USXGMII Vladimir Oltean
` (9 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Vladimir Oltean @ 2025-09-26 18:04 UTC (permalink / raw)
To: linux-phy
Cc: Ioana Ciornei, Vinod Koul, Kishon Vijay Abraham I, Josua Mayer,
linux-kernel
Lynx 28G is a multi-protocol SerDes - it handles serial Ethernet, PCIe,
SATA.
The driver should not use the phylib-specific phy_interface_t as an
internal data representation, but something specific to its internal
capabilities, and only convert to phy_interface_t when PHY_MODE_ETHERNET
is selected and used.
Otherwise it has no way of representing the non-Ethernet lanes (which
was not a short-term goal when the driver was introduced, and is not a
goal per se right now either, but should nonetheless be possible).
Prefer the "enum lynx_lane_mode" name over "lynx_28g_lane_mode", in
preparation of future Lynx 10G SerDes support. This SerDes is part of
the same IP family and has similar capabilities, and will reuse some
code, hence the common data type.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
v2->v3:
- fix lynx_28g_set_mode() by using lane_mode instead of submode
- save lane_mode to local variable in lynx_28g_set_mode()
v1->v2: none
drivers/phy/freescale/phy-fsl-lynx-28g.c | 208 ++++++++++++-----------
1 file changed, 106 insertions(+), 102 deletions(-)
diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
index 65eb00938b72..7ef81f26bee8 100644
--- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
+++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
@@ -243,6 +243,13 @@ enum lynx_28g_proto_sel {
PROTO_SEL_25G_50G_100G = 0x1a,
};
+enum lynx_lane_mode {
+ LANE_MODE_UNKNOWN,
+ LANE_MODE_1000BASEX_SGMII,
+ LANE_MODE_10GBASER_USXGMII,
+ LANE_MODE_MAX,
+};
+
struct lynx_28g_proto_conf {
/* LNaGCR0 */
int proto_sel;
@@ -280,8 +287,8 @@ struct lynx_28g_proto_conf {
int smp_autoz_eg1r;
};
-static const struct lynx_28g_proto_conf lynx_28g_proto_conf[PHY_INTERFACE_MODE_MAX] = {
- [PHY_INTERFACE_MODE_SGMII] = {
+static const struct lynx_28g_proto_conf lynx_28g_proto_conf[LANE_MODE_MAX] = {
+ [LANE_MODE_1000BASEX_SGMII] = {
.proto_sel = LNaGCR0_PROTO_SEL_SGMII,
.if_width = LNaGCR0_IF_WIDTH_10_BIT,
.teq_type = EQ_TYPE_NO_EQ,
@@ -309,35 +316,7 @@ static const struct lynx_28g_proto_conf lynx_28g_proto_conf[PHY_INTERFACE_MODE_M
.smp_autoz_d1r = 0,
.smp_autoz_eg1r = 0,
},
- [PHY_INTERFACE_MODE_1000BASEX] = {
- .proto_sel = LNaGCR0_PROTO_SEL_SGMII,
- .if_width = LNaGCR0_IF_WIDTH_10_BIT,
- .teq_type = EQ_TYPE_NO_EQ,
- .sgn_preq = 1,
- .ratio_preq = 0,
- .sgn_post1q = 1,
- .ratio_post1q = 0,
- .amp_red = 6,
- .adpt_eq = 48,
- .enter_idle_flt_sel = 4,
- .exit_idle_flt_sel = 3,
- .data_lost_th_sel = 1,
- .gk2ovd = 0x1f,
- .gk3ovd = 0,
- .gk4ovd = 0,
- .gk2ovd_en = 1,
- .gk3ovd_en = 1,
- .gk4ovd_en = 0,
- .eq_offset_ovd = 0x1f,
- .eq_offset_ovd_en = 0,
- .eq_offset_rng_dbl = 0,
- .eq_blw_sel = 0,
- .eq_boost = 0,
- .spare_in = 0,
- .smp_autoz_d1r = 0,
- .smp_autoz_eg1r = 0,
- },
- [PHY_INTERFACE_MODE_10GBASER] = {
+ [LANE_MODE_10GBASER_USXGMII] = {
.proto_sel = LNaGCR0_PROTO_SEL_XFI,
.if_width = LNaGCR0_IF_WIDTH_20_BIT,
.teq_type = EQ_TYPE_2TAP,
@@ -379,7 +358,7 @@ struct lynx_28g_pll {
struct lynx_28g_priv *priv;
u32 rstctl, cr0, cr1;
int id;
- DECLARE_PHY_INTERFACE_MASK(supported);
+ DECLARE_BITMAP(supported, LANE_MODE_MAX);
};
struct lynx_28g_lane {
@@ -388,7 +367,7 @@ struct lynx_28g_lane {
bool powered_up;
bool init;
unsigned int id;
- phy_interface_t interface;
+ enum lynx_lane_mode mode;
};
struct lynx_28g_priv {
@@ -429,7 +408,34 @@ static void lynx_28g_rmw(struct lynx_28g_priv *priv, unsigned long off,
#define lynx_28g_pll_read(pll, reg) \
ioread32((pll)->priv->base + reg((pll)->id))
-static bool lynx_28g_supports_interface(struct lynx_28g_priv *priv, int intf)
+static const char *lynx_lane_mode_str(enum lynx_lane_mode lane_mode)
+{
+ switch (lane_mode) {
+ case LANE_MODE_1000BASEX_SGMII:
+ return "1000Base-X/SGMII";
+ case LANE_MODE_10GBASER_USXGMII:
+ return "10GBase-R/USXGMII";
+ default:
+ return "unknown";
+ }
+}
+
+static enum lynx_lane_mode phy_interface_to_lane_mode(phy_interface_t intf)
+{
+ switch (intf) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ return LANE_MODE_1000BASEX_SGMII;
+ case PHY_INTERFACE_MODE_10GBASER:
+ case PHY_INTERFACE_MODE_USXGMII:
+ return LANE_MODE_10GBASER_USXGMII;
+ default:
+ return LANE_MODE_UNKNOWN;
+ }
+}
+
+static bool lynx_28g_supports_lane_mode(struct lynx_28g_priv *priv,
+ enum lynx_lane_mode mode)
{
int i;
@@ -437,7 +443,7 @@ static bool lynx_28g_supports_interface(struct lynx_28g_priv *priv, int intf)
if (PLLnRSTCTL_DIS(priv->pll[i].rstctl))
continue;
- if (test_bit(intf, priv->pll[i].supported))
+ if (test_bit(mode, priv->pll[i].supported))
return true;
}
@@ -445,7 +451,7 @@ static bool lynx_28g_supports_interface(struct lynx_28g_priv *priv, int intf)
}
static struct lynx_28g_pll *lynx_28g_pll_get(struct lynx_28g_priv *priv,
- phy_interface_t intf)
+ enum lynx_lane_mode mode)
{
struct lynx_28g_pll *pll;
int i;
@@ -456,27 +462,27 @@ static struct lynx_28g_pll *lynx_28g_pll_get(struct lynx_28g_priv *priv,
if (PLLnRSTCTL_DIS(pll->rstctl))
continue;
- if (test_bit(intf, pll->supported))
+ if (test_bit(mode, pll->supported))
return pll;
}
/* no pll supports requested mode, either caller forgot to check
* lynx_28g_supports_lane_mode, or this is a bug.
*/
- dev_WARN_ONCE(priv->dev, 1, "no pll for interface %s\n", phy_modes(intf));
+ dev_WARN_ONCE(priv->dev, 1, "no pll for lane mode %s\n",
+ lynx_lane_mode_str(mode));
return NULL;
}
static void lynx_28g_lane_set_nrate(struct lynx_28g_lane *lane,
struct lynx_28g_pll *pll,
- phy_interface_t intf)
+ enum lynx_lane_mode lane_mode)
{
switch (FIELD_GET(PLLnCR1_FRATE_SEL, pll->cr1)) {
case PLLnCR1_FRATE_5G_10GVCO:
case PLLnCR1_FRATE_5G_25GVCO:
- switch (intf) {
- case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_1000BASEX:
+ switch (lane_mode) {
+ case LANE_MODE_1000BASEX_SGMII:
lynx_28g_lane_rmw(lane, LNaTGCR0,
FIELD_PREP(LNaTGCR0_N_RATE, LNaTGCR0_N_RATE_QUARTER),
LNaTGCR0_N_RATE);
@@ -489,9 +495,8 @@ static void lynx_28g_lane_set_nrate(struct lynx_28g_lane *lane,
}
break;
case PLLnCR1_FRATE_10G_20GVCO:
- switch (intf) {
- case PHY_INTERFACE_MODE_10GBASER:
- case PHY_INTERFACE_MODE_USXGMII:
+ switch (lane_mode) {
+ case LANE_MODE_10GBASER_USXGMII:
lynx_28g_lane_rmw(lane, LNaTGCR0,
FIELD_PREP(LNaTGCR0_N_RATE, LNaTGCR0_N_RATE_FULL),
LNaTGCR0_N_RATE);
@@ -580,17 +585,16 @@ static int lynx_28g_power_on(struct phy *phy)
return 0;
}
-static int lynx_28g_get_pccr(phy_interface_t interface, int lane,
+static int lynx_28g_get_pccr(enum lynx_lane_mode lane_mode, int lane,
struct lynx_pccr *pccr)
{
- switch (interface) {
- case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_1000BASEX:
+ switch (lane_mode) {
+ case LANE_MODE_1000BASEX_SGMII:
pccr->offset = PCC8;
pccr->width = 4;
pccr->shift = SGMII_CFG(lane);
break;
- case PHY_INTERFACE_MODE_10GBASER:
+ case LANE_MODE_10GBASER_USXGMII:
pccr->offset = PCCC;
pccr->width = 4;
pccr->shift = SXGMII_CFG(lane);
@@ -602,13 +606,12 @@ static int lynx_28g_get_pccr(phy_interface_t interface, int lane,
return 0;
}
-static int lynx_28g_get_pcvt_offset(int lane, phy_interface_t interface)
+static int lynx_28g_get_pcvt_offset(int lane, enum lynx_lane_mode lane_mode)
{
- switch (interface) {
- case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_1000BASEX:
+ switch (lane_mode) {
+ case LANE_MODE_1000BASEX_SGMII:
return SGMIIaCR0(lane);
- case PHY_INTERFACE_MODE_10GBASER:
+ case LANE_MODE_10GBASER_USXGMII:
return SXGMIIaCR0(lane);
default:
return -EOPNOTSUPP;
@@ -616,14 +619,14 @@ static int lynx_28g_get_pcvt_offset(int lane, phy_interface_t interface)
}
static int lynx_pccr_write(struct lynx_28g_lane *lane,
- phy_interface_t interface, u32 val)
+ enum lynx_lane_mode lane_mode, u32 val)
{
struct lynx_28g_priv *priv = lane->priv;
struct lynx_pccr pccr;
u32 old, tmp, mask;
int err;
- err = lynx_28g_get_pccr(interface, lane->id, &pccr);
+ err = lynx_28g_get_pccr(lane_mode, lane->id, &pccr);
if (err)
return err;
@@ -638,13 +641,13 @@ static int lynx_pccr_write(struct lynx_28g_lane *lane,
return 0;
}
-static int lynx_pcvt_read(struct lynx_28g_lane *lane, phy_interface_t interface,
- int cr, u32 *val)
+static int lynx_pcvt_read(struct lynx_28g_lane *lane,
+ enum lynx_lane_mode lane_mode, int cr, u32 *val)
{
struct lynx_28g_priv *priv = lane->priv;
int offset;
- offset = lynx_28g_get_pcvt_offset(lane->id, interface);
+ offset = lynx_28g_get_pcvt_offset(lane->id, lane_mode);
if (offset < 0)
return offset;
@@ -653,13 +656,13 @@ static int lynx_pcvt_read(struct lynx_28g_lane *lane, phy_interface_t interface,
return 0;
}
-static int lynx_pcvt_write(struct lynx_28g_lane *lane, phy_interface_t interface,
- int cr, u32 val)
+static int lynx_pcvt_write(struct lynx_28g_lane *lane,
+ enum lynx_lane_mode lane_mode, int cr, u32 val)
{
struct lynx_28g_priv *priv = lane->priv;
int offset;
- offset = lynx_28g_get_pcvt_offset(lane->id, interface);
+ offset = lynx_28g_get_pcvt_offset(lane->id, lane_mode);
if (offset < 0)
return offset;
@@ -668,43 +671,44 @@ static int lynx_pcvt_write(struct lynx_28g_lane *lane, phy_interface_t interface
return 0;
}
-static int lynx_pcvt_rmw(struct lynx_28g_lane *lane, phy_interface_t interface,
+static int lynx_pcvt_rmw(struct lynx_28g_lane *lane,
+ enum lynx_lane_mode lane_mode,
int cr, u32 val, u32 mask)
{
int err;
u32 tmp;
- err = lynx_pcvt_read(lane, interface, cr, &tmp);
+ err = lynx_pcvt_read(lane, lane_mode, cr, &tmp);
if (err)
return err;
tmp &= ~mask;
tmp |= val;
- return lynx_pcvt_write(lane, interface, cr, tmp);
+ return lynx_pcvt_write(lane, lane_mode, cr, tmp);
}
static void lynx_28g_lane_remap_pll(struct lynx_28g_lane *lane,
- phy_interface_t interface)
+ enum lynx_lane_mode lane_mode)
{
struct lynx_28g_priv *priv = lane->priv;
struct lynx_28g_pll *pll;
/* Switch to the PLL that works with this interface type */
- pll = lynx_28g_pll_get(priv, interface);
+ pll = lynx_28g_pll_get(priv, lane_mode);
if (unlikely(pll == NULL))
return;
lynx_28g_lane_set_pll(lane, pll);
/* Choose the portion of clock net to be used on this lane */
- lynx_28g_lane_set_nrate(lane, pll, interface);
+ lynx_28g_lane_set_nrate(lane, pll, lane_mode);
}
static void lynx_28g_lane_change_proto_conf(struct lynx_28g_lane *lane,
- phy_interface_t interface)
+ enum lynx_lane_mode lane_mode)
{
- const struct lynx_28g_proto_conf *conf = &lynx_28g_proto_conf[interface];
+ const struct lynx_28g_proto_conf *conf = &lynx_28g_proto_conf[lane_mode];
lynx_28g_lane_rmw(lane, LNaGCR0,
FIELD_PREP(LNaGCR0_PROTO_SEL, conf->proto_sel) |
@@ -775,21 +779,20 @@ static void lynx_28g_lane_change_proto_conf(struct lynx_28g_lane *lane,
}
static int lynx_28g_lane_disable_pcvt(struct lynx_28g_lane *lane,
- phy_interface_t interface)
+ enum lynx_lane_mode lane_mode)
{
struct lynx_28g_priv *priv = lane->priv;
int err;
spin_lock(&priv->pcc_lock);
- err = lynx_pccr_write(lane, interface, 0);
+ err = lynx_pccr_write(lane, lane_mode, 0);
if (err)
goto out;
- switch (interface) {
- case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_1000BASEX:
- err = lynx_pcvt_rmw(lane, interface, CR(1), 0,
+ switch (lane_mode) {
+ case LANE_MODE_1000BASEX_SGMII:
+ err = lynx_pcvt_rmw(lane, lane_mode, CR(1), 0,
SGMIIaCR1_SGPCS_EN);
break;
default:
@@ -803,7 +806,7 @@ static int lynx_28g_lane_disable_pcvt(struct lynx_28g_lane *lane,
}
static int lynx_28g_lane_enable_pcvt(struct lynx_28g_lane *lane,
- phy_interface_t interface)
+ enum lynx_lane_mode lane_mode)
{
struct lynx_28g_priv *priv = lane->priv;
u32 val;
@@ -811,10 +814,9 @@ static int lynx_28g_lane_enable_pcvt(struct lynx_28g_lane *lane,
spin_lock(&priv->pcc_lock);
- switch (interface) {
- case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_1000BASEX:
- err = lynx_pcvt_rmw(lane, interface, CR(1), SGMIIaCR1_SGPCS_EN,
+ switch (lane_mode) {
+ case LANE_MODE_1000BASEX_SGMII:
+ err = lynx_pcvt_rmw(lane, lane_mode, CR(1), SGMIIaCR1_SGPCS_EN,
SGMIIaCR1_SGPCS_EN);
break;
default:
@@ -823,19 +825,18 @@ static int lynx_28g_lane_enable_pcvt(struct lynx_28g_lane *lane,
val = 0;
- switch (interface) {
- case PHY_INTERFACE_MODE_SGMII:
- case PHY_INTERFACE_MODE_1000BASEX:
+ switch (lane_mode) {
+ case LANE_MODE_1000BASEX_SGMII:
val |= PCC8_SGMIIa_CFG;
break;
- case PHY_INTERFACE_MODE_10GBASER:
+ case LANE_MODE_10GBASER_USXGMII:
val |= PCCC_SXGMIIn_CFG | PCCC_SXGMIIn_XFI;
break;
default:
break;
}
- err = lynx_pccr_write(lane, interface, val);
+ err = lynx_pccr_write(lane, lane_mode, val);
spin_unlock(&priv->pcc_lock);
@@ -847,18 +848,20 @@ static int lynx_28g_set_mode(struct phy *phy, enum phy_mode mode, int submode)
struct lynx_28g_lane *lane = phy_get_drvdata(phy);
struct lynx_28g_priv *priv = lane->priv;
int powered_up = lane->powered_up;
+ enum lynx_lane_mode lane_mode;
int err = 0;
if (mode != PHY_MODE_ETHERNET)
return -EOPNOTSUPP;
- if (lane->interface == PHY_INTERFACE_MODE_NA)
+ if (lane->mode == LANE_MODE_UNKNOWN)
return -EOPNOTSUPP;
- if (!lynx_28g_supports_interface(priv, submode))
+ lane_mode = phy_interface_to_lane_mode(submode);
+ if (!lynx_28g_supports_lane_mode(priv, lane_mode))
return -EOPNOTSUPP;
- if (submode == lane->interface)
+ if (lane_mode == lane->mode)
return 0;
/* If the lane is powered up, put the lane into the halt state while
@@ -867,15 +870,15 @@ static int lynx_28g_set_mode(struct phy *phy, enum phy_mode mode, int submode)
if (powered_up)
lynx_28g_power_off(phy);
- err = lynx_28g_lane_disable_pcvt(lane, lane->interface);
+ err = lynx_28g_lane_disable_pcvt(lane, lane->mode);
if (err)
goto out;
- lynx_28g_lane_change_proto_conf(lane, submode);
- lynx_28g_lane_remap_pll(lane, submode);
- WARN_ON(lynx_28g_lane_enable_pcvt(lane, submode));
+ lynx_28g_lane_change_proto_conf(lane, lane_mode);
+ lynx_28g_lane_remap_pll(lane, lane_mode);
+ WARN_ON(lynx_28g_lane_enable_pcvt(lane, lane_mode));
- lane->interface = submode;
+ lane->mode = lane_mode;
out:
if (powered_up)
@@ -889,11 +892,13 @@ static int lynx_28g_validate(struct phy *phy, enum phy_mode mode, int submode,
{
struct lynx_28g_lane *lane = phy_get_drvdata(phy);
struct lynx_28g_priv *priv = lane->priv;
+ enum lynx_lane_mode lane_mode;
if (mode != PHY_MODE_ETHERNET)
return -EOPNOTSUPP;
- if (!lynx_28g_supports_interface(priv, submode))
+ lane_mode = phy_interface_to_lane_mode(submode);
+ if (!lynx_28g_supports_lane_mode(priv, lane_mode))
return -EOPNOTSUPP;
return 0;
@@ -946,12 +951,11 @@ static void lynx_28g_pll_read_configuration(struct lynx_28g_priv *priv)
case PLLnCR1_FRATE_5G_10GVCO:
case PLLnCR1_FRATE_5G_25GVCO:
/* 5GHz clock net */
- __set_bit(PHY_INTERFACE_MODE_1000BASEX, pll->supported);
- __set_bit(PHY_INTERFACE_MODE_SGMII, pll->supported);
+ __set_bit(LANE_MODE_1000BASEX_SGMII, pll->supported);
break;
case PLLnCR1_FRATE_10G_20GVCO:
/* 10.3125GHz clock net */
- __set_bit(PHY_INTERFACE_MODE_10GBASER, pll->supported);
+ __set_bit(LANE_MODE_10GBASER_USXGMII, pll->supported);
break;
default:
/* 6GHz, 12.890625GHz, 8GHz */
@@ -1002,13 +1006,13 @@ static void lynx_28g_lane_read_configuration(struct lynx_28g_lane *lane)
protocol = FIELD_GET(LNaPSS_TYPE, pss);
switch (protocol) {
case LNaPSS_TYPE_SGMII:
- lane->interface = PHY_INTERFACE_MODE_SGMII;
+ lane->mode = LANE_MODE_1000BASEX_SGMII;
break;
case LNaPSS_TYPE_XFI:
- lane->interface = PHY_INTERFACE_MODE_10GBASER;
+ lane->mode = LANE_MODE_10GBASER_USXGMII;
break;
default:
- lane->interface = PHY_INTERFACE_MODE_NA;
+ lane->mode = LANE_MODE_UNKNOWN;
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v3 phy 08/17] phy: lynx-28g: distinguish between 10GBASE-R and USXGMII
2025-09-26 18:04 [PATCH v3 phy 00/17] Lynx 28G improvements part 1 Vladimir Oltean
` (6 preceding siblings ...)
2025-09-26 18:04 ` [PATCH v3 phy 07/17] phy: lynx-28g: refactor lane->interface to lane->mode Vladimir Oltean
@ 2025-09-26 18:04 ` Vladimir Oltean
2025-09-26 18:04 ` [PATCH v3 phy 09/17] phy: lynx-28g: configure more equalization params for 1GbE and 10GbE Vladimir Oltean
` (8 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Vladimir Oltean @ 2025-09-26 18:04 UTC (permalink / raw)
To: linux-phy
Cc: Ioana Ciornei, Vinod Koul, Kishon Vijay Abraham I, Josua Mayer,
linux-kernel
The driver does not handle well protocol switching to or from USXGMII,
because it conflates it with 10GBase-R.
In the expected USXGMII use case, that isn't a problem, because SerDes
protocol switching performed by the lynx-28g driver is not necessary,
because USXGMII natively supports multiple speeds, as opposed to SFP
modules using 1000Base-X or 10GBase-R which require switching between
the 2.
That being said, let's be explicit, and in case someone requests a
protocol change which involves USXGMII, let's do the right thing.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
v1->v3: none
drivers/phy/freescale/phy-fsl-lynx-28g.c | 87 ++++++++++++++++++++----
1 file changed, 74 insertions(+), 13 deletions(-)
diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
index 7ef81f26bee8..a8a335680092 100644
--- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
+++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
@@ -246,7 +246,8 @@ enum lynx_28g_proto_sel {
enum lynx_lane_mode {
LANE_MODE_UNKNOWN,
LANE_MODE_1000BASEX_SGMII,
- LANE_MODE_10GBASER_USXGMII,
+ LANE_MODE_10GBASER,
+ LANE_MODE_USXGMII,
LANE_MODE_MAX,
};
@@ -316,7 +317,35 @@ static const struct lynx_28g_proto_conf lynx_28g_proto_conf[LANE_MODE_MAX] = {
.smp_autoz_d1r = 0,
.smp_autoz_eg1r = 0,
},
- [LANE_MODE_10GBASER_USXGMII] = {
+ [LANE_MODE_USXGMII] = {
+ .proto_sel = LNaGCR0_PROTO_SEL_XFI,
+ .if_width = LNaGCR0_IF_WIDTH_20_BIT,
+ .teq_type = EQ_TYPE_2TAP,
+ .sgn_preq = 1,
+ .ratio_preq = 0,
+ .sgn_post1q = 1,
+ .ratio_post1q = 3,
+ .amp_red = 7,
+ .adpt_eq = 48,
+ .enter_idle_flt_sel = 0,
+ .exit_idle_flt_sel = 0,
+ .data_lost_th_sel = 0,
+ .gk2ovd = 0,
+ .gk3ovd = 0,
+ .gk4ovd = 0,
+ .gk2ovd_en = 0,
+ .gk3ovd_en = 0,
+ .gk4ovd_en = 0,
+ .eq_offset_ovd = 0x1f,
+ .eq_offset_ovd_en = 0,
+ .eq_offset_rng_dbl = 1,
+ .eq_blw_sel = 1,
+ .eq_boost = 0,
+ .spare_in = 0,
+ .smp_autoz_d1r = 2,
+ .smp_autoz_eg1r = 0,
+ },
+ [LANE_MODE_10GBASER] = {
.proto_sel = LNaGCR0_PROTO_SEL_XFI,
.if_width = LNaGCR0_IF_WIDTH_20_BIT,
.teq_type = EQ_TYPE_2TAP,
@@ -413,8 +442,10 @@ static const char *lynx_lane_mode_str(enum lynx_lane_mode lane_mode)
switch (lane_mode) {
case LANE_MODE_1000BASEX_SGMII:
return "1000Base-X/SGMII";
- case LANE_MODE_10GBASER_USXGMII:
- return "10GBase-R/USXGMII";
+ case LANE_MODE_10GBASER:
+ return "10GBase-R";
+ case LANE_MODE_USXGMII:
+ return "USXGMII";
default:
return "unknown";
}
@@ -427,8 +458,9 @@ static enum lynx_lane_mode phy_interface_to_lane_mode(phy_interface_t intf)
case PHY_INTERFACE_MODE_1000BASEX:
return LANE_MODE_1000BASEX_SGMII;
case PHY_INTERFACE_MODE_10GBASER:
+ return LANE_MODE_10GBASER;
case PHY_INTERFACE_MODE_USXGMII:
- return LANE_MODE_10GBASER_USXGMII;
+ return LANE_MODE_USXGMII;
default:
return LANE_MODE_UNKNOWN;
}
@@ -496,7 +528,8 @@ static void lynx_28g_lane_set_nrate(struct lynx_28g_lane *lane,
break;
case PLLnCR1_FRATE_10G_20GVCO:
switch (lane_mode) {
- case LANE_MODE_10GBASER_USXGMII:
+ case LANE_MODE_10GBASER:
+ case LANE_MODE_USXGMII:
lynx_28g_lane_rmw(lane, LNaTGCR0,
FIELD_PREP(LNaTGCR0_N_RATE, LNaTGCR0_N_RATE_FULL),
LNaTGCR0_N_RATE);
@@ -594,7 +627,8 @@ static int lynx_28g_get_pccr(enum lynx_lane_mode lane_mode, int lane,
pccr->width = 4;
pccr->shift = SGMII_CFG(lane);
break;
- case LANE_MODE_10GBASER_USXGMII:
+ case LANE_MODE_USXGMII:
+ case LANE_MODE_10GBASER:
pccr->offset = PCCC;
pccr->width = 4;
pccr->shift = SXGMII_CFG(lane);
@@ -611,13 +645,32 @@ static int lynx_28g_get_pcvt_offset(int lane, enum lynx_lane_mode lane_mode)
switch (lane_mode) {
case LANE_MODE_1000BASEX_SGMII:
return SGMIIaCR0(lane);
- case LANE_MODE_10GBASER_USXGMII:
+ case LANE_MODE_USXGMII:
+ case LANE_MODE_10GBASER:
return SXGMIIaCR0(lane);
default:
return -EOPNOTSUPP;
}
}
+static int lynx_pccr_read(struct lynx_28g_lane *lane, enum lynx_lane_mode mode,
+ u32 *val)
+{
+ struct lynx_28g_priv *priv = lane->priv;
+ struct lynx_pccr pccr;
+ u32 tmp;
+ int err;
+
+ err = lynx_28g_get_pccr(mode, lane->id, &pccr);
+ if (err)
+ return err;
+
+ tmp = lynx_28g_read(priv, pccr.offset);
+ *val = (tmp >> pccr.shift) & GENMASK(pccr.width - 1, 0);
+
+ return 0;
+}
+
static int lynx_pccr_write(struct lynx_28g_lane *lane,
enum lynx_lane_mode lane_mode, u32 val)
{
@@ -829,8 +882,11 @@ static int lynx_28g_lane_enable_pcvt(struct lynx_28g_lane *lane,
case LANE_MODE_1000BASEX_SGMII:
val |= PCC8_SGMIIa_CFG;
break;
- case LANE_MODE_10GBASER_USXGMII:
- val |= PCCC_SXGMIIn_CFG | PCCC_SXGMIIn_XFI;
+ case LANE_MODE_10GBASER:
+ val |= PCCC_SXGMIIn_XFI;
+ fallthrough;
+ case LANE_MODE_USXGMII:
+ val |= PCCC_SXGMIIn_CFG;
break;
default:
break;
@@ -955,7 +1011,8 @@ static void lynx_28g_pll_read_configuration(struct lynx_28g_priv *priv)
break;
case PLLnCR1_FRATE_10G_20GVCO:
/* 10.3125GHz clock net */
- __set_bit(LANE_MODE_10GBASER_USXGMII, pll->supported);
+ __set_bit(LANE_MODE_10GBASER, pll->supported);
+ __set_bit(LANE_MODE_USXGMII, pll->supported);
break;
default:
/* 6GHz, 12.890625GHz, 8GHz */
@@ -1000,7 +1057,7 @@ static void lynx_28g_cdr_lock_check(struct work_struct *work)
static void lynx_28g_lane_read_configuration(struct lynx_28g_lane *lane)
{
- u32 pss, protocol;
+ u32 pccr, pss, protocol;
pss = lynx_28g_lane_read(lane, LNaPSS);
protocol = FIELD_GET(LNaPSS_TYPE, pss);
@@ -1009,7 +1066,11 @@ static void lynx_28g_lane_read_configuration(struct lynx_28g_lane *lane)
lane->mode = LANE_MODE_1000BASEX_SGMII;
break;
case LNaPSS_TYPE_XFI:
- lane->mode = LANE_MODE_10GBASER_USXGMII;
+ lynx_pccr_read(lane, LANE_MODE_10GBASER, &pccr);
+ if (pccr & PCCC_SXGMIIn_XFI)
+ lane->mode = LANE_MODE_10GBASER;
+ else
+ lane->mode = LANE_MODE_USXGMII;
break;
default:
lane->mode = LANE_MODE_UNKNOWN;
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v3 phy 09/17] phy: lynx-28g: configure more equalization params for 1GbE and 10GbE
2025-09-26 18:04 [PATCH v3 phy 00/17] Lynx 28G improvements part 1 Vladimir Oltean
` (7 preceding siblings ...)
2025-09-26 18:04 ` [PATCH v3 phy 08/17] phy: lynx-28g: distinguish between 10GBASE-R and USXGMII Vladimir Oltean
@ 2025-09-26 18:04 ` Vladimir Oltean
2025-09-26 18:04 ` [PATCH v3 phy 10/17] phy: lynx-28g: use "dev" argument more in lynx_28g_probe() Vladimir Oltean
` (7 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Vladimir Oltean @ 2025-09-26 18:04 UTC (permalink / raw)
To: linux-phy
Cc: Ioana Ciornei, Vinod Koul, Kishon Vijay Abraham I, Josua Mayer,
linux-kernel
From: Ioana Ciornei <ioana.ciornei@nxp.com>
While adding support for 25GbE, it was noticed that the RCCR0 and TTLCR0
registers have different values for this protocol than the 10GbE and
1GbE modes.
Expand the lynx_28g_proto_conf[] array with the expected values for the
currently supported protocols. These were dumped from a live system, and
are the out-of-reset values. It will ensure that the lane is configured
with these values when transitioning from 25GbE back into one of these
modes.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
v1->v3: none
drivers/phy/freescale/phy-fsl-lynx-28g.c | 37 ++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
index a8a335680092..eb2353531ef7 100644
--- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
+++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
@@ -166,6 +166,18 @@
#define LNaRECR4_EQ_BIN_DATA GENMASK(8, 0) /* bit 9 is reserved */
#define LNaRECR4_EQ_BIN_DATA_SGN BIT(8)
+#define LNaRCCR0(lane) (0x800 + (lane) * 0x100 + 0x68)
+#define LNaRCCR0_CAL_EN BIT(31)
+#define LNaRCCR0_MEAS_EN BIT(30)
+#define LNaRCCR0_CAL_BIN_SEL BIT(28)
+#define LNaRCCR0_CAL_DC3_DIS BIT(27)
+#define LNaRCCR0_CAL_DC2_DIS BIT(26)
+#define LNaRCCR0_CAL_DC1_DIS BIT(25)
+#define LNaRCCR0_CAL_DC0_DIS BIT(24)
+#define LNaRCCR0_CAL_AC3_OV_EN BIT(15)
+#define LNaRCCR0_CAL_AC3_OV GENMASK(11, 8)
+#define LNaRCCR0_CAL_AC2_OV_EN BIT(7)
+
#define LNaRSCCR0(lane) (0x800 + (lane) * 0x100 + 0x74)
#define LNaRSCCR0_SMP_OFF_EN BIT(31)
#define LNaRSCCR0_SMP_OFF_OV_EN BIT(30)
@@ -180,6 +192,15 @@
#define LNaRSCCR0_SMP_AUTOZ_EG1R GENMASK(5, 4)
#define LNaRSCCR0_SMP_AUTOZ_EG1F GENMASK(1, 0)
+#define LNaTTLCR0(lane) (0x800 + (lane) * 0x100 + 0x80)
+#define LNaTTLCR0_TTL_FLT_SEL GENMASK(29, 24)
+#define LNaTTLCR0_TTL_SLO_PM_BYP BIT(22)
+#define LNaTTLCR0_STALL_DET_DIS BIT(21)
+#define LNaTTLCR0_INACT_MON_DIS BIT(20)
+#define LNaTTLCR0_CDR_OV GENMASK(18, 16)
+#define LNaTTLCR0_DATA_IN_SSC BIT(15)
+#define LNaTTLCR0_CDR_MIN_SMP_ON GENMASK(1, 0)
+
#define LNaTCSR0(lane) (0x800 + (lane) * 0x100 + 0xa0)
#define LNaTCSR0_SD_STAT_OBS_EN BIT(31)
#define LNaTCSR0_SD_LPBK_SEL GENMASK(29, 28)
@@ -286,6 +307,10 @@ struct lynx_28g_proto_conf {
/* LNaRSCCR0 */
int smp_autoz_d1r;
int smp_autoz_eg1r;
+ /* LNaRCCR0 */
+ int rccr0;
+ /* LNaTTLCR0 */
+ int ttlcr0;
};
static const struct lynx_28g_proto_conf lynx_28g_proto_conf[LANE_MODE_MAX] = {
@@ -316,6 +341,9 @@ static const struct lynx_28g_proto_conf lynx_28g_proto_conf[LANE_MODE_MAX] = {
.spare_in = 0,
.smp_autoz_d1r = 0,
.smp_autoz_eg1r = 0,
+ .rccr0 = LNaRCCR0_CAL_EN,
+ .ttlcr0 = LNaTTLCR0_TTL_SLO_PM_BYP |
+ LNaTTLCR0_DATA_IN_SSC,
},
[LANE_MODE_USXGMII] = {
.proto_sel = LNaGCR0_PROTO_SEL_XFI,
@@ -344,6 +372,9 @@ static const struct lynx_28g_proto_conf lynx_28g_proto_conf[LANE_MODE_MAX] = {
.spare_in = 0,
.smp_autoz_d1r = 2,
.smp_autoz_eg1r = 0,
+ .rccr0 = LNaRCCR0_CAL_EN,
+ .ttlcr0 = LNaTTLCR0_TTL_SLO_PM_BYP |
+ LNaTTLCR0_DATA_IN_SSC,
},
[LANE_MODE_10GBASER] = {
.proto_sel = LNaGCR0_PROTO_SEL_XFI,
@@ -372,6 +403,9 @@ static const struct lynx_28g_proto_conf lynx_28g_proto_conf[LANE_MODE_MAX] = {
.spare_in = 0,
.smp_autoz_d1r = 2,
.smp_autoz_eg1r = 0,
+ .rccr0 = LNaRCCR0_CAL_EN,
+ .ttlcr0 = LNaTTLCR0_TTL_SLO_PM_BYP |
+ LNaTTLCR0_DATA_IN_SSC,
},
};
@@ -829,6 +863,9 @@ static void lynx_28g_lane_change_proto_conf(struct lynx_28g_lane *lane,
FIELD_PREP(LNaRSCCR0_SMP_AUTOZ_EG1R, conf->smp_autoz_eg1r),
LNaRSCCR0_SMP_AUTOZ_D1R |
LNaRSCCR0_SMP_AUTOZ_EG1R);
+
+ lynx_28g_lane_write(lane, LNaRCCR0, conf->rccr0);
+ lynx_28g_lane_write(lane, LNaTTLCR0, conf->ttlcr0);
}
static int lynx_28g_lane_disable_pcvt(struct lynx_28g_lane *lane,
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v3 phy 10/17] phy: lynx-28g: use "dev" argument more in lynx_28g_probe()
2025-09-26 18:04 [PATCH v3 phy 00/17] Lynx 28G improvements part 1 Vladimir Oltean
` (8 preceding siblings ...)
2025-09-26 18:04 ` [PATCH v3 phy 09/17] phy: lynx-28g: configure more equalization params for 1GbE and 10GbE Vladimir Oltean
@ 2025-09-26 18:04 ` Vladimir Oltean
2025-09-26 18:04 ` [PATCH v3 phy 11/17] phy: lynx-28g: improve lynx_28g_probe() sequence Vladimir Oltean
` (6 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Vladimir Oltean @ 2025-09-26 18:04 UTC (permalink / raw)
To: linux-phy
Cc: Ioana Ciornei, Vinod Koul, Kishon Vijay Abraham I, Josua Mayer,
linux-kernel
We have "dev" which holds &pdev->dev, but we still dereference this
pointer 5 more times, instead of using the local variable.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
v2->v3: none
v1->v2: patch is new
drivers/phy/freescale/phy-fsl-lynx-28g.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
index eb2353531ef7..7800f57413ee 100644
--- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
+++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
@@ -1133,10 +1133,10 @@ static int lynx_28g_probe(struct platform_device *pdev)
struct lynx_28g_priv *priv;
int i;
- priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
- priv->dev = &pdev->dev;
+ priv->dev = dev;
priv->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->base))
@@ -1150,7 +1150,7 @@ static int lynx_28g_probe(struct platform_device *pdev)
memset(lane, 0, sizeof(*lane));
- phy = devm_phy_create(&pdev->dev, NULL, &lynx_28g_ops);
+ phy = devm_phy_create(dev, NULL, &lynx_28g_ops);
if (IS_ERR(phy))
return PTR_ERR(phy);
@@ -1169,8 +1169,8 @@ static int lynx_28g_probe(struct platform_device *pdev)
queue_delayed_work(system_power_efficient_wq, &priv->cdr_check,
msecs_to_jiffies(1000));
- dev_set_drvdata(&pdev->dev, priv);
- provider = devm_of_phy_provider_register(&pdev->dev, lynx_28g_xlate);
+ dev_set_drvdata(dev, priv);
+ provider = devm_of_phy_provider_register(dev, lynx_28g_xlate);
return PTR_ERR_OR_ZERO(provider);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v3 phy 11/17] phy: lynx-28g: improve lynx_28g_probe() sequence
2025-09-26 18:04 [PATCH v3 phy 00/17] Lynx 28G improvements part 1 Vladimir Oltean
` (9 preceding siblings ...)
2025-09-26 18:04 ` [PATCH v3 phy 10/17] phy: lynx-28g: use "dev" argument more in lynx_28g_probe() Vladimir Oltean
@ 2025-09-26 18:04 ` Vladimir Oltean
2025-09-26 18:05 ` [PATCH v3 phy 12/17] dt-bindings: phy: lynx-28g: add compatible strings per SerDes and instantiation Vladimir Oltean
` (5 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Vladimir Oltean @ 2025-09-26 18:04 UTC (permalink / raw)
To: linux-phy
Cc: Ioana Ciornei, Vinod Koul, Kishon Vijay Abraham I, Josua Mayer,
linux-kernel
dev_set_drvdata() is called twice, it is sufficient to do it only once.
devm_of_phy_provider_register() can fail, and if it does, the
&priv->cdr_check work item is queued, but not cancelled, and the device
probing failed, so it will trigger use after free. This is a minor risk
though.
Resource initialization should be done a little earlier, in case we need
to dereference dev_get_drvdata() in lynx_28g_pll_read_configuration() or
in lynx_28g_lane_read_configuration().
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
v2->v3: none
v1->v2: patch is new
drivers/phy/freescale/phy-fsl-lynx-28g.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
index 7800f57413ee..453e76e0a6b7 100644
--- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
+++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
@@ -1136,7 +1136,11 @@ static int lynx_28g_probe(struct platform_device *pdev)
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
+
priv->dev = dev;
+ dev_set_drvdata(dev, priv);
+ spin_lock_init(&priv->pcc_lock);
+ INIT_DELAYED_WORK(&priv->cdr_check, lynx_28g_cdr_lock_check);
priv->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->base))
@@ -1161,18 +1165,14 @@ static int lynx_28g_probe(struct platform_device *pdev)
lynx_28g_lane_read_configuration(lane);
}
- dev_set_drvdata(dev, priv);
-
- spin_lock_init(&priv->pcc_lock);
- INIT_DELAYED_WORK(&priv->cdr_check, lynx_28g_cdr_lock_check);
+ provider = devm_of_phy_provider_register(dev, lynx_28g_xlate);
+ if (IS_ERR(provider))
+ return PTR_ERR(provider);
queue_delayed_work(system_power_efficient_wq, &priv->cdr_check,
msecs_to_jiffies(1000));
- dev_set_drvdata(dev, priv);
- provider = devm_of_phy_provider_register(dev, lynx_28g_xlate);
-
- return PTR_ERR_OR_ZERO(provider);
+ return 0;
}
static void lynx_28g_remove(struct platform_device *pdev)
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v3 phy 12/17] dt-bindings: phy: lynx-28g: add compatible strings per SerDes and instantiation
2025-09-26 18:04 [PATCH v3 phy 00/17] Lynx 28G improvements part 1 Vladimir Oltean
` (10 preceding siblings ...)
2025-09-26 18:04 ` [PATCH v3 phy 11/17] phy: lynx-28g: improve lynx_28g_probe() sequence Vladimir Oltean
@ 2025-09-26 18:05 ` Vladimir Oltean
2025-09-30 14:07 ` Vladimir Oltean
2025-09-26 18:05 ` [PATCH v3 phy 13/17] phy: lynx-28g: probe on per-SoC and per-instance compatible strings Vladimir Oltean
` (4 subsequent siblings)
16 siblings, 1 reply; 26+ messages in thread
From: Vladimir Oltean @ 2025-09-26 18:05 UTC (permalink / raw)
To: linux-phy
Cc: Ioana Ciornei, Vinod Koul, Kishon Vijay Abraham I, Josua Mayer,
linux-kernel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
devicetree
Going by the generic "fsl,lynx-28g" compatible string and expecting all
SerDes instantiations on all SoCs to use it was a mistake.
They all share the same register map, sure, but the number of protocol
converters and lanes which are instantiated differs in a way that isn't
detectable by the programming interface.
Using a separate compatible string per SerDes instantiation is
sufficient for any device driver to distinguish these features and/or
any instance-specific quirk. It also reflects how the SoC reference
manual provides different tables with protocol combinations for each
SerDes. NXP clearly documents these as not identical, and refers to them
as such (SerDes 1, 2, etc).
The other sufficient approach for Lynx 28G would be to list in the
device tree all protocols supported by each lane. That would be
insufficient for the very similar Lynx 10G SerDes however, for which
there exists a higher degree of variability in the PCCR register values
that need to be written per protocol. This attempt can be seen in this
unmerged patch set for Lynx 10G:
https://lore.kernel.org/linux-phy/20230413160607.4128315-3-sean.anderson@seco.com/
but that approach is more drawn-out and more prone to errors, whereas
this one is more succinct and obviously correct.
One aspect which is different with the per-SoC compatible strings is
that they have one PHY provider for each lane (and #phy-cells = <0> in
lane sub-nodes), rather than "fsl,lynx-28g" which has a single PHY
provider for all lanes (and #phy-cells = <1> in the top-level node).
This is done to fulfill Josua Mayer's request:
https://lore.kernel.org/lkml/02270f62-9334-400c-b7b9-7e6a44dbbfc9@solid-run.com/
to have OF nodes for each lane, so that we can further apply schemas
such as Documentation/devicetree/bindings/phy/transmit-amplitude.yaml
individually.
This is the easiest and most intuitive way to describe that. The above
is not the only electrical tuning that needs to be done, but rather the
only one currently standardized in a schema. TX equalization parameters
are TBD, but we need to not limit ourselves to just what currently exists.
Luckily, we can overlap the modern binding format over the legacy one
and they can coexist without interfering. Old kernels use compatible =
"fsl,lynx-28g" and the top-level PHY provider, whereas new kernels probe
on e.g. compatible = "fsl,lx2160a-serdes1" and use the per-lane PHY
providers.
Overlaying modern on top of legacy is only necessary for SerDes 1 and 2.
LX2160A SerDes #3 (a non-networking SerDes) is not yet present in any
device trees in circulation, and will only have the device-specific
compatible (even though it shares the Lynx 28G programming model,
specifying the "fsl,lynx-28g" compatible string for it provides no
benefit that I can see).
Change the expected name of the top-level node to "serdes", and update
the example too.
Cc: Rob Herring <robh@kernel.org>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
v2->v3:
- re-add "fsl,lynx-28g" as fallback compatible, and #phy-cells = <1> in
top-level "serdes" node
- drop useless description texts
- fix text formatting
- schema is more lax to allow overlaying old and new required properties
v1->v2:
- drop the usage of "fsl,lynx-28g" as a fallback compatible
- mark "fsl,lynx-28g" as deprecated
- implement Josua's request for per-lane OF nodes for the new compatible
strings
.../devicetree/bindings/phy/fsl,lynx-28g.yaml | 159 +++++++++++++++++-
1 file changed, 152 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml b/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml
index ff9f9ca0f19c..e8b3a48b9515 100644
--- a/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml
+++ b/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml
@@ -9,21 +9,123 @@ title: Freescale Lynx 28G SerDes PHY
maintainers:
- Ioana Ciornei <ioana.ciornei@nxp.com>
+description:
+ The Lynx 28G is a multi-lane, multi-protocol SerDes (PCIe, SATA, Ethernet)
+ present in multiple instances on NXP LX2160A and LX2162A SoCs. All instances
+ share a common register map and programming model, however they differ in
+ supported protocols per lane in a way that is not detectable by said
+ programming model without prior knowledge. The distinction is made through
+ the compatible string.
+
properties:
compatible:
- enum:
- - fsl,lynx-28g
+ oneOf:
+ - const: fsl,lynx-28g
+ deprecated: true
+ description:
+ Legacy compatibility string for Lynx 28G SerDes. Any assumption
+ regarding whether a certain lane supports a certain protocol may
+ be incorrect. Deprecated except when used as a fallback. Use
+ device-specific strings instead.
+ - items:
+ - const: fsl,lx2160a-serdes1
+ - const: fsl,lynx-28g
+ - items:
+ - const: fsl,lx2160a-serdes2
+ - const: fsl,lynx-28g
+ - items:
+ - const: fsl,lx2162a-serdes1
+ - const: fsl,lynx-28g
+ - items:
+ - const: fsl,lx2162a-serdes2
+ - const: fsl,lynx-28g
+ - const: fsl,lx2160a-serdes3
reg:
maxItems: 1
- "#phy-cells":
- const: 1
+ "#address-cells": true
+
+ "#size-cells": true
+
+ "#phy-cells": true
+
+patternProperties:
+ "^phy@[0-9a-f]+$":
+ type: object
+ description: Individual SerDes lane acting as PHY provider
+
+ properties:
+ reg:
+ description: Lane index as seen in register map
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+ required:
+ - reg
+ - "#phy-cells"
+
+ additionalProperties: false
required:
- compatible
- reg
- - "#phy-cells"
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,lynx-28g
+ then:
+ # Legacy case: parent is the PHY provider, cell encodes lane index
+ properties:
+ "#phy-cells":
+ const: 1
+ required:
+ - "#phy-cells"
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,lx2160a-serdes1
+ - fsl,lx2160a-serdes2
+ - fsl,lx2160a-serdes3
+ - fsl,lx2162a-serdes1
+ - fsl,lx2162a-serdes2
+ then:
+ # Modern binding: lanes must have their own nodes
+ properties:
+ "#address-cells":
+ const: 1
+ "#size-cells":
+ const: 0
+ required:
+ - "#address-cells"
+ - "#size-cells"
+
+ # LX2162A SerDes 1 has fewer lanes than the others
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,lx2162a-serdes1
+ then:
+ patternProperties:
+ "^phy@[0-9a-f]+$":
+ properties:
+ reg:
+ enum: [4, 5, 6, 7]
+ else:
+ patternProperties:
+ "^phy@[0-9a-f]+$":
+ properties:
+ reg:
+ enum: [0, 1, 2, 3, 4, 5, 6, 7]
additionalProperties: false
@@ -32,9 +134,52 @@ examples:
soc {
#address-cells = <2>;
#size-cells = <2>;
- serdes_1: phy@1ea0000 {
- compatible = "fsl,lynx-28g";
+
+ serdes_1: serdes@1ea0000 {
+ compatible = "fsl,lx2160a-serdes1", "fsl,lynx-28g";
reg = <0x0 0x1ea0000 0x0 0x1e30>;
+ #address-cells = <1>;
+ #size-cells = <0>;
#phy-cells = <1>;
+
+ phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+
+ phy@4 {
+ reg = <4>;
+ #phy-cells = <0>;
+ };
+
+ phy@5 {
+ reg = <5>;
+ #phy-cells = <0>;
+ };
+
+ phy@6 {
+ reg = <6>;
+ #phy-cells = <0>;
+ };
+
+ phy@7 {
+ reg = <7>;
+ #phy-cells = <0>;
+ };
};
};
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v3 phy 13/17] phy: lynx-28g: probe on per-SoC and per-instance compatible strings
2025-09-26 18:04 [PATCH v3 phy 00/17] Lynx 28G improvements part 1 Vladimir Oltean
` (11 preceding siblings ...)
2025-09-26 18:05 ` [PATCH v3 phy 12/17] dt-bindings: phy: lynx-28g: add compatible strings per SerDes and instantiation Vladimir Oltean
@ 2025-09-26 18:05 ` Vladimir Oltean
2025-10-02 10:40 ` Josua Mayer
2025-09-26 18:05 ` [PATCH v3 phy 14/17] phy: lynx-28g: add support for 25GBASER Vladimir Oltean
` (3 subsequent siblings)
16 siblings, 1 reply; 26+ messages in thread
From: Vladimir Oltean @ 2025-09-26 18:05 UTC (permalink / raw)
To: linux-phy
Cc: Ioana Ciornei, Vinod Koul, Kishon Vijay Abraham I, Josua Mayer,
linux-kernel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
devicetree
Add driver support for probing on the new, per-instance and per-SoC
bindings, which provide the following benefits:
- they allow rejecting unsupported protocols per lane (10GbE on SerDes 2
lanes 0-5)
- individual lanes have their own OF nodes as PHY providers, which
allows board device tree authors to tune electrical parameters such as
TX amplitude, equalization etc.
Probing on "fsl,lynx-28g" is still supported, but the feature set is
frozen in time to just 1GbE and 10GbE (essentially the feature set as of
this change). However, we encourage the user at probe time to update the
device tree.
Refactor the per-lane logic from lynx_28g_probe() into
lynx_28g_lane_probe(), and call it from two distinct paths depending on
whether the modern or the legacy compatible string is used, with an OF
node for the lane or without.
Notable implication of the above: when lanes have disabled OF nodes, we
skip creating PHYs for them, and must also skip the CDR lock workaround.
lynx_28g_supports_lane_mode() was a SerDes-global function and now
becomes per lane, to reflect the specific capabilities each instance may
have.
Cc: Rob Herring <robh@kernel.org>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
v2->v3:
- reword commit message
- add some comments regarding the "fsl,lynx-28g" fallback mechanism
- skip CDR lock workaround for lanes with no PHY (disabled in the device
tree in the new binding)
v1->v2:
- remove priv->info->get_pccr() and priv->info->get_pcvt_offset().
These were always called directly as lynx_28g_get_pccr() and
lynx_28g_get_pcvt_offset().
- Add forgotten priv->info->lane_supports_mode() test to
lynx_28g_supports_lane_mode().
- Rename the "fsl,lynx-28g" drvdata as lynx_info_compat rather than
lynx_info_lx2160a_serdes1, to reflect its treatment as less featured.
- Implement a separate lane probing path for the #phy-cells = <0> case.
drivers/phy/freescale/phy-fsl-lynx-28g.c | 202 ++++++++++++++++++++---
1 file changed, 179 insertions(+), 23 deletions(-)
diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
index 453e76e0a6b7..1ddca8b4de17 100644
--- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
+++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
@@ -433,9 +433,15 @@ struct lynx_28g_lane {
enum lynx_lane_mode mode;
};
+struct lynx_info {
+ bool (*lane_supports_mode)(int lane, enum lynx_lane_mode mode);
+ int first_lane;
+};
+
struct lynx_28g_priv {
void __iomem *base;
struct device *dev;
+ const struct lynx_info *info;
/* Serialize concurrent access to registers shared between lanes,
* like PCCn
*/
@@ -500,11 +506,18 @@ static enum lynx_lane_mode phy_interface_to_lane_mode(phy_interface_t intf)
}
}
-static bool lynx_28g_supports_lane_mode(struct lynx_28g_priv *priv,
+/* A lane mode is supported if we have a PLL that can provide its required
+ * clock net, and if there is a protocol converter for that mode on that lane.
+ */
+static bool lynx_28g_supports_lane_mode(struct lynx_28g_lane *lane,
enum lynx_lane_mode mode)
{
+ struct lynx_28g_priv *priv = lane->priv;
int i;
+ if (!priv->info->lane_supports_mode(lane->id, mode))
+ return false;
+
for (i = 0; i < LYNX_28G_NUM_PLL; i++) {
if (PLLnRSTCTL_DIS(priv->pll[i].rstctl))
continue;
@@ -687,6 +700,86 @@ static int lynx_28g_get_pcvt_offset(int lane, enum lynx_lane_mode lane_mode)
}
}
+static bool lx2160a_serdes1_lane_supports_mode(int lane,
+ enum lynx_lane_mode mode)
+{
+ return true;
+}
+
+static bool lx2160a_serdes2_lane_supports_mode(int lane,
+ enum lynx_lane_mode mode)
+{
+ switch (mode) {
+ case LANE_MODE_1000BASEX_SGMII:
+ return true;
+ case LANE_MODE_USXGMII:
+ case LANE_MODE_10GBASER:
+ return lane == 6 || lane == 7;
+ default:
+ return false;
+ }
+}
+
+static bool lx2160a_serdes3_lane_supports_mode(int lane,
+ enum lynx_lane_mode mode)
+{
+ /*
+ * Non-networking SerDes, and this driver supports only
+ * networking protocols
+ */
+ return false;
+}
+
+static bool lx2162a_serdes1_lane_supports_mode(int lane,
+ enum lynx_lane_mode mode)
+{
+ return true;
+}
+
+static bool lx2162a_serdes2_lane_supports_mode(int lane,
+ enum lynx_lane_mode mode)
+{
+ return lx2160a_serdes2_lane_supports_mode(lane, mode);
+}
+
+static bool lynx_28g_compat_lane_supports_mode(int lane,
+ enum lynx_lane_mode mode)
+{
+ switch (mode) {
+ case LANE_MODE_1000BASEX_SGMII:
+ case LANE_MODE_USXGMII:
+ case LANE_MODE_10GBASER:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static const struct lynx_info lynx_info_compat = {
+ .lane_supports_mode = lynx_28g_compat_lane_supports_mode,
+};
+
+static const struct lynx_info lynx_info_lx2160a_serdes1 = {
+ .lane_supports_mode = lx2160a_serdes1_lane_supports_mode,
+};
+
+static const struct lynx_info lynx_info_lx2160a_serdes2 = {
+ .lane_supports_mode = lx2160a_serdes2_lane_supports_mode,
+};
+
+static const struct lynx_info lynx_info_lx2160a_serdes3 = {
+ .lane_supports_mode = lx2160a_serdes3_lane_supports_mode,
+};
+
+static const struct lynx_info lynx_info_lx2162a_serdes1 = {
+ .lane_supports_mode = lx2162a_serdes1_lane_supports_mode,
+ .first_lane = 4,
+};
+
+static const struct lynx_info lynx_info_lx2162a_serdes2 = {
+ .lane_supports_mode = lx2162a_serdes2_lane_supports_mode,
+};
+
static int lynx_pccr_read(struct lynx_28g_lane *lane, enum lynx_lane_mode mode,
u32 *val)
{
@@ -939,7 +1032,6 @@ static int lynx_28g_lane_enable_pcvt(struct lynx_28g_lane *lane,
static int lynx_28g_set_mode(struct phy *phy, enum phy_mode mode, int submode)
{
struct lynx_28g_lane *lane = phy_get_drvdata(phy);
- struct lynx_28g_priv *priv = lane->priv;
int powered_up = lane->powered_up;
enum lynx_lane_mode lane_mode;
int err = 0;
@@ -951,7 +1043,7 @@ static int lynx_28g_set_mode(struct phy *phy, enum phy_mode mode, int submode)
return -EOPNOTSUPP;
lane_mode = phy_interface_to_lane_mode(submode);
- if (!lynx_28g_supports_lane_mode(priv, lane_mode))
+ if (!lynx_28g_supports_lane_mode(lane, lane_mode))
return -EOPNOTSUPP;
if (lane_mode == lane->mode)
@@ -984,14 +1076,13 @@ static int lynx_28g_validate(struct phy *phy, enum phy_mode mode, int submode,
union phy_configure_opts *opts __always_unused)
{
struct lynx_28g_lane *lane = phy_get_drvdata(phy);
- struct lynx_28g_priv *priv = lane->priv;
enum lynx_lane_mode lane_mode;
if (mode != PHY_MODE_ETHERNET)
return -EOPNOTSUPP;
lane_mode = phy_interface_to_lane_mode(submode);
- if (!lynx_28g_supports_lane_mode(priv, lane_mode))
+ if (!lynx_28g_supports_lane_mode(lane, lane_mode))
return -EOPNOTSUPP;
return 0;
@@ -1067,8 +1158,10 @@ static void lynx_28g_cdr_lock_check(struct work_struct *work)
u32 rrstctl;
int i;
- for (i = 0; i < LYNX_28G_NUM_LANE; i++) {
+ for (i = priv->info->first_lane; i < LYNX_28G_NUM_LANE; i++) {
lane = &priv->lane[i];
+ if (!lane->phy)
+ continue;
mutex_lock(&lane->phy->mutex);
@@ -1120,24 +1213,48 @@ static struct phy *lynx_28g_xlate(struct device *dev,
struct lynx_28g_priv *priv = dev_get_drvdata(dev);
int idx = args->args[0];
- if (WARN_ON(idx >= LYNX_28G_NUM_LANE))
+ if (WARN_ON(idx >= LYNX_28G_NUM_LANE ||
+ idx < priv->info->first_lane))
return ERR_PTR(-EINVAL);
return priv->lane[idx].phy;
}
+static int lynx_28g_probe_lane(struct lynx_28g_priv *priv, int id,
+ struct device_node *dn)
+{
+ struct lynx_28g_lane *lane = &priv->lane[id];
+ struct phy *phy;
+
+ memset(lane, 0, sizeof(*lane));
+
+ phy = devm_phy_create(priv->dev, dn, &lynx_28g_ops);
+ if (IS_ERR(phy))
+ return PTR_ERR(phy);
+
+ lane->priv = priv;
+ lane->phy = phy;
+ lane->id = id;
+ phy_set_drvdata(phy, lane);
+ lynx_28g_lane_read_configuration(lane);
+
+ return 0;
+}
+
static int lynx_28g_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
+ bool lane_phy_providers = true;
struct phy_provider *provider;
struct lynx_28g_priv *priv;
- int i;
+ int err;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->dev = dev;
+ priv->info = of_device_get_match_data(dev);
dev_set_drvdata(dev, priv);
spin_lock_init(&priv->pcc_lock);
INIT_DELAYED_WORK(&priv->cdr_check, lynx_28g_cdr_lock_check);
@@ -1146,26 +1263,60 @@ static int lynx_28g_probe(struct platform_device *pdev)
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
- lynx_28g_pll_read_configuration(priv);
+ if (priv->info == &lynx_info_compat) {
+ /*
+ * If we get here it means we probed on a device tree where
+ * "fsl,lynx-28g" wasn't the fallback, but the sole compatible
+ * string.
+ */
+ dev_warn(dev, "Please update device tree to use per-device compatible strings\n");
+ lane_phy_providers = false;
+ }
- for (i = 0; i < LYNX_28G_NUM_LANE; i++) {
- struct lynx_28g_lane *lane = &priv->lane[i];
- struct phy *phy;
+ lynx_28g_pll_read_configuration(priv);
- memset(lane, 0, sizeof(*lane));
+ if (lane_phy_providers) {
+ struct device_node *dn = dev_of_node(dev), *child;
+
+ for_each_available_child_of_node(dn, child) {
+ u32 reg;
+
+ /* PHY subnode name must be 'phy'. */
+ if (!(of_node_name_eq(child, "phy")))
+ continue;
+
+ if (of_property_read_u32(child, "reg", ®)) {
+ dev_err(dev, "No \"reg\" property for %pOF\n", child);
+ of_node_put(child);
+ return -EINVAL;
+ }
+
+ if (reg < priv->info->first_lane || reg >= LYNX_28G_NUM_LANE) {
+ dev_err(dev, "\"reg\" property out of range for %pOF\n", child);
+ of_node_put(child);
+ return -EINVAL;
+ }
+
+ err = lynx_28g_probe_lane(priv, reg, child);
+ if (err) {
+ of_node_put(child);
+ return err;
+ }
+ }
- phy = devm_phy_create(dev, NULL, &lynx_28g_ops);
- if (IS_ERR(phy))
- return PTR_ERR(phy);
+ provider = devm_of_phy_provider_register(&pdev->dev,
+ of_phy_simple_xlate);
+ } else {
+ for (int i = priv->info->first_lane; i < LYNX_28G_NUM_LANE; i++) {
+ err = lynx_28g_probe_lane(priv, i, NULL);
+ if (err)
+ return err;
+ }
- lane->priv = priv;
- lane->phy = phy;
- lane->id = i;
- phy_set_drvdata(phy, lane);
- lynx_28g_lane_read_configuration(lane);
+ provider = devm_of_phy_provider_register(&pdev->dev,
+ lynx_28g_xlate);
}
- provider = devm_of_phy_provider_register(dev, lynx_28g_xlate);
if (IS_ERR(provider))
return PTR_ERR(provider);
@@ -1184,7 +1335,12 @@ static void lynx_28g_remove(struct platform_device *pdev)
}
static const struct of_device_id lynx_28g_of_match_table[] = {
- { .compatible = "fsl,lynx-28g" },
+ { .compatible = "fsl,lx2160a-serdes1", .data = &lynx_info_lx2160a_serdes1 },
+ { .compatible = "fsl,lx2160a-serdes2", .data = &lynx_info_lx2160a_serdes2 },
+ { .compatible = "fsl,lx2160a-serdes3", .data = &lynx_info_lx2160a_serdes3 },
+ { .compatible = "fsl,lx2162a-serdes1", .data = &lynx_info_lx2162a_serdes1 },
+ { .compatible = "fsl,lx2162a-serdes2", .data = &lynx_info_lx2162a_serdes2 },
+ { .compatible = "fsl,lynx-28g", .data = &lynx_info_compat }, /* fallback, keep last */
{ },
};
MODULE_DEVICE_TABLE(of, lynx_28g_of_match_table);
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v3 phy 14/17] phy: lynx-28g: add support for 25GBASER
2025-09-26 18:04 [PATCH v3 phy 00/17] Lynx 28G improvements part 1 Vladimir Oltean
` (12 preceding siblings ...)
2025-09-26 18:05 ` [PATCH v3 phy 13/17] phy: lynx-28g: probe on per-SoC and per-instance compatible strings Vladimir Oltean
@ 2025-09-26 18:05 ` Vladimir Oltean
2025-09-26 18:05 ` [PATCH v3 phy 15/17] phy: lynx-28g: use timeouts when waiting for lane halt and reset Vladimir Oltean
` (2 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Vladimir Oltean @ 2025-09-26 18:05 UTC (permalink / raw)
To: linux-phy
Cc: Ioana Ciornei, Vinod Koul, Kishon Vijay Abraham I, Josua Mayer,
linux-kernel
From: Ioana Ciornei <ioana.ciornei@nxp.com>
Add support for 25GBASE-R in the Lynx 28G SerDes PHY driver.
This mainly means being able to determine if a PLL is able to support
the new interface type, to determine at probe time if a lane is
configured from the Reset Configuration Word (RCW) with this interface
type and to be able to reconfigure a lane.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
v2->v3: none
v1->v2: implement missing lane_supports_mode() restrictions for 25GbE
drivers/phy/freescale/phy-fsl-lynx-28g.c | 90 +++++++++++++++++++++++-
1 file changed, 88 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
index 1ddca8b4de17..aaec680e813f 100644
--- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
+++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
@@ -57,6 +57,7 @@
#define PLLnCR1_FRATE_5G_10GVCO 0x0
#define PLLnCR1_FRATE_5G_25GVCO 0x10
#define PLLnCR1_FRATE_10G_20GVCO 0x6
+#define PLLnCR1_FRATE_12G_25GVCO 0x16
/* Per SerDes lane registers */
/* Lane a General Control Register */
@@ -64,9 +65,11 @@
#define LNaGCR0_PROTO_SEL GENMASK(7, 3)
#define LNaGCR0_PROTO_SEL_SGMII 0x1
#define LNaGCR0_PROTO_SEL_XFI 0xa
+#define LNaGCR0_PROTO_SEL_25G 0x1a
#define LNaGCR0_IF_WIDTH GENMASK(2, 0)
#define LNaGCR0_IF_WIDTH_10_BIT 0x0
#define LNaGCR0_IF_WIDTH_20_BIT 0x2
+#define LNaGCR0_IF_WIDTH_40_BIT 0x4
/* Lane a Tx Reset Control Register */
#define LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20)
@@ -83,6 +86,7 @@
#define LNaTGCR0_N_RATE_FULL 0x0
#define LNaTGCR0_N_RATE_HALF 0x1
#define LNaTGCR0_N_RATE_QUARTER 0x2
+#define LNaTGCR0_N_RATE_DOUBLE 0x3
#define LNaTECR0(lane) (0x800 + (lane) * 0x100 + 0x30)
#define LNaTECR0_EQ_TYPE GENMASK(30, 28)
@@ -112,6 +116,7 @@
#define LNaRGCR0_N_RATE_FULL 0x0
#define LNaRGCR0_N_RATE_HALF 0x1
#define LNaRGCR0_N_RATE_QUARTER 0x2
+#define LNaRGCR0_N_RATE_DOUBLE 0x3
#define LNaRGCR1(lane) (0x800 + (lane) * 0x100 + 0x48)
#define LNaRGCR1_RX_ORD_ELECIDLE BIT(31)
@@ -269,6 +274,7 @@ enum lynx_lane_mode {
LANE_MODE_1000BASEX_SGMII,
LANE_MODE_10GBASER,
LANE_MODE_USXGMII,
+ LANE_MODE_25GBASER,
LANE_MODE_MAX,
};
@@ -407,6 +413,41 @@ static const struct lynx_28g_proto_conf lynx_28g_proto_conf[LANE_MODE_MAX] = {
.ttlcr0 = LNaTTLCR0_TTL_SLO_PM_BYP |
LNaTTLCR0_DATA_IN_SSC,
},
+ [LANE_MODE_25GBASER] = {
+ .proto_sel = LNaGCR0_PROTO_SEL_25G,
+ .if_width = LNaGCR0_IF_WIDTH_40_BIT,
+ .teq_type = EQ_TYPE_3TAP,
+ .sgn_preq = 1,
+ .ratio_preq = 2,
+ .sgn_post1q = 1,
+ .ratio_post1q = 7,
+ .amp_red = 0,
+ .adpt_eq = 48,
+ .enter_idle_flt_sel = 0,
+ .exit_idle_flt_sel = 0,
+ .data_lost_th_sel = 0,
+ .gk2ovd = 0,
+ .gk3ovd = 0,
+ .gk4ovd = 5,
+ .gk2ovd_en = 0,
+ .gk3ovd_en = 0,
+ .gk4ovd_en = 1,
+ .eq_offset_ovd = 0x1f,
+ .eq_offset_ovd_en = 0,
+ .eq_offset_rng_dbl = 1,
+ .eq_blw_sel = 1,
+ .eq_boost = 2,
+ .spare_in = 3,
+ .smp_autoz_d1r = 2,
+ .smp_autoz_eg1r = 2,
+ .rccr0 = LNaRCCR0_CAL_EN |
+ LNaRCCR0_CAL_DC3_DIS |
+ LNaRCCR0_CAL_DC2_DIS |
+ LNaRCCR0_CAL_DC1_DIS |
+ LNaRCCR0_CAL_DC0_DIS,
+ .ttlcr0 = LNaTTLCR0_DATA_IN_SSC |
+ FIELD_PREP_CONST(LNaTTLCR0_CDR_MIN_SMP_ON, 1),
+ },
};
struct lynx_pccr {
@@ -486,6 +527,8 @@ static const char *lynx_lane_mode_str(enum lynx_lane_mode lane_mode)
return "10GBase-R";
case LANE_MODE_USXGMII:
return "USXGMII";
+ case LANE_MODE_25GBASER:
+ return "25GBase-R";
default:
return "unknown";
}
@@ -501,6 +544,8 @@ static enum lynx_lane_mode phy_interface_to_lane_mode(phy_interface_t intf)
return LANE_MODE_10GBASER;
case PHY_INTERFACE_MODE_USXGMII:
return LANE_MODE_USXGMII;
+ case PHY_INTERFACE_MODE_25GBASER:
+ return LANE_MODE_25GBASER;
default:
return LANE_MODE_UNKNOWN;
}
@@ -588,6 +633,20 @@ static void lynx_28g_lane_set_nrate(struct lynx_28g_lane *lane,
break;
}
break;
+ case PLLnCR1_FRATE_12G_25GVCO:
+ switch (lane_mode) {
+ case LANE_MODE_25GBASER:
+ lynx_28g_lane_rmw(lane, LNaTGCR0,
+ FIELD_PREP(LNaTGCR0_N_RATE, LNaTGCR0_N_RATE_DOUBLE),
+ LNaTGCR0_N_RATE);
+ lynx_28g_lane_rmw(lane, LNaRGCR0,
+ FIELD_PREP(LNaRGCR0_N_RATE, LNaRGCR0_N_RATE_DOUBLE),
+ LNaRGCR0_N_RATE);
+ break;
+ default:
+ break;
+ }
+ break;
default:
break;
}
@@ -665,6 +724,11 @@ static int lynx_28g_power_on(struct phy *phy)
return 0;
}
+static int lynx_28g_e25g_pcvt(int lane)
+{
+ return 7 - lane;
+}
+
static int lynx_28g_get_pccr(enum lynx_lane_mode lane_mode, int lane,
struct lynx_pccr *pccr)
{
@@ -680,6 +744,11 @@ static int lynx_28g_get_pccr(enum lynx_lane_mode lane_mode, int lane,
pccr->width = 4;
pccr->shift = SXGMII_CFG(lane);
break;
+ case LANE_MODE_25GBASER:
+ pccr->offset = PCCD;
+ pccr->width = 4;
+ pccr->shift = E25G_CFG(lynx_28g_e25g_pcvt(lane));
+ break;
default:
return -EOPNOTSUPP;
}
@@ -695,6 +764,8 @@ static int lynx_28g_get_pcvt_offset(int lane, enum lynx_lane_mode lane_mode)
case LANE_MODE_USXGMII:
case LANE_MODE_10GBASER:
return SXGMIIaCR0(lane);
+ case LANE_MODE_25GBASER:
+ return E25GaCR0(lynx_28g_e25g_pcvt(lane));
default:
return -EOPNOTSUPP;
}
@@ -703,7 +774,12 @@ static int lynx_28g_get_pcvt_offset(int lane, enum lynx_lane_mode lane_mode)
static bool lx2160a_serdes1_lane_supports_mode(int lane,
enum lynx_lane_mode mode)
{
- return true;
+ switch (mode) {
+ case LANE_MODE_25GBASER:
+ return lane != 2 && lane != 3;
+ default:
+ return true;
+ }
}
static bool lx2160a_serdes2_lane_supports_mode(int lane,
@@ -1018,6 +1094,9 @@ static int lynx_28g_lane_enable_pcvt(struct lynx_28g_lane *lane,
case LANE_MODE_USXGMII:
val |= PCCC_SXGMIIn_CFG;
break;
+ case LANE_MODE_25GBASER:
+ val |= PCCD_E25Gn_CFG;
+ break;
default:
break;
}
@@ -1142,8 +1221,12 @@ static void lynx_28g_pll_read_configuration(struct lynx_28g_priv *priv)
__set_bit(LANE_MODE_10GBASER, pll->supported);
__set_bit(LANE_MODE_USXGMII, pll->supported);
break;
+ case PLLnCR1_FRATE_12G_25GVCO:
+ /* 12.890625GHz clock net */
+ __set_bit(LANE_MODE_25GBASER, pll->supported);
+ break;
default:
- /* 6GHz, 12.890625GHz, 8GHz */
+ /* 6GHz, 8GHz */
break;
}
}
@@ -1202,6 +1285,9 @@ static void lynx_28g_lane_read_configuration(struct lynx_28g_lane *lane)
else
lane->mode = LANE_MODE_USXGMII;
break;
+ case LNaPSS_TYPE_25G:
+ lane->mode = LANE_MODE_25GBASER;
+ break;
default:
lane->mode = LANE_MODE_UNKNOWN;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v3 phy 15/17] phy: lynx-28g: use timeouts when waiting for lane halt and reset
2025-09-26 18:04 [PATCH v3 phy 00/17] Lynx 28G improvements part 1 Vladimir Oltean
` (13 preceding siblings ...)
2025-09-26 18:05 ` [PATCH v3 phy 14/17] phy: lynx-28g: add support for 25GBASER Vladimir Oltean
@ 2025-09-26 18:05 ` Vladimir Oltean
2025-09-26 18:05 ` [PATCH v3 phy 16/17] phy: lynx-28g: truly power the lanes up or down Vladimir Oltean
2025-09-26 18:05 ` [PATCH v3 phy 17/17] phy: lynx-28g: implement phy_exit() operation Vladimir Oltean
16 siblings, 0 replies; 26+ messages in thread
From: Vladimir Oltean @ 2025-09-26 18:05 UTC (permalink / raw)
To: linux-phy
Cc: Ioana Ciornei, Vinod Koul, Kishon Vijay Abraham I, Josua Mayer,
linux-kernel
There are various circumstances in which a lane halt, or a lane reset,
will fail to complete. If this happens, it will hang the kernel, which
only implements a busy loop with no timeout.
The circumstances in which this will happen are all bugs in nature:
- if we try to power off a powered off lane
- if we try to power off a lane that uses a PLL locked onto the wrong
refclk frequency
Actually, unbounded loops in the kernel are a bad practice, so let's use
read_poll_timeout() with a custom function that reads both LNaTRSTCTL
(lane transmit control register) and LNaRRSTCTL (lane receive control
register) and returns true when the request is done in both directions.
The HLT_REQ bit has to clear, whereas the RST_DONE bit has to get set.
Suggested-by: Josua Mayer <josua@solid-run.com>
Link: https://lore.kernel.org/lkml/d0c8bbf8-a0c5-469f-a148-de2235948c0f@solid-run.com/
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
v2->v3: patch is new
drivers/phy/freescale/phy-fsl-lynx-28g.c | 96 ++++++++++++++++++------
1 file changed, 74 insertions(+), 22 deletions(-)
diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
index aaec680e813f..4e3ff7ef47e4 100644
--- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
+++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
@@ -254,6 +254,12 @@
#define CR(x) ((x) * 4)
+#define LYNX_28G_LANE_HALT_SLEEP_US 100
+#define LYNX_28G_LANE_HALT_TIMEOUT_US 1000000
+
+#define LYNX_28G_LANE_RESET_SLEEP_US 100
+#define LYNX_28G_LANE_RESET_TIMEOUT_US 1000000
+
enum lynx_28g_eq_type {
EQ_TYPE_NO_EQ = 0,
EQ_TYPE_2TAP = 1,
@@ -672,10 +678,29 @@ static void lynx_28g_lane_set_pll(struct lynx_28g_lane *lane,
}
}
+static bool lynx_28g_lane_halt_done(struct lynx_28g_lane *lane)
+{
+ u32 trstctl = lynx_28g_lane_read(lane, LNaTRSTCTL);
+ u32 rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
+
+ return !(trstctl & LNaTRSTCTL_HLT_REQ) &&
+ !(rrstctl & LNaRRSTCTL_HLT_REQ);
+}
+
+static bool lynx_28g_lane_reset_done(struct lynx_28g_lane *lane)
+{
+ u32 trstctl = lynx_28g_lane_read(lane, LNaTRSTCTL);
+ u32 rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
+
+ return (trstctl & LNaTRSTCTL_RST_DONE) &&
+ (rrstctl & LNaRRSTCTL_RST_DONE);
+}
+
static int lynx_28g_power_off(struct phy *phy)
{
struct lynx_28g_lane *lane = phy_get_drvdata(phy);
- u32 trstctl, rrstctl;
+ bool done;
+ int err;
if (!lane->powered_up)
return 0;
@@ -687,11 +712,15 @@ static int lynx_28g_power_off(struct phy *phy)
LNaRRSTCTL_HLT_REQ);
/* Wait until the halting process is complete */
- do {
- trstctl = lynx_28g_lane_read(lane, LNaTRSTCTL);
- rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
- } while ((trstctl & LNaTRSTCTL_HLT_REQ) ||
- (rrstctl & LNaRRSTCTL_HLT_REQ));
+ err = read_poll_timeout(lynx_28g_lane_halt_done, done, done,
+ LYNX_28G_LANE_HALT_SLEEP_US,
+ LYNX_28G_LANE_HALT_TIMEOUT_US,
+ false, lane);
+ if (err) {
+ dev_err(&phy->dev, "Lane %c halt failed: %pe\n",
+ 'A' + lane->id, ERR_PTR(err));
+ return err;
+ }
lane->powered_up = false;
@@ -701,7 +730,8 @@ static int lynx_28g_power_off(struct phy *phy)
static int lynx_28g_power_on(struct phy *phy)
{
struct lynx_28g_lane *lane = phy_get_drvdata(phy);
- u32 trstctl, rrstctl;
+ bool done;
+ int err;
if (lane->powered_up)
return 0;
@@ -713,11 +743,15 @@ static int lynx_28g_power_on(struct phy *phy)
LNaRRSTCTL_RST_REQ);
/* Wait until the reset sequence is completed */
- do {
- trstctl = lynx_28g_lane_read(lane, LNaTRSTCTL);
- rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
- } while (!(trstctl & LNaTRSTCTL_RST_DONE) ||
- !(rrstctl & LNaRRSTCTL_RST_DONE));
+ err = read_poll_timeout(lynx_28g_lane_reset_done, done, done,
+ LYNX_28G_LANE_RESET_SLEEP_US,
+ LYNX_28G_LANE_RESET_TIMEOUT_US,
+ false, lane);
+ if (err) {
+ dev_err(&phy->dev, "Lane %c reset failed: %pe\n",
+ 'A' + lane->id, ERR_PTR(err));
+ return err;
+ }
lane->powered_up = true;
@@ -1131,8 +1165,11 @@ static int lynx_28g_set_mode(struct phy *phy, enum phy_mode mode, int submode)
/* If the lane is powered up, put the lane into the halt state while
* the reconfiguration is being done.
*/
- if (powered_up)
- lynx_28g_power_off(phy);
+ if (powered_up) {
+ err = lynx_28g_power_off(phy);
+ if (err)
+ return err;
+ }
err = lynx_28g_lane_disable_pcvt(lane, lane->mode);
if (err)
@@ -1145,8 +1182,16 @@ static int lynx_28g_set_mode(struct phy *phy, enum phy_mode mode, int submode)
lane->mode = lane_mode;
out:
- if (powered_up)
- lynx_28g_power_on(phy);
+ if (powered_up) {
+ int err2 = lynx_28g_power_on(phy);
+ /*
+ * Don't overwrite a failed protocol converter disable error
+ * code with a successful lane power on error code, but
+ * propagate a failed lane power on error.
+ */
+ if (!err)
+ err = err2;
+ }
return err;
}
@@ -1179,9 +1224,8 @@ static int lynx_28g_init(struct phy *phy)
* probe time.
*/
lane->powered_up = true;
- lynx_28g_power_off(phy);
- return 0;
+ return lynx_28g_power_off(phy);
}
static const struct phy_ops lynx_28g_ops = {
@@ -1239,7 +1283,7 @@ static void lynx_28g_cdr_lock_check(struct work_struct *work)
struct lynx_28g_priv *priv = work_to_lynx(work);
struct lynx_28g_lane *lane;
u32 rrstctl;
- int i;
+ int err, i;
for (i = priv->info->first_lane; i < LYNX_28G_NUM_LANE; i++) {
lane = &priv->lane[i];
@@ -1257,9 +1301,17 @@ static void lynx_28g_cdr_lock_check(struct work_struct *work)
if (!(rrstctl & LNaRRSTCTL_CDR_LOCK)) {
lynx_28g_lane_rmw(lane, LNaRRSTCTL, LNaRRSTCTL_RST_REQ,
LNaRRSTCTL_RST_REQ);
- do {
- rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
- } while (!(rrstctl & LNaRRSTCTL_RST_DONE));
+
+ err = read_poll_timeout(lynx_28g_lane_read, rrstctl,
+ !!(rrstctl & LNaRRSTCTL_RST_DONE),
+ LYNX_28G_LANE_RESET_SLEEP_US,
+ LYNX_28G_LANE_RESET_TIMEOUT_US,
+ false, lane, LNaRRSTCTL);
+ if (err) {
+ dev_warn_once(&lane->phy->dev,
+ "Lane %c receiver reset failed: %pe\n",
+ 'A' + lane->id, ERR_PTR(err));
+ }
}
mutex_unlock(&lane->phy->mutex);
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v3 phy 16/17] phy: lynx-28g: truly power the lanes up or down
2025-09-26 18:04 [PATCH v3 phy 00/17] Lynx 28G improvements part 1 Vladimir Oltean
` (14 preceding siblings ...)
2025-09-26 18:05 ` [PATCH v3 phy 15/17] phy: lynx-28g: use timeouts when waiting for lane halt and reset Vladimir Oltean
@ 2025-09-26 18:05 ` Vladimir Oltean
2025-09-26 18:05 ` [PATCH v3 phy 17/17] phy: lynx-28g: implement phy_exit() operation Vladimir Oltean
16 siblings, 0 replies; 26+ messages in thread
From: Vladimir Oltean @ 2025-09-26 18:05 UTC (permalink / raw)
To: linux-phy
Cc: Ioana Ciornei, Vinod Koul, Kishon Vijay Abraham I, Josua Mayer,
linux-kernel
The current procedure for power_off() and power_on() is the same as the
one used for major lane reconfiguration, aka halting.
But one would expect that a powered off lane causes the CDR (clock and
data recovery) loop of the link partner to lose lock onto its RX stream
(which suggests there are no longer any bit transitions => the channel
is inactive). However, this does not take place (the CDR lock is still
there), so a halted lane is still active.
Implement the procedure mentioned in the block guide for powering down
a lane, and then back on.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
v2->v3: reimplement lynx_28g_power_off() using read_poll_timeout()
v1->v2: slight commit message reword
drivers/phy/freescale/phy-fsl-lynx-28g.c | 99 ++++++++++++++++++++----
1 file changed, 83 insertions(+), 16 deletions(-)
diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
index 4e3ff7ef47e4..8e38acd30224 100644
--- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
+++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
@@ -73,9 +73,11 @@
/* Lane a Tx Reset Control Register */
#define LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20)
-#define LNaTRSTCTL_HLT_REQ BIT(27)
-#define LNaTRSTCTL_RST_DONE BIT(30)
#define LNaTRSTCTL_RST_REQ BIT(31)
+#define LNaTRSTCTL_RST_DONE BIT(30)
+#define LNaTRSTCTL_HLT_REQ BIT(27)
+#define LNaTRSTCTL_STP_REQ BIT(26)
+#define LNaTRSTCTL_DIS BIT(24)
/* Lane a Tx General Control Register */
#define LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24)
@@ -102,9 +104,11 @@
/* Lane a Rx Reset Control Register */
#define LNaRRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x40)
-#define LNaRRSTCTL_HLT_REQ BIT(27)
-#define LNaRRSTCTL_RST_DONE BIT(30)
#define LNaRRSTCTL_RST_REQ BIT(31)
+#define LNaRRSTCTL_RST_DONE BIT(30)
+#define LNaRRSTCTL_HLT_REQ BIT(27)
+#define LNaRRSTCTL_STP_REQ BIT(26)
+#define LNaRRSTCTL_DIS BIT(24)
#define LNaRRSTCTL_CDR_LOCK BIT(12)
/* Lane a Rx General Control Register */
@@ -260,6 +264,9 @@
#define LYNX_28G_LANE_RESET_SLEEP_US 100
#define LYNX_28G_LANE_RESET_TIMEOUT_US 1000000
+#define LYNX_28G_LANE_STOP_SLEEP_US 100
+#define LYNX_28G_LANE_STOP_TIMEOUT_US 1000000
+
enum lynx_28g_eq_type {
EQ_TYPE_NO_EQ = 0,
EQ_TYPE_2TAP = 1,
@@ -687,6 +694,15 @@ static bool lynx_28g_lane_halt_done(struct lynx_28g_lane *lane)
!(rrstctl & LNaRRSTCTL_HLT_REQ);
}
+static bool lynx_28g_lane_stop_done(struct lynx_28g_lane *lane)
+{
+ u32 trstctl = lynx_28g_lane_read(lane, LNaTRSTCTL);
+ u32 rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
+
+ return !(trstctl & LNaTRSTCTL_STP_REQ) &&
+ !(rrstctl & LNaRRSTCTL_STP_REQ);
+}
+
static bool lynx_28g_lane_reset_done(struct lynx_28g_lane *lane)
{
u32 trstctl = lynx_28g_lane_read(lane, LNaTRSTCTL);
@@ -696,15 +712,13 @@ static bool lynx_28g_lane_reset_done(struct lynx_28g_lane *lane)
(rrstctl & LNaRRSTCTL_RST_DONE);
}
-static int lynx_28g_power_off(struct phy *phy)
+/* Halting puts the lane in a mode in which it can be reconfigured */
+static int lynx_28g_lane_halt(struct phy *phy)
{
struct lynx_28g_lane *lane = phy_get_drvdata(phy);
bool done;
int err;
- if (!lane->powered_up)
- return 0;
-
/* Issue a halt request */
lynx_28g_lane_rmw(lane, LNaTRSTCTL, LNaTRSTCTL_HLT_REQ,
LNaTRSTCTL_HLT_REQ);
@@ -727,15 +741,12 @@ static int lynx_28g_power_off(struct phy *phy)
return 0;
}
-static int lynx_28g_power_on(struct phy *phy)
+static int lynx_28g_lane_reset(struct phy *phy)
{
struct lynx_28g_lane *lane = phy_get_drvdata(phy);
bool done;
int err;
- if (lane->powered_up)
- return 0;
-
/* Issue a reset request on the lane */
lynx_28g_lane_rmw(lane, LNaTRSTCTL, LNaTRSTCTL_RST_REQ,
LNaTRSTCTL_RST_REQ);
@@ -750,9 +761,64 @@ static int lynx_28g_power_on(struct phy *phy)
if (err) {
dev_err(&phy->dev, "Lane %c reset failed: %pe\n",
'A' + lane->id, ERR_PTR(err));
+ }
+
+ return err;
+}
+
+static int lynx_28g_power_off(struct phy *phy)
+{
+ struct lynx_28g_lane *lane = phy_get_drvdata(phy);
+ bool done;
+ int err;
+
+ if (!lane->powered_up)
+ return 0;
+
+ /* Issue a stop request */
+ lynx_28g_lane_rmw(lane, LNaTRSTCTL, LNaTRSTCTL_STP_REQ,
+ LNaTRSTCTL_STP_REQ);
+ lynx_28g_lane_rmw(lane, LNaRRSTCTL, LNaRRSTCTL_STP_REQ,
+ LNaRRSTCTL_STP_REQ);
+
+ /* Wait until the stop process is complete */
+ err = read_poll_timeout(lynx_28g_lane_stop_done, done, done,
+ LYNX_28G_LANE_STOP_SLEEP_US,
+ LYNX_28G_LANE_STOP_TIMEOUT_US,
+ false, lane);
+ if (err) {
+ dev_err(&phy->dev, "Lane %c stop failed: %pe\n",
+ 'A' + lane->id, ERR_PTR(err));
return err;
}
+ /* Power down the RX and TX portions of the lane */
+ lynx_28g_lane_rmw(lane, LNaRRSTCTL, LNaRRSTCTL_DIS,
+ LNaRRSTCTL_DIS);
+ lynx_28g_lane_rmw(lane, LNaTRSTCTL, LNaTRSTCTL_DIS,
+ LNaTRSTCTL_DIS);
+
+ lane->powered_up = false;
+
+ return 0;
+}
+
+static int lynx_28g_power_on(struct phy *phy)
+{
+ struct lynx_28g_lane *lane = phy_get_drvdata(phy);
+ int err;
+
+ if (lane->powered_up)
+ return 0;
+
+ /* Power up the RX and TX portions of the lane */
+ lynx_28g_lane_rmw(lane, LNaRRSTCTL, 0, LNaRRSTCTL_DIS);
+ lynx_28g_lane_rmw(lane, LNaTRSTCTL, 0, LNaTRSTCTL_DIS);
+
+ err = lynx_28g_lane_reset(phy);
+ if (err)
+ return err;
+
lane->powered_up = true;
return 0;
@@ -1166,7 +1232,7 @@ static int lynx_28g_set_mode(struct phy *phy, enum phy_mode mode, int submode)
* the reconfiguration is being done.
*/
if (powered_up) {
- err = lynx_28g_power_off(phy);
+ err = lynx_28g_lane_halt(phy);
if (err)
return err;
}
@@ -1182,12 +1248,13 @@ static int lynx_28g_set_mode(struct phy *phy, enum phy_mode mode, int submode)
lane->mode = lane_mode;
out:
+ /* Reset the lane if necessary */
if (powered_up) {
- int err2 = lynx_28g_power_on(phy);
+ int err2 = lynx_28g_lane_reset(phy);
/*
* Don't overwrite a failed protocol converter disable error
- * code with a successful lane power on error code, but
- * propagate a failed lane power on error.
+ * code with a successful lane reset error code, but propagate
+ * a failed lane reset error.
*/
if (!err)
err = err2;
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v3 phy 17/17] phy: lynx-28g: implement phy_exit() operation
2025-09-26 18:04 [PATCH v3 phy 00/17] Lynx 28G improvements part 1 Vladimir Oltean
` (15 preceding siblings ...)
2025-09-26 18:05 ` [PATCH v3 phy 16/17] phy: lynx-28g: truly power the lanes up or down Vladimir Oltean
@ 2025-09-26 18:05 ` Vladimir Oltean
16 siblings, 0 replies; 26+ messages in thread
From: Vladimir Oltean @ 2025-09-26 18:05 UTC (permalink / raw)
To: linux-phy
Cc: Ioana Ciornei, Vinod Koul, Kishon Vijay Abraham I, Josua Mayer,
linux-kernel
Managed lanes are supposed to have power management through
phy_power_on() and phy_power_off().
Unmanaged lanes are supposed to be always powered on, because they might
have a consumer which doesn't use this SerDes driver, and we don't want
to break it.
A lane is initially unmanaged, and becomes managed when phy_init() is
called on it.
It is normal for consumer drivers to call both phy_init() and
phy_exit(), in a balanced way. This ensures the phy->init_count from the
phy core is brought back to zero, for example during -EPROBE_DEFER in
the consumer, the lane temporarily becomes unmanaged and then managed
again.
Given the above requirement for consumers, it also imposes a requirement
for the SerDes driver to implement the exit() operation. Otherwise, a
balanced set of phy_init() and phy_exit() calls from the consumer will
effectively result in multiple lynx_28g_init() calls as seen by the
SerDes and nothing else. That actually doesn't work - the driver can't
power down a SerDes lane which is actually powered down, so such a call
sequence would hang the kernel.
No consumer driver currently uses phy_exit(), so the above problem does
not yet trigger, but in preparation for its introduction without any
regressions, it is necessary to add lynx_28g_exit() as the mirror of
lynx_28g_init().
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
v2->v3: propagate the potential -ETIMEDOUT error code from
lynx_28g_power_on() to the caller
v1->v2: slight commit message reword
drivers/phy/freescale/phy-fsl-lynx-28g.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
index 8e38acd30224..fef2b2d7d170 100644
--- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
+++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
@@ -1295,8 +1295,23 @@ static int lynx_28g_init(struct phy *phy)
return lynx_28g_power_off(phy);
}
+static int lynx_28g_exit(struct phy *phy)
+{
+ struct lynx_28g_lane *lane = phy_get_drvdata(phy);
+
+ /* The lane returns to the state where it isn't managed by the
+ * consumer, so we must treat is as if it isn't initialized, and always
+ * powered on.
+ */
+ lane->init = false;
+ lane->powered_up = false;
+
+ return lynx_28g_power_on(phy);
+}
+
static const struct phy_ops lynx_28g_ops = {
.init = lynx_28g_init,
+ .exit = lynx_28g_exit,
.power_on = lynx_28g_power_on,
.power_off = lynx_28g_power_off,
.set_mode = lynx_28g_set_mode,
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH v3 phy 12/17] dt-bindings: phy: lynx-28g: add compatible strings per SerDes and instantiation
2025-09-26 18:05 ` [PATCH v3 phy 12/17] dt-bindings: phy: lynx-28g: add compatible strings per SerDes and instantiation Vladimir Oltean
@ 2025-09-30 14:07 ` Vladimir Oltean
2025-10-02 3:03 ` Rob Herring
0 siblings, 1 reply; 26+ messages in thread
From: Vladimir Oltean @ 2025-09-30 14:07 UTC (permalink / raw)
To: Rob Herring, Josua Mayer
Cc: Ioana Ciornei, Vinod Koul, Kishon Vijay Abraham I, linux-kernel,
Krzysztof Kozlowski, Conor Dooley, devicetree, linux-phy
On Fri, Sep 26, 2025 at 09:05:00PM +0300, Vladimir Oltean wrote:
> Going by the generic "fsl,lynx-28g" compatible string and expecting all
> SerDes instantiations on all SoCs to use it was a mistake.
>
> They all share the same register map, sure, but the number of protocol
> converters and lanes which are instantiated differs in a way that isn't
> detectable by the programming interface.
>
> Using a separate compatible string per SerDes instantiation is
> sufficient for any device driver to distinguish these features and/or
> any instance-specific quirk. It also reflects how the SoC reference
> manual provides different tables with protocol combinations for each
> SerDes. NXP clearly documents these as not identical, and refers to them
> as such (SerDes 1, 2, etc).
>
> The other sufficient approach for Lynx 28G would be to list in the
> device tree all protocols supported by each lane. That would be
> insufficient for the very similar Lynx 10G SerDes however, for which
> there exists a higher degree of variability in the PCCR register values
> that need to be written per protocol. This attempt can be seen in this
> unmerged patch set for Lynx 10G:
> https://lore.kernel.org/linux-phy/20230413160607.4128315-3-sean.anderson@seco.com/
>
> but that approach is more drawn-out and more prone to errors, whereas
> this one is more succinct and obviously correct.
>
> One aspect which is different with the per-SoC compatible strings is
> that they have one PHY provider for each lane (and #phy-cells = <0> in
> lane sub-nodes), rather than "fsl,lynx-28g" which has a single PHY
> provider for all lanes (and #phy-cells = <1> in the top-level node).
>
> This is done to fulfill Josua Mayer's request:
> https://lore.kernel.org/lkml/02270f62-9334-400c-b7b9-7e6a44dbbfc9@solid-run.com/
> to have OF nodes for each lane, so that we can further apply schemas
> such as Documentation/devicetree/bindings/phy/transmit-amplitude.yaml
> individually.
>
> This is the easiest and most intuitive way to describe that. The above
> is not the only electrical tuning that needs to be done, but rather the
> only one currently standardized in a schema. TX equalization parameters
> are TBD, but we need to not limit ourselves to just what currently exists.
>
> Luckily, we can overlap the modern binding format over the legacy one
> and they can coexist without interfering. Old kernels use compatible =
> "fsl,lynx-28g" and the top-level PHY provider, whereas new kernels probe
> on e.g. compatible = "fsl,lx2160a-serdes1" and use the per-lane PHY
> providers.
>
> Overlaying modern on top of legacy is only necessary for SerDes 1 and 2.
> LX2160A SerDes #3 (a non-networking SerDes) is not yet present in any
> device trees in circulation, and will only have the device-specific
> compatible (even though it shares the Lynx 28G programming model,
> specifying the "fsl,lynx-28g" compatible string for it provides no
> benefit that I can see).
>
> Change the expected name of the top-level node to "serdes", and update
> the example too.
>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
> v2->v3:
> - re-add "fsl,lynx-28g" as fallback compatible, and #phy-cells = <1> in
> top-level "serdes" node
> - drop useless description texts
> - fix text formatting
> - schema is more lax to allow overlaying old and new required properties
> v1->v2:
> - drop the usage of "fsl,lynx-28g" as a fallback compatible
> - mark "fsl,lynx-28g" as deprecated
> - implement Josua's request for per-lane OF nodes for the new compatible
> strings
>
> .../devicetree/bindings/phy/fsl,lynx-28g.yaml | 159 +++++++++++++++++-
> 1 file changed, 152 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml b/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml
> index ff9f9ca0f19c..e8b3a48b9515 100644
> --- a/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml
> +++ b/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml
> @@ -9,21 +9,123 @@ title: Freescale Lynx 28G SerDes PHY
> maintainers:
> - Ioana Ciornei <ioana.ciornei@nxp.com>
>
> +description:
> + The Lynx 28G is a multi-lane, multi-protocol SerDes (PCIe, SATA, Ethernet)
> + present in multiple instances on NXP LX2160A and LX2162A SoCs. All instances
> + share a common register map and programming model, however they differ in
> + supported protocols per lane in a way that is not detectable by said
> + programming model without prior knowledge. The distinction is made through
> + the compatible string.
> +
> properties:
> compatible:
> - enum:
> - - fsl,lynx-28g
> + oneOf:
> + - const: fsl,lynx-28g
> + deprecated: true
> + description:
> + Legacy compatibility string for Lynx 28G SerDes. Any assumption
> + regarding whether a certain lane supports a certain protocol may
> + be incorrect. Deprecated except when used as a fallback. Use
> + device-specific strings instead.
> + - items:
> + - const: fsl,lx2160a-serdes1
> + - const: fsl,lynx-28g
> + - items:
> + - const: fsl,lx2160a-serdes2
> + - const: fsl,lynx-28g
> + - items:
> + - const: fsl,lx2162a-serdes1
> + - const: fsl,lynx-28g
> + - items:
> + - const: fsl,lx2162a-serdes2
> + - const: fsl,lynx-28g
> + - const: fsl,lx2160a-serdes3
>
> reg:
> maxItems: 1
>
> - "#phy-cells":
> - const: 1
> + "#address-cells": true
> +
> + "#size-cells": true
> +
> + "#phy-cells": true
> +
> +patternProperties:
> + "^phy@[0-9a-f]+$":
> + type: object
> + description: Individual SerDes lane acting as PHY provider
> +
> + properties:
> + reg:
> + description: Lane index as seen in register map
> + maxItems: 1
> +
> + "#phy-cells":
> + const: 0
> +
> + required:
> + - reg
> + - "#phy-cells"
> +
> + additionalProperties: false
>
> required:
> - compatible
> - reg
> - - "#phy-cells"
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: fsl,lynx-28g
> + then:
> + # Legacy case: parent is the PHY provider, cell encodes lane index
> + properties:
> + "#phy-cells":
> + const: 1
> + required:
> + - "#phy-cells"
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - fsl,lx2160a-serdes1
> + - fsl,lx2160a-serdes2
> + - fsl,lx2160a-serdes3
> + - fsl,lx2162a-serdes1
> + - fsl,lx2162a-serdes2
> + then:
> + # Modern binding: lanes must have their own nodes
> + properties:
> + "#address-cells":
> + const: 1
> + "#size-cells":
> + const: 0
> + required:
> + - "#address-cells"
> + - "#size-cells"
> +
> + # LX2162A SerDes 1 has fewer lanes than the others
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: fsl,lx2162a-serdes1
> + then:
> + patternProperties:
> + "^phy@[0-9a-f]+$":
> + properties:
> + reg:
> + enum: [4, 5, 6, 7]
> + else:
> + patternProperties:
> + "^phy@[0-9a-f]+$":
> + properties:
> + reg:
> + enum: [0, 1, 2, 3, 4, 5, 6, 7]
>
> additionalProperties: false
>
> @@ -32,9 +134,52 @@ examples:
> soc {
> #address-cells = <2>;
> #size-cells = <2>;
> - serdes_1: phy@1ea0000 {
> - compatible = "fsl,lynx-28g";
> +
> + serdes_1: serdes@1ea0000 {
> + compatible = "fsl,lx2160a-serdes1", "fsl,lynx-28g";
> reg = <0x0 0x1ea0000 0x0 0x1e30>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> #phy-cells = <1>;
> +
> + phy@0 {
> + reg = <0>;
> + #phy-cells = <0>;
> + };
> +
> + phy@1 {
> + reg = <1>;
> + #phy-cells = <0>;
> + };
> +
> + phy@2 {
> + reg = <2>;
> + #phy-cells = <0>;
> + };
> +
> + phy@3 {
> + reg = <3>;
> + #phy-cells = <0>;
> + };
> +
> + phy@4 {
> + reg = <4>;
> + #phy-cells = <0>;
> + };
> +
> + phy@5 {
> + reg = <5>;
> + #phy-cells = <0>;
> + };
> +
> + phy@6 {
> + reg = <6>;
> + #phy-cells = <0>;
> + };
> +
> + phy@7 {
> + reg = <7>;
> + #phy-cells = <0>;
> + };
> };
> };
> --
> 2.34.1
>
I should have realized sooner when Rob/Josua requested the changes for
backwards schema compatibility in v2:
https://lore.kernel.org/lkml/20250925080317.2ocgybitliwddhcf@skbuf/
that despite our attempts to preserve compatibility with old kernels,
we actually fail to do that. Actually I should have documented my
earlier thought process better, where I already came to that conclusion,
but which I had forgotten when told that this could work...
The SerDes schema itself is technically backwards-compatible, but the
problem is with consumers, which aren't. In old device trees, they have:
phys = <&serdes_1 0>;
and in new ones, they have:
phys = <&serdes_1_lane_a>;
Because the consumer has a single "phys" phandle to the PHY provider, it
either has to point to one, or to the other. But on old kernels, we do
not register PHY providers per lane, so "phys = <&serdes_1_lane_a>"
results in a broken reference.
There are 2 directions to go from here:
1. Have optional per-lane "phy" OF node children, which exist solely for
tuning electrical parameters. We need to keep the top-level SerDes as
the only PHY provider, with #phy-cells = <1> denoting the lane.
2. Accept that keeping "fsl,lynx-28g" and overlaid properties has
absolutely no practical benefit, and drop them (effectively returning
to Conor's suggestion, as implemented in v2)
3. Extend the schema and the driver support for it as a backportable bug
fix, to allow registering PHY providers for lanes with OF nodes in
stable kernels. This avoids regressing when the device trees are
updated, assuming the stable kernel is also updated.
It's not that I particularly like #2, but going with #1 would imply that
lane OF nodes exist, but the "phys" phandles do not point to them.
Combine that with the fact that anything we do with the 28G Lynx
bindings will have to be replicated, for uniformity's sake, with the
upcoming 10G Lynx SerDes binding (very similar hardware IP), and #1 is
suddenly not looking so pretty at all. I.e. introducing the 10G Lynx
bindings like the 28G Lynx ones would mean deviating from the widely
established norm, and introducing them like the widely established norm
would mean deviating from the 28G Lynx. I can easily see how someone
might look at them one day and think "hmm, can't we make them more
uniform?"
OTOH, the fact that device tree updates require kernel updates (as
implied by #2) is acceptably by everyone in this thread who expressed an
opinion on this topic.
As for option #3, while IMO it would be a justified "new feature as
bug fix", it sounds a bit counterintuitive and I'm afraid I won't manage
to convince all maintainers along the way that this is the way forward.
I'll wait for the merge window to close before reposting anything, but
I'd like an explicit ack from Rob and Josua in the meantime, whose
change request I'd be effectively reverting, to make sure that this
topic is closed.
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v3 phy 12/17] dt-bindings: phy: lynx-28g: add compatible strings per SerDes and instantiation
2025-09-30 14:07 ` Vladimir Oltean
@ 2025-10-02 3:03 ` Rob Herring
2025-10-02 10:08 ` Josua Mayer
0 siblings, 1 reply; 26+ messages in thread
From: Rob Herring @ 2025-10-02 3:03 UTC (permalink / raw)
To: Vladimir Oltean
Cc: Josua Mayer, Ioana Ciornei, Vinod Koul, Kishon Vijay Abraham I,
linux-kernel, Krzysztof Kozlowski, Conor Dooley, devicetree,
linux-phy
On Tue, Sep 30, 2025 at 05:07:35PM +0300, Vladimir Oltean wrote:
> On Fri, Sep 26, 2025 at 09:05:00PM +0300, Vladimir Oltean wrote:
> > Going by the generic "fsl,lynx-28g" compatible string and expecting all
> > SerDes instantiations on all SoCs to use it was a mistake.
> >
> > They all share the same register map, sure, but the number of protocol
> > converters and lanes which are instantiated differs in a way that isn't
> > detectable by the programming interface.
> >
> > Using a separate compatible string per SerDes instantiation is
> > sufficient for any device driver to distinguish these features and/or
> > any instance-specific quirk. It also reflects how the SoC reference
> > manual provides different tables with protocol combinations for each
> > SerDes. NXP clearly documents these as not identical, and refers to them
> > as such (SerDes 1, 2, etc).
> >
> > The other sufficient approach for Lynx 28G would be to list in the
> > device tree all protocols supported by each lane. That would be
> > insufficient for the very similar Lynx 10G SerDes however, for which
> > there exists a higher degree of variability in the PCCR register values
> > that need to be written per protocol. This attempt can be seen in this
> > unmerged patch set for Lynx 10G:
> > https://lore.kernel.org/linux-phy/20230413160607.4128315-3-sean.anderson@seco.com/
> >
> > but that approach is more drawn-out and more prone to errors, whereas
> > this one is more succinct and obviously correct.
> >
> > One aspect which is different with the per-SoC compatible strings is
> > that they have one PHY provider for each lane (and #phy-cells = <0> in
> > lane sub-nodes), rather than "fsl,lynx-28g" which has a single PHY
> > provider for all lanes (and #phy-cells = <1> in the top-level node).
> >
> > This is done to fulfill Josua Mayer's request:
> > https://lore.kernel.org/lkml/02270f62-9334-400c-b7b9-7e6a44dbbfc9@solid-run.com/
> > to have OF nodes for each lane, so that we can further apply schemas
> > such as Documentation/devicetree/bindings/phy/transmit-amplitude.yaml
> > individually.
> >
> > This is the easiest and most intuitive way to describe that. The above
> > is not the only electrical tuning that needs to be done, but rather the
> > only one currently standardized in a schema. TX equalization parameters
> > are TBD, but we need to not limit ourselves to just what currently exists.
> >
> > Luckily, we can overlap the modern binding format over the legacy one
> > and they can coexist without interfering. Old kernels use compatible =
> > "fsl,lynx-28g" and the top-level PHY provider, whereas new kernels probe
> > on e.g. compatible = "fsl,lx2160a-serdes1" and use the per-lane PHY
> > providers.
> >
> > Overlaying modern on top of legacy is only necessary for SerDes 1 and 2.
> > LX2160A SerDes #3 (a non-networking SerDes) is not yet present in any
> > device trees in circulation, and will only have the device-specific
> > compatible (even though it shares the Lynx 28G programming model,
> > specifying the "fsl,lynx-28g" compatible string for it provides no
> > benefit that I can see).
> >
> > Change the expected name of the top-level node to "serdes", and update
> > the example too.
> >
> > Cc: Rob Herring <robh@kernel.org>
> > Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> > Cc: Conor Dooley <conor+dt@kernel.org>
> > Cc: devicetree@vger.kernel.org
> > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> > ---
> > v2->v3:
> > - re-add "fsl,lynx-28g" as fallback compatible, and #phy-cells = <1> in
> > top-level "serdes" node
> > - drop useless description texts
> > - fix text formatting
> > - schema is more lax to allow overlaying old and new required properties
> > v1->v2:
> > - drop the usage of "fsl,lynx-28g" as a fallback compatible
> > - mark "fsl,lynx-28g" as deprecated
> > - implement Josua's request for per-lane OF nodes for the new compatible
> > strings
> >
> > .../devicetree/bindings/phy/fsl,lynx-28g.yaml | 159 +++++++++++++++++-
> > 1 file changed, 152 insertions(+), 7 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml b/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml
> > index ff9f9ca0f19c..e8b3a48b9515 100644
> > --- a/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml
> > +++ b/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml
> > @@ -9,21 +9,123 @@ title: Freescale Lynx 28G SerDes PHY
> > maintainers:
> > - Ioana Ciornei <ioana.ciornei@nxp.com>
> >
> > +description:
> > + The Lynx 28G is a multi-lane, multi-protocol SerDes (PCIe, SATA, Ethernet)
> > + present in multiple instances on NXP LX2160A and LX2162A SoCs. All instances
> > + share a common register map and programming model, however they differ in
> > + supported protocols per lane in a way that is not detectable by said
> > + programming model without prior knowledge. The distinction is made through
> > + the compatible string.
> > +
> > properties:
> > compatible:
> > - enum:
> > - - fsl,lynx-28g
> > + oneOf:
> > + - const: fsl,lynx-28g
> > + deprecated: true
> > + description:
> > + Legacy compatibility string for Lynx 28G SerDes. Any assumption
> > + regarding whether a certain lane supports a certain protocol may
> > + be incorrect. Deprecated except when used as a fallback. Use
> > + device-specific strings instead.
> > + - items:
> > + - const: fsl,lx2160a-serdes1
> > + - const: fsl,lynx-28g
> > + - items:
> > + - const: fsl,lx2160a-serdes2
> > + - const: fsl,lynx-28g
> > + - items:
> > + - const: fsl,lx2162a-serdes1
> > + - const: fsl,lynx-28g
> > + - items:
> > + - const: fsl,lx2162a-serdes2
> > + - const: fsl,lynx-28g
> > + - const: fsl,lx2160a-serdes3
> >
> > reg:
> > maxItems: 1
> >
> > - "#phy-cells":
> > - const: 1
> > + "#address-cells": true
> > +
> > + "#size-cells": true
> > +
> > + "#phy-cells": true
> > +
> > +patternProperties:
> > + "^phy@[0-9a-f]+$":
> > + type: object
> > + description: Individual SerDes lane acting as PHY provider
> > +
> > + properties:
> > + reg:
> > + description: Lane index as seen in register map
> > + maxItems: 1
> > +
> > + "#phy-cells":
> > + const: 0
> > +
> > + required:
> > + - reg
> > + - "#phy-cells"
> > +
> > + additionalProperties: false
> >
> > required:
> > - compatible
> > - reg
> > - - "#phy-cells"
> > +
> > +allOf:
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: fsl,lynx-28g
> > + then:
> > + # Legacy case: parent is the PHY provider, cell encodes lane index
> > + properties:
> > + "#phy-cells":
> > + const: 1
> > + required:
> > + - "#phy-cells"
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - fsl,lx2160a-serdes1
> > + - fsl,lx2160a-serdes2
> > + - fsl,lx2160a-serdes3
> > + - fsl,lx2162a-serdes1
> > + - fsl,lx2162a-serdes2
> > + then:
> > + # Modern binding: lanes must have their own nodes
> > + properties:
> > + "#address-cells":
> > + const: 1
> > + "#size-cells":
> > + const: 0
> > + required:
> > + - "#address-cells"
> > + - "#size-cells"
> > +
> > + # LX2162A SerDes 1 has fewer lanes than the others
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: fsl,lx2162a-serdes1
> > + then:
> > + patternProperties:
> > + "^phy@[0-9a-f]+$":
> > + properties:
> > + reg:
> > + enum: [4, 5, 6, 7]
> > + else:
> > + patternProperties:
> > + "^phy@[0-9a-f]+$":
> > + properties:
> > + reg:
> > + enum: [0, 1, 2, 3, 4, 5, 6, 7]
> >
> > additionalProperties: false
> >
> > @@ -32,9 +134,52 @@ examples:
> > soc {
> > #address-cells = <2>;
> > #size-cells = <2>;
> > - serdes_1: phy@1ea0000 {
> > - compatible = "fsl,lynx-28g";
> > +
> > + serdes_1: serdes@1ea0000 {
> > + compatible = "fsl,lx2160a-serdes1", "fsl,lynx-28g";
> > reg = <0x0 0x1ea0000 0x0 0x1e30>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > #phy-cells = <1>;
> > +
> > + phy@0 {
> > + reg = <0>;
> > + #phy-cells = <0>;
> > + };
> > +
> > + phy@1 {
> > + reg = <1>;
> > + #phy-cells = <0>;
> > + };
> > +
> > + phy@2 {
> > + reg = <2>;
> > + #phy-cells = <0>;
> > + };
> > +
> > + phy@3 {
> > + reg = <3>;
> > + #phy-cells = <0>;
> > + };
> > +
> > + phy@4 {
> > + reg = <4>;
> > + #phy-cells = <0>;
> > + };
> > +
> > + phy@5 {
> > + reg = <5>;
> > + #phy-cells = <0>;
> > + };
> > +
> > + phy@6 {
> > + reg = <6>;
> > + #phy-cells = <0>;
> > + };
> > +
> > + phy@7 {
> > + reg = <7>;
> > + #phy-cells = <0>;
> > + };
> > };
> > };
> > --
> > 2.34.1
> >
>
> I should have realized sooner when Rob/Josua requested the changes for
> backwards schema compatibility in v2:
> https://lore.kernel.org/lkml/20250925080317.2ocgybitliwddhcf@skbuf/
> that despite our attempts to preserve compatibility with old kernels,
> we actually fail to do that. Actually I should have documented my
> earlier thought process better, where I already came to that conclusion,
> but which I had forgotten when told that this could work...
>
> The SerDes schema itself is technically backwards-compatible, but the
> problem is with consumers, which aren't. In old device trees, they have:
>
> phys = <&serdes_1 0>;
>
> and in new ones, they have:
>
> phys = <&serdes_1_lane_a>;
>
> Because the consumer has a single "phys" phandle to the PHY provider, it
> either has to point to one, or to the other. But on old kernels, we do
> not register PHY providers per lane, so "phys = <&serdes_1_lane_a>"
> results in a broken reference.
>
> There are 2 directions to go from here:
> 1. Have optional per-lane "phy" OF node children, which exist solely for
> tuning electrical parameters. We need to keep the top-level SerDes as
> the only PHY provider, with #phy-cells = <1> denoting the lane.
>
> 2. Accept that keeping "fsl,lynx-28g" and overlaid properties has
> absolutely no practical benefit, and drop them (effectively returning
> to Conor's suggestion, as implemented in v2)
>
> 3. Extend the schema and the driver support for it as a backportable bug
> fix, to allow registering PHY providers for lanes with OF nodes in
> stable kernels. This avoids regressing when the device trees are
> updated, assuming the stable kernel is also updated.
>
> It's not that I particularly like #2, but going with #1 would imply that
> lane OF nodes exist, but the "phys" phandles do not point to them.
>
> Combine that with the fact that anything we do with the 28G Lynx
> bindings will have to be replicated, for uniformity's sake, with the
> upcoming 10G Lynx SerDes binding (very similar hardware IP), and #1 is
> suddenly not looking so pretty at all. I.e. introducing the 10G Lynx
> bindings like the 28G Lynx ones would mean deviating from the widely
> established norm, and introducing them like the widely established norm
> would mean deviating from the 28G Lynx. I can easily see how someone
> might look at them one day and think "hmm, can't we make them more
> uniform?"
>
> OTOH, the fact that device tree updates require kernel updates (as
> implied by #2) is acceptably by everyone in this thread who expressed an
> opinion on this topic.
>
> As for option #3, while IMO it would be a justified "new feature as
> bug fix", it sounds a bit counterintuitive and I'm afraid I won't manage
> to convince all maintainers along the way that this is the way forward.
>
> I'll wait for the merge window to close before reposting anything, but
> I'd like an explicit ack from Rob and Josua in the meantime, whose
> change request I'd be effectively reverting, to make sure that this
> topic is closed.
If #2 is not going to upset anyone (that their device stopped working),
then that route is fine.
Rob
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v3 phy 12/17] dt-bindings: phy: lynx-28g: add compatible strings per SerDes and instantiation
2025-10-02 3:03 ` Rob Herring
@ 2025-10-02 10:08 ` Josua Mayer
2025-10-02 11:32 ` Vladimir Oltean
0 siblings, 1 reply; 26+ messages in thread
From: Josua Mayer @ 2025-10-02 10:08 UTC (permalink / raw)
To: Rob Herring, Vladimir Oltean
Cc: Ioana Ciornei, Vinod Koul, Kishon Vijay Abraham I,
linux-kernel@vger.kernel.org, Krzysztof Kozlowski, Conor Dooley,
devicetree@vger.kernel.org, linux-phy@lists.infradead.org
Am 02.10.25 um 05:03 schrieb Rob Herring:
> On Tue, Sep 30, 2025 at 05:07:35PM +0300, Vladimir Oltean wrote:
>> On Fri, Sep 26, 2025 at 09:05:00PM +0300, Vladimir Oltean wrote:
>>> Going by the generic "fsl,lynx-28g" compatible string and expecting all
>>> SerDes instantiations on all SoCs to use it was a mistake.
>>>
>>> They all share the same register map, sure, but the number of protocol
>>> converters and lanes which are instantiated differs in a way that isn't
>>> detectable by the programming interface.
>>>
>>> Using a separate compatible string per SerDes instantiation is
>>> sufficient for any device driver to distinguish these features and/or
>>> any instance-specific quirk. It also reflects how the SoC reference
>>> manual provides different tables with protocol combinations for each
>>> SerDes. NXP clearly documents these as not identical, and refers to them
>>> as such (SerDes 1, 2, etc).
>>>
>>> The other sufficient approach for Lynx 28G would be to list in the
>>> device tree all protocols supported by each lane. That would be
>>> insufficient for the very similar Lynx 10G SerDes however, for which
>>> there exists a higher degree of variability in the PCCR register values
>>> that need to be written per protocol. This attempt can be seen in this
>>> unmerged patch set for Lynx 10G:
>>> https://lore.kernel.org/linux-phy/20230413160607.4128315-3-sean.anderson@seco.com/
>>>
>>> but that approach is more drawn-out and more prone to errors, whereas
>>> this one is more succinct and obviously correct.
>>>
>>> One aspect which is different with the per-SoC compatible strings is
>>> that they have one PHY provider for each lane (and #phy-cells = <0> in
>>> lane sub-nodes), rather than "fsl,lynx-28g" which has a single PHY
>>> provider for all lanes (and #phy-cells = <1> in the top-level node).
>>>
>>> This is done to fulfill Josua Mayer's request:
>>> https://lore.kernel.org/lkml/02270f62-9334-400c-b7b9-7e6a44dbbfc9@solid-run.com/
>>> to have OF nodes for each lane, so that we can further apply schemas
>>> such as Documentation/devicetree/bindings/phy/transmit-amplitude.yaml
>>> individually.
>>>
>>> This is the easiest and most intuitive way to describe that. The above
>>> is not the only electrical tuning that needs to be done, but rather the
>>> only one currently standardized in a schema. TX equalization parameters
>>> are TBD, but we need to not limit ourselves to just what currently exists.
>>>
>>> Luckily, we can overlap the modern binding format over the legacy one
>>> and they can coexist without interfering. Old kernels use compatible =
>>> "fsl,lynx-28g" and the top-level PHY provider, whereas new kernels probe
>>> on e.g. compatible = "fsl,lx2160a-serdes1" and use the per-lane PHY
>>> providers.
>>>
>>> Overlaying modern on top of legacy is only necessary for SerDes 1 and 2.
>>> LX2160A SerDes #3 (a non-networking SerDes) is not yet present in any
>>> device trees in circulation, and will only have the device-specific
>>> compatible (even though it shares the Lynx 28G programming model,
>>> specifying the "fsl,lynx-28g" compatible string for it provides no
>>> benefit that I can see).
>>>
>>> Change the expected name of the top-level node to "serdes", and update
>>> the example too.
>>>
>>> Cc: Rob Herring <robh@kernel.org>
>>> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
>>> Cc: Conor Dooley <conor+dt@kernel.org>
>>> Cc: devicetree@vger.kernel.org
>>> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
>>> ---
>>> v2->v3:
>>> - re-add "fsl,lynx-28g" as fallback compatible, and #phy-cells = <1> in
>>> top-level "serdes" node
>>> - drop useless description texts
>>> - fix text formatting
>>> - schema is more lax to allow overlaying old and new required properties
>>> v1->v2:
>>> - drop the usage of "fsl,lynx-28g" as a fallback compatible
>>> - mark "fsl,lynx-28g" as deprecated
>>> - implement Josua's request for per-lane OF nodes for the new compatible
>>> strings
>>>
>>> .../devicetree/bindings/phy/fsl,lynx-28g.yaml | 159 +++++++++++++++++-
>>> 1 file changed, 152 insertions(+), 7 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml b/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml
>>> index ff9f9ca0f19c..e8b3a48b9515 100644
>>> --- a/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml
>>> +++ b/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml
>>> @@ -9,21 +9,123 @@ title: Freescale Lynx 28G SerDes PHY
>>> maintainers:
>>> - Ioana Ciornei <ioana.ciornei@nxp.com>
>>>
>>> +description:
>>> + The Lynx 28G is a multi-lane, multi-protocol SerDes (PCIe, SATA, Ethernet)
>>> + present in multiple instances on NXP LX2160A and LX2162A SoCs. All instances
>>> + share a common register map and programming model, however they differ in
>>> + supported protocols per lane in a way that is not detectable by said
>>> + programming model without prior knowledge. The distinction is made through
>>> + the compatible string.
>>> +
>>> properties:
>>> compatible:
>>> - enum:
>>> - - fsl,lynx-28g
>>> + oneOf:
>>> + - const: fsl,lynx-28g
>>> + deprecated: true
>>> + description:
>>> + Legacy compatibility string for Lynx 28G SerDes. Any assumption
>>> + regarding whether a certain lane supports a certain protocol may
>>> + be incorrect. Deprecated except when used as a fallback. Use
>>> + device-specific strings instead.
>>> + - items:
>>> + - const: fsl,lx2160a-serdes1
>>> + - const: fsl,lynx-28g
>>> + - items:
>>> + - const: fsl,lx2160a-serdes2
>>> + - const: fsl,lynx-28g
>>> + - items:
>>> + - const: fsl,lx2162a-serdes1
>>> + - const: fsl,lynx-28g
>>> + - items:
>>> + - const: fsl,lx2162a-serdes2
>>> + - const: fsl,lynx-28g
>>> + - const: fsl,lx2160a-serdes3
>>>
>>> reg:
>>> maxItems: 1
>>>
>>> - "#phy-cells":
>>> - const: 1
>>> + "#address-cells": true
>>> +
>>> + "#size-cells": true
>>> +
>>> + "#phy-cells": true
>>> +
>>> +patternProperties:
>>> + "^phy@[0-9a-f]+$":
>>> + type: object
>>> + description: Individual SerDes lane acting as PHY provider
>>> +
>>> + properties:
>>> + reg:
>>> + description: Lane index as seen in register map
>>> + maxItems: 1
>>> +
>>> + "#phy-cells":
>>> + const: 0
>>> +
>>> + required:
>>> + - reg
>>> + - "#phy-cells"
>>> +
>>> + additionalProperties: false
>>>
>>> required:
>>> - compatible
>>> - reg
>>> - - "#phy-cells"
>>> +
>>> +allOf:
>>> + - if:
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + const: fsl,lynx-28g
>>> + then:
>>> + # Legacy case: parent is the PHY provider, cell encodes lane index
>>> + properties:
>>> + "#phy-cells":
>>> + const: 1
>>> + required:
>>> + - "#phy-cells"
>>> +
>>> + - if:
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + enum:
>>> + - fsl,lx2160a-serdes1
>>> + - fsl,lx2160a-serdes2
>>> + - fsl,lx2160a-serdes3
>>> + - fsl,lx2162a-serdes1
>>> + - fsl,lx2162a-serdes2
>>> + then:
>>> + # Modern binding: lanes must have their own nodes
>>> + properties:
>>> + "#address-cells":
>>> + const: 1
>>> + "#size-cells":
>>> + const: 0
>>> + required:
>>> + - "#address-cells"
>>> + - "#size-cells"
>>> +
>>> + # LX2162A SerDes 1 has fewer lanes than the others
>>> + - if:
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + const: fsl,lx2162a-serdes1
>>> + then:
>>> + patternProperties:
>>> + "^phy@[0-9a-f]+$":
>>> + properties:
>>> + reg:
>>> + enum: [4, 5, 6, 7]
>>> + else:
>>> + patternProperties:
>>> + "^phy@[0-9a-f]+$":
>>> + properties:
>>> + reg:
>>> + enum: [0, 1, 2, 3, 4, 5, 6, 7]
>>>
>>> additionalProperties: false
>>>
>>> @@ -32,9 +134,52 @@ examples:
>>> soc {
>>> #address-cells = <2>;
>>> #size-cells = <2>;
>>> - serdes_1: phy@1ea0000 {
>>> - compatible = "fsl,lynx-28g";
>>> +
>>> + serdes_1: serdes@1ea0000 {
>>> + compatible = "fsl,lx2160a-serdes1", "fsl,lynx-28g";
>>> reg = <0x0 0x1ea0000 0x0 0x1e30>;
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> #phy-cells = <1>;
>>> +
>>> + phy@0 {
>>> + reg = <0>;
>>> + #phy-cells = <0>;
>>> + };
>>> +
>>> + phy@1 {
>>> + reg = <1>;
>>> + #phy-cells = <0>;
>>> + };
>>> +
>>> + phy@2 {
>>> + reg = <2>;
>>> + #phy-cells = <0>;
>>> + };
>>> +
>>> + phy@3 {
>>> + reg = <3>;
>>> + #phy-cells = <0>;
>>> + };
>>> +
>>> + phy@4 {
>>> + reg = <4>;
>>> + #phy-cells = <0>;
>>> + };
>>> +
>>> + phy@5 {
>>> + reg = <5>;
>>> + #phy-cells = <0>;
>>> + };
>>> +
>>> + phy@6 {
>>> + reg = <6>;
>>> + #phy-cells = <0>;
>>> + };
>>> +
>>> + phy@7 {
>>> + reg = <7>;
>>> + #phy-cells = <0>;
>>> + };
>>> };
>>> };
>>> --
>>> 2.34.1
>>>
>> I should have realized sooner when Rob/Josua requested the changes for
>> backwards schema compatibility in v2:
>> https://lore.kernel.org/lkml/20250925080317.2ocgybitliwddhcf@skbuf/
>> that despite our attempts to preserve compatibility with old kernels,
>> we actually fail to do that. Actually I should have documented my
>> earlier thought process better, where I already came to that conclusion,
>> but which I had forgotten when told that this could work...
>>
>> The SerDes schema itself is technically backwards-compatible, but the
>> problem is with consumers, which aren't. In old device trees, they have:
>>
>> phys = <&serdes_1 0>;
>>
>> and in new ones, they have:
>>
>> phys = <&serdes_1_lane_a>;
>>
>> Because the consumer has a single "phys" phandle to the PHY provider, it
>> either has to point to one, or to the other. But on old kernels, we do
>> not register PHY providers per lane, so "phys = <&serdes_1_lane_a>"
>> results in a broken reference.
I would not expect being able to use a new schema in an older kernel.
Maybe DT maintainers can confirm whether anyone expects that.
>>
>> There are 2 directions to go from here:
>> 1. Have optional per-lane "phy" OF node children, which exist solely for
>> tuning electrical parameters. We need to keep the top-level SerDes as
>> the only PHY provider, with #phy-cells = <1> denoting the lane.
>>
>> 2. Accept that keeping "fsl,lynx-28g" and overlaid properties has
>> absolutely no practical benefit, and drop them (effectively returning
>> to Conor's suggestion, as implemented in v2)
I don't quite understand how keeping or dropping fsl,lynx-28g compatible
impacts the ability to set phandles to the base and child nodes.
An updated driver can be made to handle both references,
and an older driver will only handle the one to the base node.
>>
>> 3. Extend the schema and the driver support for it as a backportable bug
>> fix, to allow registering PHY providers for lanes with OF nodes in
>> stable kernels. This avoids regressing when the device trees are
>> updated, assuming the stable kernel is also updated.
I think whatever will be done with phy sub-nodes on the serdes block node
should not count as a fix to be backported in stable.
Any attempt to backport reference to &serdes_1_lane_a will produce a
compile-time error.
>>
>> It's not that I particularly like #2, but going with #1 would imply that
>> lane OF nodes exist, but the "phys" phandles do not point to them.
>>
>> Combine that with the fact that anything we do with the 28G Lynx
>> bindings will have to be replicated, for uniformity's sake, with the
>> upcoming 10G Lynx SerDes binding (very similar hardware IP), and #1 is
>> suddenly not looking so pretty at all. I.e. introducing the 10G Lynx
>> bindings like the 28G Lynx ones would mean deviating from the widely
>> established norm, and introducing them like the widely established norm
>> would mean deviating from the 28G Lynx. I can easily see how someone
>> might look at them one day and think "hmm, can't we make them more
>> uniform?"
>>
>> OTOH, the fact that device tree updates require kernel updates (as
>> implied by #2) is acceptably by everyone in this thread who expressed an
>> opinion on this topic.
>>
>> As for option #3, while IMO it would be a justified "new feature as
>> bug fix", it sounds a bit counterintuitive and I'm afraid I won't manage
>> to convince all maintainers along the way that this is the way forward.
>>
>> I'll wait for the merge window to close before reposting anything, but
>> I'd like an explicit ack from Rob and Josua in the meantime, whose
>> change request I'd be effectively reverting, to make sure that this
>> topic is closed.
> If #2 is not going to upset anyone (that their device stopped working),
> then that route is fine.
>
> Rob
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v3 phy 13/17] phy: lynx-28g: probe on per-SoC and per-instance compatible strings
2025-09-26 18:05 ` [PATCH v3 phy 13/17] phy: lynx-28g: probe on per-SoC and per-instance compatible strings Vladimir Oltean
@ 2025-10-02 10:40 ` Josua Mayer
2025-10-02 10:50 ` Josua Mayer
2025-10-02 11:14 ` Vladimir Oltean
0 siblings, 2 replies; 26+ messages in thread
From: Josua Mayer @ 2025-10-02 10:40 UTC (permalink / raw)
To: Vladimir Oltean, linux-phy@lists.infradead.org
Cc: Ioana Ciornei, Vinod Koul, Kishon Vijay Abraham I,
linux-kernel@vger.kernel.org, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree@vger.kernel.org
Am 26.09.25 um 20:05 schrieb Vladimir Oltean:
> Add driver support for probing on the new, per-instance and per-SoC
> bindings, which provide the following benefits:
> - they allow rejecting unsupported protocols per lane (10GbE on SerDes 2
> lanes 0-5)
> - individual lanes have their own OF nodes as PHY providers, which
> allows board device tree authors to tune electrical parameters such as
> TX amplitude, equalization etc.
>
> Probing on "fsl,lynx-28g" is still supported, but the feature set is
> frozen in time to just 1GbE and 10GbE (essentially the feature set as of
> this change). However, we encourage the user at probe time to update the
> device tree.
>
> Refactor the per-lane logic from lynx_28g_probe() into
> lynx_28g_lane_probe(), and call it from two distinct paths depending on
> whether the modern or the legacy compatible string is used, with an OF
> node for the lane or without.
>
> Notable implication of the above: when lanes have disabled OF nodes, we
> skip creating PHYs for them, and must also skip the CDR lock workaround.
>
> lynx_28g_supports_lane_mode() was a SerDes-global function and now
> becomes per lane, to reflect the specific capabilities each instance may
> have.
>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
> Cc: Conor Dooley <conor+dt@kernel.org>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
> v2->v3:
> - reword commit message
> - add some comments regarding the "fsl,lynx-28g" fallback mechanism
> - skip CDR lock workaround for lanes with no PHY (disabled in the device
> tree in the new binding)
> v1->v2:
> - remove priv->info->get_pccr() and priv->info->get_pcvt_offset().
> These were always called directly as lynx_28g_get_pccr() and
> lynx_28g_get_pcvt_offset().
> - Add forgotten priv->info->lane_supports_mode() test to
> lynx_28g_supports_lane_mode().
> - Rename the "fsl,lynx-28g" drvdata as lynx_info_compat rather than
> lynx_info_lx2160a_serdes1, to reflect its treatment as less featured.
> - Implement a separate lane probing path for the #phy-cells = <0> case.
>
> drivers/phy/freescale/phy-fsl-lynx-28g.c | 202 ++++++++++++++++++++---
> 1 file changed, 179 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
> index 453e76e0a6b7..1ddca8b4de17 100644
> --- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
> +++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
> @@ -433,9 +433,15 @@ struct lynx_28g_lane {
> enum lynx_lane_mode mode;
> };
>
> +struct lynx_info {
> + bool (*lane_supports_mode)(int lane, enum lynx_lane_mode mode);
> + int first_lane;
> +};
> +
> struct lynx_28g_priv {
> void __iomem *base;
> struct device *dev;
> + const struct lynx_info *info;
> /* Serialize concurrent access to registers shared between lanes,
> * like PCCn
> */
> @@ -500,11 +506,18 @@ static enum lynx_lane_mode phy_interface_to_lane_mode(phy_interface_t intf)
> }
> }
>
> -static bool lynx_28g_supports_lane_mode(struct lynx_28g_priv *priv,
> +/* A lane mode is supported if we have a PLL that can provide its required
> + * clock net, and if there is a protocol converter for that mode on that lane.
> + */
> +static bool lynx_28g_supports_lane_mode(struct lynx_28g_lane *lane,
> enum lynx_lane_mode mode)
> {
> + struct lynx_28g_priv *priv = lane->priv;
> int i;
>
> + if (!priv->info->lane_supports_mode(lane->id, mode))
> + return false;
> +
> for (i = 0; i < LYNX_28G_NUM_PLL; i++) {
> if (PLLnRSTCTL_DIS(priv->pll[i].rstctl))
> continue;
> @@ -687,6 +700,86 @@ static int lynx_28g_get_pcvt_offset(int lane, enum lynx_lane_mode lane_mode)
> }
> }
>
> +static bool lx2160a_serdes1_lane_supports_mode(int lane,
> + enum lynx_lane_mode mode)
> +{
> + return true;
> +}
> +
> +static bool lx2160a_serdes2_lane_supports_mode(int lane,
> + enum lynx_lane_mode mode)
> +{
> + switch (mode) {
> + case LANE_MODE_1000BASEX_SGMII:
> + return true;
> + case LANE_MODE_USXGMII:
> + case LANE_MODE_10GBASER:
> + return lane == 6 || lane == 7;
> + default:
> + return false;
> + }
> +}
> +
> +static bool lx2160a_serdes3_lane_supports_mode(int lane,
> + enum lynx_lane_mode mode)
> +{
> + /*
> + * Non-networking SerDes, and this driver supports only
> + * networking protocols
> + */
> + return false;
> +}
> +
> +static bool lx2162a_serdes1_lane_supports_mode(int lane,
> + enum lynx_lane_mode mode)
> +{
> + return true;
> +}
> +
> +static bool lx2162a_serdes2_lane_supports_mode(int lane,
> + enum lynx_lane_mode mode)
> +{
> + return lx2160a_serdes2_lane_supports_mode(lane, mode);
> +}
> +
> +static bool lynx_28g_compat_lane_supports_mode(int lane,
> + enum lynx_lane_mode mode)
> +{
> + switch (mode) {
> + case LANE_MODE_1000BASEX_SGMII:
> + case LANE_MODE_USXGMII:
> + case LANE_MODE_10GBASER:
> + return true;
> + default:
> + return false;
> + }
> +}
> +
> +static const struct lynx_info lynx_info_compat = {
> + .lane_supports_mode = lynx_28g_compat_lane_supports_mode,
> +};
> +
> +static const struct lynx_info lynx_info_lx2160a_serdes1 = {
> + .lane_supports_mode = lx2160a_serdes1_lane_supports_mode,
> +};
> +
> +static const struct lynx_info lynx_info_lx2160a_serdes2 = {
> + .lane_supports_mode = lx2160a_serdes2_lane_supports_mode,
> +};
> +
> +static const struct lynx_info lynx_info_lx2160a_serdes3 = {
> + .lane_supports_mode = lx2160a_serdes3_lane_supports_mode,
> +};
> +
> +static const struct lynx_info lynx_info_lx2162a_serdes1 = {
> + .lane_supports_mode = lx2162a_serdes1_lane_supports_mode,
> + .first_lane = 4,
> +};
> +
> +static const struct lynx_info lynx_info_lx2162a_serdes2 = {
> + .lane_supports_mode = lx2162a_serdes2_lane_supports_mode,
> +};
> +
> static int lynx_pccr_read(struct lynx_28g_lane *lane, enum lynx_lane_mode mode,
> u32 *val)
> {
> @@ -939,7 +1032,6 @@ static int lynx_28g_lane_enable_pcvt(struct lynx_28g_lane *lane,
> static int lynx_28g_set_mode(struct phy *phy, enum phy_mode mode, int submode)
> {
> struct lynx_28g_lane *lane = phy_get_drvdata(phy);
> - struct lynx_28g_priv *priv = lane->priv;
> int powered_up = lane->powered_up;
> enum lynx_lane_mode lane_mode;
> int err = 0;
> @@ -951,7 +1043,7 @@ static int lynx_28g_set_mode(struct phy *phy, enum phy_mode mode, int submode)
> return -EOPNOTSUPP;
>
> lane_mode = phy_interface_to_lane_mode(submode);
> - if (!lynx_28g_supports_lane_mode(priv, lane_mode))
> + if (!lynx_28g_supports_lane_mode(lane, lane_mode))
> return -EOPNOTSUPP;
>
> if (lane_mode == lane->mode)
> @@ -984,14 +1076,13 @@ static int lynx_28g_validate(struct phy *phy, enum phy_mode mode, int submode,
> union phy_configure_opts *opts __always_unused)
> {
> struct lynx_28g_lane *lane = phy_get_drvdata(phy);
> - struct lynx_28g_priv *priv = lane->priv;
> enum lynx_lane_mode lane_mode;
>
> if (mode != PHY_MODE_ETHERNET)
> return -EOPNOTSUPP;
>
> lane_mode = phy_interface_to_lane_mode(submode);
> - if (!lynx_28g_supports_lane_mode(priv, lane_mode))
> + if (!lynx_28g_supports_lane_mode(lane, lane_mode))
> return -EOPNOTSUPP;
>
> return 0;
> @@ -1067,8 +1158,10 @@ static void lynx_28g_cdr_lock_check(struct work_struct *work)
> u32 rrstctl;
> int i;
>
> - for (i = 0; i < LYNX_28G_NUM_LANE; i++) {
> + for (i = priv->info->first_lane; i < LYNX_28G_NUM_LANE; i++) {
> lane = &priv->lane[i];
> + if (!lane->phy)
> + continue;
>
> mutex_lock(&lane->phy->mutex);
>
> @@ -1120,24 +1213,48 @@ static struct phy *lynx_28g_xlate(struct device *dev,
> struct lynx_28g_priv *priv = dev_get_drvdata(dev);
> int idx = args->args[0];
>
> - if (WARN_ON(idx >= LYNX_28G_NUM_LANE))
> + if (WARN_ON(idx >= LYNX_28G_NUM_LANE ||
> + idx < priv->info->first_lane))
> return ERR_PTR(-EINVAL);
>
> return priv->lane[idx].phy;
> }
>
> +static int lynx_28g_probe_lane(struct lynx_28g_priv *priv, int id,
> + struct device_node *dn)
> +{
> + struct lynx_28g_lane *lane = &priv->lane[id];
> + struct phy *phy;
> +
> + memset(lane, 0, sizeof(*lane));
> +
> + phy = devm_phy_create(priv->dev, dn, &lynx_28g_ops);
> + if (IS_ERR(phy))
> + return PTR_ERR(phy);
> +
> + lane->priv = priv;
> + lane->phy = phy;
> + lane->id = id;
> + phy_set_drvdata(phy, lane);
> + lynx_28g_lane_read_configuration(lane);
> +
> + return 0;
> +}
> +
> static int lynx_28g_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> + bool lane_phy_providers = true;
> struct phy_provider *provider;
> struct lynx_28g_priv *priv;
> - int i;
> + int err;
>
> priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> if (!priv)
> return -ENOMEM;
>
> priv->dev = dev;
> + priv->info = of_device_get_match_data(dev);
> dev_set_drvdata(dev, priv);
> spin_lock_init(&priv->pcc_lock);
> INIT_DELAYED_WORK(&priv->cdr_check, lynx_28g_cdr_lock_check);
> @@ -1146,26 +1263,60 @@ static int lynx_28g_probe(struct platform_device *pdev)
> if (IS_ERR(priv->base))
> return PTR_ERR(priv->base);
>
> - lynx_28g_pll_read_configuration(priv);
> + if (priv->info == &lynx_info_compat) {
> + /*
> + * If we get here it means we probed on a device tree where
> + * "fsl,lynx-28g" wasn't the fallback, but the sole compatible
> + * string.
> + */
> + dev_warn(dev, "Please update device tree to use per-device compatible strings\n");
> + lane_phy_providers = false;
> + }
>
> - for (i = 0; i < LYNX_28G_NUM_LANE; i++) {
> - struct lynx_28g_lane *lane = &priv->lane[i];
> - struct phy *phy;
> + lynx_28g_pll_read_configuration(priv);
>
> - memset(lane, 0, sizeof(*lane));
> + if (lane_phy_providers) {
> + struct device_node *dn = dev_of_node(dev), *child;
> +
> + for_each_available_child_of_node(dn, child) {
> + u32 reg;
> +
> + /* PHY subnode name must be 'phy'. */
> + if (!(of_node_name_eq(child, "phy")))
> + continue;
> +
> + if (of_property_read_u32(child, "reg", ®)) {
> + dev_err(dev, "No \"reg\" property for %pOF\n", child);
> + of_node_put(child);
> + return -EINVAL;
> + }
> +
> + if (reg < priv->info->first_lane || reg >= LYNX_28G_NUM_LANE) {
> + dev_err(dev, "\"reg\" property out of range for %pOF\n", child);
> + of_node_put(child);
> + return -EINVAL;
> + }
> +
> + err = lynx_28g_probe_lane(priv, reg, child);
> + if (err) {
> + of_node_put(child);
> + return err;
> + }
> + }
>
> - phy = devm_phy_create(dev, NULL, &lynx_28g_ops);
> - if (IS_ERR(phy))
> - return PTR_ERR(phy);
> + provider = devm_of_phy_provider_register(&pdev->dev,
> + of_phy_simple_xlate);
Is this really necessary? I believe phy_provider is not needed to resolve phandle
to a single phy, and is used only when one driver provides multiple phys.
> + } else {
> + for (int i = priv->info->first_lane; i < LYNX_28G_NUM_LANE; i++) {
> + err = lynx_28g_probe_lane(priv, i, NULL);
> + if (err)
> + return err;
> + }
>
> - lane->priv = priv;
> - lane->phy = phy;
> - lane->id = i;
> - phy_set_drvdata(phy, lane);
> - lynx_28g_lane_read_configuration(lane);
> + provider = devm_of_phy_provider_register(&pdev->dev,
> + lynx_28g_xlate);
> }
>
> - provider = devm_of_phy_provider_register(dev, lynx_28g_xlate);
> if (IS_ERR(provider))
> return PTR_ERR(provider);
Keep this to have compatibility with phandles to the parent.
>
> @@ -1184,7 +1335,12 @@ static void lynx_28g_remove(struct platform_device *pdev)
> }
>
> static const struct of_device_id lynx_28g_of_match_table[] = {
> - { .compatible = "fsl,lynx-28g" },
> + { .compatible = "fsl,lx2160a-serdes1", .data = &lynx_info_lx2160a_serdes1 },
> + { .compatible = "fsl,lx2160a-serdes2", .data = &lynx_info_lx2160a_serdes2 },
> + { .compatible = "fsl,lx2160a-serdes3", .data = &lynx_info_lx2160a_serdes3 },
> + { .compatible = "fsl,lx2162a-serdes1", .data = &lynx_info_lx2162a_serdes1 },
> + { .compatible = "fsl,lx2162a-serdes2", .data = &lynx_info_lx2162a_serdes2 },
> + { .compatible = "fsl,lynx-28g", .data = &lynx_info_compat }, /* fallback, keep last */
> { },
> };
> MODULE_DEVICE_TABLE(of, lynx_28g_of_match_table);
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v3 phy 13/17] phy: lynx-28g: probe on per-SoC and per-instance compatible strings
2025-10-02 10:40 ` Josua Mayer
@ 2025-10-02 10:50 ` Josua Mayer
2025-10-02 11:10 ` Vladimir Oltean
2025-10-02 11:14 ` Vladimir Oltean
1 sibling, 1 reply; 26+ messages in thread
From: Josua Mayer @ 2025-10-02 10:50 UTC (permalink / raw)
To: Vladimir Oltean, linux-phy@lists.infradead.org
Cc: Ioana Ciornei, Vinod Koul, Kishon Vijay Abraham I,
linux-kernel@vger.kernel.org, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree@vger.kernel.org
Am 02.10.25 um 12:40 schrieb Josua Mayer:
> Am 26.09.25 um 20:05 schrieb Vladimir Oltean:
>
>> Add driver support for probing on the new, per-instance and per-SoC
>> bindings, which provide the following benefits:
>> - they allow rejecting unsupported protocols per lane (10GbE on SerDes 2
>> lanes 0-5)
>> - individual lanes have their own OF nodes as PHY providers, which
>> allows board device tree authors to tune electrical parameters such as
>> TX amplitude, equalization etc.
>>
>> Probing on "fsl,lynx-28g" is still supported, but the feature set is
>> frozen in time to just 1GbE and 10GbE (essentially the feature set as of
>> this change). However, we encourage the user at probe time to update the
>> device tree.
>>
>> Refactor the per-lane logic from lynx_28g_probe() into
>> lynx_28g_lane_probe(), and call it from two distinct paths depending on
>> whether the modern or the legacy compatible string is used, with an OF
>> node for the lane or without.
>>
>> Notable implication of the above: when lanes have disabled OF nodes, we
>> skip creating PHYs for them, and must also skip the CDR lock workaround.
>>
>> lynx_28g_supports_lane_mode() was a SerDes-global function and now
>> becomes per lane, to reflect the specific capabilities each instance may
>> have.
>>
>> Cc: Rob Herring <robh@kernel.org>
>> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
>> Cc: Conor Dooley <conor+dt@kernel.org>
>> Cc: devicetree@vger.kernel.org
>> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
>> ---
>> v2->v3:
>> - reword commit message
>> - add some comments regarding the "fsl,lynx-28g" fallback mechanism
>> - skip CDR lock workaround for lanes with no PHY (disabled in the device
>> tree in the new binding)
>> v1->v2:
>> - remove priv->info->get_pccr() and priv->info->get_pcvt_offset().
>> These were always called directly as lynx_28g_get_pccr() and
>> lynx_28g_get_pcvt_offset().
>> - Add forgotten priv->info->lane_supports_mode() test to
>> lynx_28g_supports_lane_mode().
>> - Rename the "fsl,lynx-28g" drvdata as lynx_info_compat rather than
>> lynx_info_lx2160a_serdes1, to reflect its treatment as less featured.
>> - Implement a separate lane probing path for the #phy-cells = <0> case.
>>
>> drivers/phy/freescale/phy-fsl-lynx-28g.c | 202 ++++++++++++++++++++---
>> 1 file changed, 179 insertions(+), 23 deletions(-)
>>
>> diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
>> index 453e76e0a6b7..1ddca8b4de17 100644
>> --- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
>> +++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
>> @@ -433,9 +433,15 @@ struct lynx_28g_lane {
>> enum lynx_lane_mode mode;
>> };
>>
>> +struct lynx_info {
>> + bool (*lane_supports_mode)(int lane, enum lynx_lane_mode mode);
>> + int first_lane;
>> +};
>> +
>> struct lynx_28g_priv {
>> void __iomem *base;
>> struct device *dev;
>> + const struct lynx_info *info;
>> /* Serialize concurrent access to registers shared between lanes,
>> * like PCCn
>> */
>> @@ -500,11 +506,18 @@ static enum lynx_lane_mode phy_interface_to_lane_mode(phy_interface_t intf)
>> }
>> }
>>
>> -static bool lynx_28g_supports_lane_mode(struct lynx_28g_priv *priv,
>> +/* A lane mode is supported if we have a PLL that can provide its required
>> + * clock net, and if there is a protocol converter for that mode on that lane.
>> + */
>> +static bool lynx_28g_supports_lane_mode(struct lynx_28g_lane *lane,
>> enum lynx_lane_mode mode)
>> {
>> + struct lynx_28g_priv *priv = lane->priv;
>> int i;
>>
>> + if (!priv->info->lane_supports_mode(lane->id, mode))
>> + return false;
>> +
>> for (i = 0; i < LYNX_28G_NUM_PLL; i++) {
>> if (PLLnRSTCTL_DIS(priv->pll[i].rstctl))
>> continue;
>> @@ -687,6 +700,86 @@ static int lynx_28g_get_pcvt_offset(int lane, enum lynx_lane_mode lane_mode)
>> }
>> }
>>
>> +static bool lx2160a_serdes1_lane_supports_mode(int lane,
>> + enum lynx_lane_mode mode)
>> +{
>> + return true;
>> +}
>> +
>> +static bool lx2160a_serdes2_lane_supports_mode(int lane,
>> + enum lynx_lane_mode mode)
>> +{
>> + switch (mode) {
>> + case LANE_MODE_1000BASEX_SGMII:
>> + return true;
>> + case LANE_MODE_USXGMII:
>> + case LANE_MODE_10GBASER:
>> + return lane == 6 || lane == 7;
>> + default:
>> + return false;
>> + }
>> +}
>> +
>> +static bool lx2160a_serdes3_lane_supports_mode(int lane,
>> + enum lynx_lane_mode mode)
>> +{
>> + /*
>> + * Non-networking SerDes, and this driver supports only
>> + * networking protocols
>> + */
>> + return false;
>> +}
>> +
>> +static bool lx2162a_serdes1_lane_supports_mode(int lane,
>> + enum lynx_lane_mode mode)
>> +{
>> + return true;
>> +}
>> +
>> +static bool lx2162a_serdes2_lane_supports_mode(int lane,
>> + enum lynx_lane_mode mode)
>> +{
>> + return lx2160a_serdes2_lane_supports_mode(lane, mode);
>> +}
>> +
>> +static bool lynx_28g_compat_lane_supports_mode(int lane,
>> + enum lynx_lane_mode mode)
>> +{
>> + switch (mode) {
>> + case LANE_MODE_1000BASEX_SGMII:
>> + case LANE_MODE_USXGMII:
>> + case LANE_MODE_10GBASER:
>> + return true;
>> + default:
>> + return false;
>> + }
>> +}
>> +
>> +static const struct lynx_info lynx_info_compat = {
>> + .lane_supports_mode = lynx_28g_compat_lane_supports_mode,
>> +};
>> +
>> +static const struct lynx_info lynx_info_lx2160a_serdes1 = {
>> + .lane_supports_mode = lx2160a_serdes1_lane_supports_mode,
>> +};
>> +
>> +static const struct lynx_info lynx_info_lx2160a_serdes2 = {
>> + .lane_supports_mode = lx2160a_serdes2_lane_supports_mode,
>> +};
>> +
>> +static const struct lynx_info lynx_info_lx2160a_serdes3 = {
>> + .lane_supports_mode = lx2160a_serdes3_lane_supports_mode,
>> +};
>> +
>> +static const struct lynx_info lynx_info_lx2162a_serdes1 = {
>> + .lane_supports_mode = lx2162a_serdes1_lane_supports_mode,
>> + .first_lane = 4,
>> +};
>> +
>> +static const struct lynx_info lynx_info_lx2162a_serdes2 = {
>> + .lane_supports_mode = lx2162a_serdes2_lane_supports_mode,
>> +};
>> +
>> static int lynx_pccr_read(struct lynx_28g_lane *lane, enum lynx_lane_mode mode,
>> u32 *val)
>> {
>> @@ -939,7 +1032,6 @@ static int lynx_28g_lane_enable_pcvt(struct lynx_28g_lane *lane,
>> static int lynx_28g_set_mode(struct phy *phy, enum phy_mode mode, int submode)
>> {
>> struct lynx_28g_lane *lane = phy_get_drvdata(phy);
>> - struct lynx_28g_priv *priv = lane->priv;
>> int powered_up = lane->powered_up;
>> enum lynx_lane_mode lane_mode;
>> int err = 0;
>> @@ -951,7 +1043,7 @@ static int lynx_28g_set_mode(struct phy *phy, enum phy_mode mode, int submode)
>> return -EOPNOTSUPP;
>>
>> lane_mode = phy_interface_to_lane_mode(submode);
>> - if (!lynx_28g_supports_lane_mode(priv, lane_mode))
>> + if (!lynx_28g_supports_lane_mode(lane, lane_mode))
>> return -EOPNOTSUPP;
>>
>> if (lane_mode == lane->mode)
>> @@ -984,14 +1076,13 @@ static int lynx_28g_validate(struct phy *phy, enum phy_mode mode, int submode,
>> union phy_configure_opts *opts __always_unused)
>> {
>> struct lynx_28g_lane *lane = phy_get_drvdata(phy);
>> - struct lynx_28g_priv *priv = lane->priv;
>> enum lynx_lane_mode lane_mode;
>>
>> if (mode != PHY_MODE_ETHERNET)
>> return -EOPNOTSUPP;
>>
>> lane_mode = phy_interface_to_lane_mode(submode);
>> - if (!lynx_28g_supports_lane_mode(priv, lane_mode))
>> + if (!lynx_28g_supports_lane_mode(lane, lane_mode))
>> return -EOPNOTSUPP;
>>
>> return 0;
>> @@ -1067,8 +1158,10 @@ static void lynx_28g_cdr_lock_check(struct work_struct *work)
>> u32 rrstctl;
>> int i;
>>
>> - for (i = 0; i < LYNX_28G_NUM_LANE; i++) {
>> + for (i = priv->info->first_lane; i < LYNX_28G_NUM_LANE; i++) {
>> lane = &priv->lane[i];
>> + if (!lane->phy)
>> + continue;
>>
>> mutex_lock(&lane->phy->mutex);
>>
>> @@ -1120,24 +1213,48 @@ static struct phy *lynx_28g_xlate(struct device *dev,
>> struct lynx_28g_priv *priv = dev_get_drvdata(dev);
>> int idx = args->args[0];
>>
>> - if (WARN_ON(idx >= LYNX_28G_NUM_LANE))
>> + if (WARN_ON(idx >= LYNX_28G_NUM_LANE ||
>> + idx < priv->info->first_lane))
>> return ERR_PTR(-EINVAL);
>>
>> return priv->lane[idx].phy;
>> }
FYI as an example please see below how I handled this previously.
The xlate function below can translate both phandles with 0 and 1 arguments:
static struct phy *lynx_28g_xlate(struct device *dev,
struct of_phandle_args *args)
{
struct lynx_28g_priv *priv;
struct phy *phy;
int idx;
if (args->args_count == 0) {
/* direct look-up */
phy = of_phy_simple_xlate(dev, args);
} else if (args->args_count == 1) {
/* look-up from parent by index */
idx = args->args[0];
if (WARN_ON(idx >= LYNX_28G_NUM_LANE))
return ERR_PTR(-EINVAL);
priv = dev_get_drvdata(dev);
phy = priv->lane[idx].phy;
if (!phy)
phy = ERR_PTR(-ENODEV);
} else {
phy = ERR_PTR(-EINVAL);
}
return phy;
}
While in probe only one phy_provider is registered.
>>
>> +static int lynx_28g_probe_lane(struct lynx_28g_priv *priv, int id,
>> + struct device_node *dn)
>> +{
>> + struct lynx_28g_lane *lane = &priv->lane[id];
>> + struct phy *phy;
>> +
>> + memset(lane, 0, sizeof(*lane));
>> +
>> + phy = devm_phy_create(priv->dev, dn, &lynx_28g_ops);
>> + if (IS_ERR(phy))
>> + return PTR_ERR(phy);
>> +
>> + lane->priv = priv;
>> + lane->phy = phy;
>> + lane->id = id;
>> + phy_set_drvdata(phy, lane);
>> + lynx_28g_lane_read_configuration(lane);
>> +
>> + return 0;
>> +}
>> +
>> static int lynx_28g_probe(struct platform_device *pdev)
>> {
>> struct device *dev = &pdev->dev;
>> + bool lane_phy_providers = true;
>> struct phy_provider *provider;
>> struct lynx_28g_priv *priv;
>> - int i;
>> + int err;
>>
>> priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
>> if (!priv)
>> return -ENOMEM;
>>
>> priv->dev = dev;
>> + priv->info = of_device_get_match_data(dev);
>> dev_set_drvdata(dev, priv);
>> spin_lock_init(&priv->pcc_lock);
>> INIT_DELAYED_WORK(&priv->cdr_check, lynx_28g_cdr_lock_check);
>> @@ -1146,26 +1263,60 @@ static int lynx_28g_probe(struct platform_device *pdev)
>> if (IS_ERR(priv->base))
>> return PTR_ERR(priv->base);
>>
>> - lynx_28g_pll_read_configuration(priv);
>> + if (priv->info == &lynx_info_compat) {
>> + /*
>> + * If we get here it means we probed on a device tree where
>> + * "fsl,lynx-28g" wasn't the fallback, but the sole compatible
>> + * string.
>> + */
>> + dev_warn(dev, "Please update device tree to use per-device compatible strings\n");
>> + lane_phy_providers = false;
>> + }
>>
>> - for (i = 0; i < LYNX_28G_NUM_LANE; i++) {
>> - struct lynx_28g_lane *lane = &priv->lane[i];
>> - struct phy *phy;
>> + lynx_28g_pll_read_configuration(priv);
>>
>> - memset(lane, 0, sizeof(*lane));
>> + if (lane_phy_providers) {
>> + struct device_node *dn = dev_of_node(dev), *child;
>> +
>> + for_each_available_child_of_node(dn, child) {
>> + u32 reg;
>> +
>> + /* PHY subnode name must be 'phy'. */
>> + if (!(of_node_name_eq(child, "phy")))
>> + continue;
>> +
>> + if (of_property_read_u32(child, "reg", ®)) {
>> + dev_err(dev, "No \"reg\" property for %pOF\n", child);
>> + of_node_put(child);
>> + return -EINVAL;
>> + }
>> +
>> + if (reg < priv->info->first_lane || reg >= LYNX_28G_NUM_LANE) {
>> + dev_err(dev, "\"reg\" property out of range for %pOF\n", child);
>> + of_node_put(child);
>> + return -EINVAL;
>> + }
>> +
>> + err = lynx_28g_probe_lane(priv, reg, child);
>> + if (err) {
>> + of_node_put(child);
>> + return err;
>> + }
>> + }
>>
>> - phy = devm_phy_create(dev, NULL, &lynx_28g_ops);
>> - if (IS_ERR(phy))
>> - return PTR_ERR(phy);
>> + provider = devm_of_phy_provider_register(&pdev->dev,
>> + of_phy_simple_xlate);
> Is this really necessary? I believe phy_provider is not needed to resolve phandle
> to a single phy, and is used only when one driver provides multiple phys.
>> + } else {
>> + for (int i = priv->info->first_lane; i < LYNX_28G_NUM_LANE; i++) {
>> + err = lynx_28g_probe_lane(priv, i, NULL);
>> + if (err)
>> + return err;
>> + }
>>
>> - lane->priv = priv;
>> - lane->phy = phy;
>> - lane->id = i;
>> - phy_set_drvdata(phy, lane);
>> - lynx_28g_lane_read_configuration(lane);
>> + provider = devm_of_phy_provider_register(&pdev->dev,
>> + lynx_28g_xlate);
>> }
>>
>> - provider = devm_of_phy_provider_register(dev, lynx_28g_xlate);
>> if (IS_ERR(provider))
>> return PTR_ERR(provider);
> Keep this to have compatibility with phandles to the parent.
>>
>> @@ -1184,7 +1335,12 @@ static void lynx_28g_remove(struct platform_device *pdev)
>> }
>>
>> static const struct of_device_id lynx_28g_of_match_table[] = {
>> - { .compatible = "fsl,lynx-28g" },
>> + { .compatible = "fsl,lx2160a-serdes1", .data = &lynx_info_lx2160a_serdes1 },
>> + { .compatible = "fsl,lx2160a-serdes2", .data = &lynx_info_lx2160a_serdes2 },
>> + { .compatible = "fsl,lx2160a-serdes3", .data = &lynx_info_lx2160a_serdes3 },
>> + { .compatible = "fsl,lx2162a-serdes1", .data = &lynx_info_lx2162a_serdes1 },
>> + { .compatible = "fsl,lx2162a-serdes2", .data = &lynx_info_lx2162a_serdes2 },
>> + { .compatible = "fsl,lynx-28g", .data = &lynx_info_compat }, /* fallback, keep last */
>> { },
>> };
>> MODULE_DEVICE_TABLE(of, lynx_28g_of_match_table);
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v3 phy 13/17] phy: lynx-28g: probe on per-SoC and per-instance compatible strings
2025-10-02 10:50 ` Josua Mayer
@ 2025-10-02 11:10 ` Vladimir Oltean
0 siblings, 0 replies; 26+ messages in thread
From: Vladimir Oltean @ 2025-10-02 11:10 UTC (permalink / raw)
To: Josua Mayer
Cc: linux-phy@lists.infradead.org, Ioana Ciornei, Vinod Koul,
Kishon Vijay Abraham I, linux-kernel@vger.kernel.org, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree@vger.kernel.org
On Thu, Oct 02, 2025 at 10:50:46AM +0000, Josua Mayer wrote:
> FYI as an example please see below how I handled this previously.
> The xlate function below can translate both phandles with 0 and 1 arguments:
>
> static struct phy *lynx_28g_xlate(struct device *dev,
> struct of_phandle_args *args)
> {
> struct lynx_28g_priv *priv;
> struct phy *phy;
> int idx;
>
> if (args->args_count == 0) {
> /* direct look-up */
> phy = of_phy_simple_xlate(dev, args);
> } else if (args->args_count == 1) {
> /* look-up from parent by index */
> idx = args->args[0];
> if (WARN_ON(idx >= LYNX_28G_NUM_LANE))
> return ERR_PTR(-EINVAL);
>
> priv = dev_get_drvdata(dev);
> phy = priv->lane[idx].phy;
> if (!phy)
> phy = ERR_PTR(-ENODEV);
> } else {
> phy = ERR_PTR(-EINVAL);
> }
>
> return phy;
> }
>
> While in probe only one phy_provider is registered.
So what is the practical difference, in the #phy-cells = <0> case,
between registering a single phy provider and a custom xlate function
that redirects to of_phy_simple_xlate(), vs registering a phy provider
per lane and passing the of_phy_simple_xlate() function directly?
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v3 phy 13/17] phy: lynx-28g: probe on per-SoC and per-instance compatible strings
2025-10-02 10:40 ` Josua Mayer
2025-10-02 10:50 ` Josua Mayer
@ 2025-10-02 11:14 ` Vladimir Oltean
1 sibling, 0 replies; 26+ messages in thread
From: Vladimir Oltean @ 2025-10-02 11:14 UTC (permalink / raw)
To: Josua Mayer
Cc: linux-phy@lists.infradead.org, Ioana Ciornei, Vinod Koul,
Kishon Vijay Abraham I, linux-kernel@vger.kernel.org, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree@vger.kernel.org
On Thu, Oct 02, 2025 at 10:40:51AM +0000, Josua Mayer wrote:
> > - provider = devm_of_phy_provider_register(dev, lynx_28g_xlate);
> > if (IS_ERR(provider))
> > return PTR_ERR(provider);
> Keep this to have compatibility with phandles to the parent.
I am not removing it. Both the "if (lane_phy_providers)" and "else"
branches call devm_of_phy_provider_register(), with a different second
xlate argument (of_phy_simple_xlate vs lynx_28g_xlate).
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v3 phy 12/17] dt-bindings: phy: lynx-28g: add compatible strings per SerDes and instantiation
2025-10-02 10:08 ` Josua Mayer
@ 2025-10-02 11:32 ` Vladimir Oltean
0 siblings, 0 replies; 26+ messages in thread
From: Vladimir Oltean @ 2025-10-02 11:32 UTC (permalink / raw)
To: Josua Mayer
Cc: Rob Herring, Ioana Ciornei, Vinod Koul, Kishon Vijay Abraham I,
linux-kernel@vger.kernel.org, Krzysztof Kozlowski, Conor Dooley,
devicetree@vger.kernel.org, linux-phy@lists.infradead.org
On Thu, Oct 02, 2025 at 10:08:31AM +0000, Josua Mayer wrote:
> I would not expect being able to use a new schema in an older kernel.
> Maybe DT maintainers can confirm whether anyone expects that.
I can confirm from my own experience - some people expect that.
https://lore.kernel.org/lkml/87czlzjxmz.wl-maz@kernel.org/
> >> There are 2 directions to go from here:
> >> 1. Have optional per-lane "phy" OF node children, which exist solely for
> >> tuning electrical parameters. We need to keep the top-level SerDes as
> >> the only PHY provider, with #phy-cells = <1> denoting the lane.
> >>
> >> 2. Accept that keeping "fsl,lynx-28g" and overlaid properties has
> >> absolutely no practical benefit, and drop them (effectively returning
> >> to Conor's suggestion, as implemented in v2)
> I don't quite understand how keeping or dropping fsl,lynx-28g compatible
> impacts the ability to set phandles to the base and child nodes.
It doesn't "impact" it, but it doesn't help it either. It is an unnecessary
complication once you accept the fact that the consumer can have a single
phandle, either to the SerDes or to the lane, and that old kernels only
understand phandles to the SerDes, not to the lane.
> >> 3. Extend the schema and the driver support for it as a backportable bug
> >> fix, to allow registering PHY providers for lanes with OF nodes in
> >> stable kernels. This avoids regressing when the device trees are
> >> updated, assuming the stable kernel is also updated.
> I think whatever will be done with phy sub-nodes on the serdes block node
> should not count as a fix to be backported in stable.
> Any attempt to backport reference to &serdes_1_lane_a will produce a
> compile-time error.
Changing the phandle from <&serdes_1> to <&serdes_1_lane_a> is a
breaking change for unpatched kernels, so your options are:
- never do it. If you still want to add OF nodes per lane, this is
strange for the reason quoted below (summary: lane OF node exists, but
the phandle does not point to it).
- fix stable kernels so it's not a breaking change.
- live with the breakage.
> >>
> >> It's not that I particularly like #2, but going with #1 would imply that
> >> lane OF nodes exist, but the "phys" phandles do not point to them.
> >>
> >> Combine that with the fact that anything we do with the 28G Lynx
> >> bindings will have to be replicated, for uniformity's sake, with the
> >> upcoming 10G Lynx SerDes binding (very similar hardware IP), and #1 is
> >> suddenly not looking so pretty at all. I.e. introducing the 10G Lynx
> >> bindings like the 28G Lynx ones would mean deviating from the widely
> >> established norm, and introducing them like the widely established norm
> >> would mean deviating from the 28G Lynx. I can easily see how someone
> >> might look at them one day and think "hmm, can't we make them more
> >> uniform?"
> >>
> >> OTOH, the fact that device tree updates require kernel updates (as
> >> implied by #2) is acceptably by everyone in this thread who expressed an
> >> opinion on this topic.
> >>
> >> As for option #3, while IMO it would be a justified "new feature as
> >> bug fix", it sounds a bit counterintuitive and I'm afraid I won't manage
> >> to convince all maintainers along the way that this is the way forward.
> >>
> >> I'll wait for the merge window to close before reposting anything, but
> >> I'd like an explicit ack from Rob and Josua in the meantime, whose
> >> change request I'd be effectively reverting, to make sure that this
> >> topic is closed.
> > If #2 is not going to upset anyone (that their device stopped working),
> > then that route is fine.
> >
> > Rob
^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2025-10-02 11:32 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-09-26 18:04 [PATCH v3 phy 00/17] Lynx 28G improvements part 1 Vladimir Oltean
2025-09-26 18:04 ` [PATCH v3 phy 01/17] phy: lynx-28g: remove LYNX_28G_ prefix from register names Vladimir Oltean
2025-09-26 18:04 ` [PATCH v3 phy 02/17] phy: lynx-28g: don't concatenate lynx_28g_lane_rmw() argument "reg" with "val" and "mask" Vladimir Oltean
2025-09-26 18:04 ` [PATCH v3 phy 03/17] phy: lynx-28g: use FIELD_GET() and FIELD_PREP() Vladimir Oltean
2025-09-26 18:04 ` [PATCH v3 phy 04/17] phy: lynx-28g: convert iowrite32() calls with magic values to macros Vladimir Oltean
2025-09-26 18:04 ` [PATCH v3 phy 05/17] phy: lynx-28g: restructure protocol configuration register accesses Vladimir Oltean
2025-09-26 18:04 ` [PATCH v3 phy 06/17] phy: lynx-28g: make lynx_28g_set_lane_mode() more systematic Vladimir Oltean
2025-09-26 18:04 ` [PATCH v3 phy 07/17] phy: lynx-28g: refactor lane->interface to lane->mode Vladimir Oltean
2025-09-26 18:04 ` [PATCH v3 phy 08/17] phy: lynx-28g: distinguish between 10GBASE-R and USXGMII Vladimir Oltean
2025-09-26 18:04 ` [PATCH v3 phy 09/17] phy: lynx-28g: configure more equalization params for 1GbE and 10GbE Vladimir Oltean
2025-09-26 18:04 ` [PATCH v3 phy 10/17] phy: lynx-28g: use "dev" argument more in lynx_28g_probe() Vladimir Oltean
2025-09-26 18:04 ` [PATCH v3 phy 11/17] phy: lynx-28g: improve lynx_28g_probe() sequence Vladimir Oltean
2025-09-26 18:05 ` [PATCH v3 phy 12/17] dt-bindings: phy: lynx-28g: add compatible strings per SerDes and instantiation Vladimir Oltean
2025-09-30 14:07 ` Vladimir Oltean
2025-10-02 3:03 ` Rob Herring
2025-10-02 10:08 ` Josua Mayer
2025-10-02 11:32 ` Vladimir Oltean
2025-09-26 18:05 ` [PATCH v3 phy 13/17] phy: lynx-28g: probe on per-SoC and per-instance compatible strings Vladimir Oltean
2025-10-02 10:40 ` Josua Mayer
2025-10-02 10:50 ` Josua Mayer
2025-10-02 11:10 ` Vladimir Oltean
2025-10-02 11:14 ` Vladimir Oltean
2025-09-26 18:05 ` [PATCH v3 phy 14/17] phy: lynx-28g: add support for 25GBASER Vladimir Oltean
2025-09-26 18:05 ` [PATCH v3 phy 15/17] phy: lynx-28g: use timeouts when waiting for lane halt and reset Vladimir Oltean
2025-09-26 18:05 ` [PATCH v3 phy 16/17] phy: lynx-28g: truly power the lanes up or down Vladimir Oltean
2025-09-26 18:05 ` [PATCH v3 phy 17/17] phy: lynx-28g: implement phy_exit() operation Vladimir Oltean
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