From: Brian Sune <briansune@gmail.com>
To: Liam Girdwood <lgirdwood@gmail.com>,
Mark Brown <broonie@kernel.org>,
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Cc: linux-sound@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH] sound/soc/codecs/wm8978: add missing BCLK divider setup
Date: Fri, 3 Oct 2025 17:13:04 +0800 [thread overview]
Message-ID: <20251003091304.3686-1-briansune@gmail.com> (raw)
The original WM8978 codec driver did not set the BCLK (bit clock)
divider, which can cause audio clocks to be incorrect or unstable
depending on the sample rate and word length.
This patch adds proper calculation and configuration of the BCLK
divider based on the sample rate and word width, ensuring the
codec generates the correct bit clock for all supported rates.
Signed-off-by: Brian Sune <briansune@gmail.com>
---
sound/soc/codecs/wm8978.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/sound/soc/codecs/wm8978.c b/sound/soc/codecs/wm8978.c
index 8c45ba6fc4c3..2109c84f33df 100644
--- a/sound/soc/codecs/wm8978.c
+++ b/sound/soc/codecs/wm8978.c
@@ -717,6 +717,11 @@ static int wm8978_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
+ unsigned int bclk, bclkdiv = 0, min_diff = UINT_MAX;
+ unsigned int target_bclk = params_rate(params) * params_width(params) * 2;
+ /* WM8978 supports divisors */
+ static const int bclk_divs[] = {1, 2, 4, 8, 16, 32};
+
struct snd_soc_component *component = dai->component;
struct wm8978_priv *wm8978 = snd_soc_component_get_drvdata(component);
/* Word length mask = 0x60 */
@@ -820,6 +825,21 @@ static int wm8978_hw_params(struct snd_pcm_substream *substream,
/* MCLK divisor mask = 0xe0 */
snd_soc_component_update_bits(component, WM8978_CLOCKING, 0xe0, best << 5);
+ for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
+ bclk = wm8978->f_256fs / bclk_divs[i];
+ if (abs(bclk - target_bclk) < min_diff) {
+ min_diff = abs(bclk - target_bclk);
+ bclkdiv = i;
+ }
+ }
+
+ dev_dbg(component->dev, "%s: fs=%u width=%u -> target BCLK=%u, using div #%u\n",
+ __func__, params_rate(params), params_width(params), target_bclk,
+ bclk_divs[bclkdiv]);
+
+ /* BCLKDIV divisor mask = 0x1c */
+ snd_soc_component_update_bits(component, WM8978_CLOCKING, 0x1c, bclkdiv << 2);
+
snd_soc_component_write(component, WM8978_AUDIO_INTERFACE, iface_ctl);
snd_soc_component_write(component, WM8978_ADDITIONAL_CONTROL, add_ctl);
--
2.47.1.windows.1
next reply other threads:[~2025-10-03 9:13 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-03 9:13 Brian Sune [this message]
2025-10-07 10:30 ` [PATCH] sound/soc/codecs/wm8978: add missing BCLK divider setup Charles Keepax
2025-10-07 11:22 ` Sune Brian
2025-10-07 12:11 ` Charles Keepax
2025-10-07 12:18 ` Mark Brown
2025-10-07 12:26 ` Charles Keepax
2025-10-07 12:30 ` Mark Brown
2025-10-07 12:37 ` Sune Brian
2025-10-07 12:48 ` Sune Brian
2025-10-07 13:15 ` Charles Keepax
2025-10-07 13:39 ` Sune Brian
2025-10-07 13:48 ` Mark Brown
2025-10-07 13:54 ` Sune Brian
2025-10-07 11:33 ` [PATCH v2] ASoC: wm8978: " Brian Sune
2025-10-07 11:44 ` Mark Brown
2025-10-07 11:48 ` Sune Brian
2025-10-07 11:52 ` Mark Brown
2025-10-07 11:56 ` Sune Brian
2025-10-07 12:10 ` Mark Brown
2025-10-07 13:03 ` Sune Brian
2025-10-07 13:15 ` Mark Brown
2025-10-07 13:48 ` Sune Brian
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