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Fri, 10 Oct 2025 03:14:04 -0700 From: Kartik Rajput To: , , , , , , CC: Prathamesh Shete , Nathan Hartman , Kartik Rajput Subject: [PATCH v4 2/2] gpio: tegra186: Add support for Tegra410 Date: Fri, 10 Oct 2025 15:43:31 +0530 Message-ID: <20251010101331.712553-2-kkartik@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251010101331.712553-1-kkartik@nvidia.com> References: <20251010101331.712553-1-kkartik@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001709B:EE_|DS0PR12MB6414:EE_ X-MS-Office365-Filtering-Correlation-Id: 19083234-3037-4670-2a3b-08de07e5c78e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?PTijCWB7KzAitFq5e03KDXq3A/MgxVtE6fPc4rYQkU699cnJSOEr//H+x3rL?= =?us-ascii?Q?5em9IsGRFgI/49WGI6U9IUbSMzyAAgVNGqQShjn7BvgyYHdNRxi3rgyu4wyW?= =?us-ascii?Q?0wKgBVHXxxb1nl5xzvZJALZ93T/YFh6lEgtTThdQct8aI19CyvAVLLmaP4kC?= =?us-ascii?Q?9rSnYbTD68ogYPkbQOiHjDTh5CTx8gF+onOyZRgOnwB1Sshe99TbMEwmEKKt?= =?us-ascii?Q?id7lXE170iV7H9cOBBgt7AVSqbsxKj2RoZCvuvxS809ygtswJKUVbZQ6XfWQ?= =?us-ascii?Q?U3P29RyxvhOXDXlm6Og8F6gRh6sc+8QPORqnFoJXwhc4wrlFNClEuzRPamKe?= =?us-ascii?Q?5G8EYd6Ut+nwmZ1hbDiqEceTBab3NBULfjiNXwz2s+1U5+WURm2SInpe/xae?= =?us-ascii?Q?8rzzHCVAJuc7JvoMQt+zUEZ1qxXlPQtUpNqp3NS6BCwNE5ZExp2CSzQ14tnr?= =?us-ascii?Q?ypaq82xRjfAyQA3BZNVlCwqFp+oy0f1fBAZqUgwSUTqMGtsgFjXQP++CPNF4?= =?us-ascii?Q?JNhN09aXiCmQKefNtqdjPQt+1ymq/KsnxBRaqaFERNnI01QMk9Mbr3USIbli?= =?us-ascii?Q?z0w7N9McrUrSWJ82Jhoe5z4YDqn5jjr2S3DC3xlMQ+gazqqk3Z+C5+sTVtnr?= =?us-ascii?Q?fWy5KwynW144BUBOnV1CkqqsD9RS9A7svd6tyvPkT8JkElsapSPzGlvQhEew?= =?us-ascii?Q?zxJnJy9bl9rorr//RWjZPYdnJJ8/zRpSbbmxKUKYL+61+9kpN6GjOetA9lJi?= =?us-ascii?Q?XzGYt4ENnvTodRD9lkq1krkgbjg5T/ZU+vUHpHFeuDV7PFRLs8MUD0hJItUl?= =?us-ascii?Q?H0dFWMu8lCif/Rzb7ocTcoZJC+sgMQH9zsWDeMdLRViu6xfe+thW+MvxndbS?= =?us-ascii?Q?yZgpQ7HNzPNS98frk6fCHFIH7uC1JrQvQ0gTEP5SmSAC1QXijv7fGazPO3aK?= =?us-ascii?Q?Wj6FezxCFSRuQp65pB21Bwt7TfTmIQDwe9DclxXzmn7TEh2B896A1H5ym6Js?= =?us-ascii?Q?JQ4HDzWOz9YC4C2i5ZkSP4O083Ju4A24Qd7bymLLVMwN4refY3uFMFck1ehj?= =?us-ascii?Q?fgCtiFbg3QLr8BWJqJIb/wHsVDTeGGU7OG7CSNQwKDKJ8vlxmxjsYyO70PGy?= =?us-ascii?Q?49dCAeBamHw4ELYW8jBIT8QxCSglRcS2iGgnZ3+7R9STqEUgqyj6xVZVDafR?= =?us-ascii?Q?exrRs5qp5tfUzoefMm8Zp3QUHqJcKFTsPtbkkKWgMhglfBzojrN5E0oyHuLW?= =?us-ascii?Q?e6kUArRX2bv5m/2HVbS274dTFW3JiRn0aLw5EcV1NJJ6ReuTJ+Mqo8NsLbav?= =?us-ascii?Q?XLu5GfCp/R0UWYrW6Zhr9SHqEI3otaWxHeLvLOrgWwzuvj0JJMQ8pR/mTd4b?= =?us-ascii?Q?5ZDVUDdU0yijMEkO22NKHGsz6QDwKW8ABEkBMA+X4dQcsbfdMNA443kRxLsi?= =?us-ascii?Q?yu9RFiQr20xFh2+PNxEMFP3Jrxdbuoloyh9f9kGy71/H+szS8BEPpEaMF9u+?= =?us-ascii?Q?IHA2S+KSwfhzdIk4/hNVoSRZOI3uG0sJP9Sj+uJuF63PnxfLW+itQaznzrKW?= =?us-ascii?Q?WXyXVRXYFCR+gJv4+IM=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2025 10:14:20.8771 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 19083234-3037-4670-2a3b-08de07e5c78e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709B.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6414 From: Prathamesh Shete Extend the existing Tegra186 GPIO controller driver with support for the GPIO controller found on Tegra410. Tegra410 supports two GPIO controllers referred to as 'COMPUTE' and 'SYSTEM'. Co-developed-by: Nathan Hartman Signed-off-by: Nathan Hartman Signed-off-by: Prathamesh Shete Signed-off-by: Kartik Rajput --- v3 -> v4: * Remove TEGRA410_COMPUTE_GPIO and TEGRA410_SYSTEM_GPIO macros as they are not used. v2 -> v3: * Add a generic TEGRA_GPIO_PORT macro and use it to define TEGRA410_COMPUTE_GPIO_PORT and TEGRA410_SYSTEM_GPIO_PORT. v1 -> v2: * Move Tegra410 GPIO Ports definition to gpio-tegra186.c * Rename Tegra410 Main GPIO as System GPIO. * Add Compute GPIOs. * Update ACPI IDs. * Set instance ID as 0 for SYSTEM and COMPUTE GPIOs. * Added Nathan as co-author for adding compute GPIO support and renaming MAIN GPIOs as SYSTEM GPIOs. --- drivers/gpio/gpio-tegra186.c | 76 +++++++++++++++++++++++++++++++++++- 1 file changed, 75 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c index 7ea541d6d537..83ecdc876985 100644 --- a/drivers/gpio/gpio-tegra186.c +++ b/drivers/gpio/gpio-tegra186.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2016-2022 NVIDIA Corporation + * Copyright (c) 2016-2025 NVIDIA Corporation * * Author: Thierry Reding * Dipen Patel @@ -69,6 +69,30 @@ #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4) +/* Tegra410 GPIOs implemented by the COMPUTE GPIO controller */ +#define TEGRA410_COMPUTE_GPIO_PORT_A 0 +#define TEGRA410_COMPUTE_GPIO_PORT_B 1 +#define TEGRA410_COMPUTE_GPIO_PORT_C 2 +#define TEGRA410_COMPUTE_GPIO_PORT_D 3 +#define TEGRA410_COMPUTE_GPIO_PORT_E 4 + +/* Tegra410 GPIOs implemented by the SYSTEM GPIO controller */ +#define TEGRA410_SYSTEM_GPIO_PORT_A 0 +#define TEGRA410_SYSTEM_GPIO_PORT_B 1 +#define TEGRA410_SYSTEM_GPIO_PORT_C 2 +#define TEGRA410_SYSTEM_GPIO_PORT_D 3 +#define TEGRA410_SYSTEM_GPIO_PORT_E 4 +#define TEGRA410_SYSTEM_GPIO_PORT_I 5 +#define TEGRA410_SYSTEM_GPIO_PORT_J 6 +#define TEGRA410_SYSTEM_GPIO_PORT_K 7 +#define TEGRA410_SYSTEM_GPIO_PORT_L 8 +#define TEGRA410_SYSTEM_GPIO_PORT_M 9 +#define TEGRA410_SYSTEM_GPIO_PORT_N 10 +#define TEGRA410_SYSTEM_GPIO_PORT_P 11 +#define TEGRA410_SYSTEM_GPIO_PORT_Q 12 +#define TEGRA410_SYSTEM_GPIO_PORT_R 13 +#define TEGRA410_SYSTEM_GPIO_PORT_V 14 + struct tegra_gpio_port { const char *name; unsigned int bank; @@ -1267,6 +1291,54 @@ static const struct tegra_gpio_soc tegra256_main_soc = { .has_vm_support = true, }; +#define TEGRA410_COMPUTE_GPIO_PORT(_name, _bank, _port, _pins) \ + TEGRA_GPIO_PORT(TEGRA410_COMPUTE, _name, _bank, _port, _pins) + +static const struct tegra_gpio_port tegra410_compute_ports[] = { + TEGRA410_COMPUTE_GPIO_PORT(A, 0, 0, 3), + TEGRA410_COMPUTE_GPIO_PORT(B, 1, 0, 8), + TEGRA410_COMPUTE_GPIO_PORT(C, 1, 1, 3), + TEGRA410_COMPUTE_GPIO_PORT(D, 2, 0, 8), + TEGRA410_COMPUTE_GPIO_PORT(E, 2, 1, 8), +}; + +static const struct tegra_gpio_soc tegra410_compute_soc = { + .num_ports = ARRAY_SIZE(tegra410_compute_ports), + .ports = tegra410_compute_ports, + .name = "tegra410-gpio-compute", + .num_irqs_per_bank = 8, + .instance = 0, +}; + +#define TEGRA410_SYSTEM_GPIO_PORT(_name, _bank, _port, _pins) \ + TEGRA_GPIO_PORT(TEGRA410_SYSTEM, _name, _bank, _port, _pins) + +static const struct tegra_gpio_port tegra410_system_ports[] = { + TEGRA410_SYSTEM_GPIO_PORT(A, 0, 0, 7), + TEGRA410_SYSTEM_GPIO_PORT(B, 0, 1, 8), + TEGRA410_SYSTEM_GPIO_PORT(C, 0, 2, 8), + TEGRA410_SYSTEM_GPIO_PORT(D, 0, 3, 8), + TEGRA410_SYSTEM_GPIO_PORT(E, 0, 4, 6), + TEGRA410_SYSTEM_GPIO_PORT(I, 1, 0, 8), + TEGRA410_SYSTEM_GPIO_PORT(J, 1, 1, 7), + TEGRA410_SYSTEM_GPIO_PORT(K, 1, 2, 7), + TEGRA410_SYSTEM_GPIO_PORT(L, 1, 3, 7), + TEGRA410_SYSTEM_GPIO_PORT(M, 2, 0, 7), + TEGRA410_SYSTEM_GPIO_PORT(N, 2, 1, 6), + TEGRA410_SYSTEM_GPIO_PORT(P, 2, 2, 8), + TEGRA410_SYSTEM_GPIO_PORT(Q, 2, 3, 3), + TEGRA410_SYSTEM_GPIO_PORT(R, 2, 4, 2), + TEGRA410_SYSTEM_GPIO_PORT(V, 1, 4, 2), +}; + +static const struct tegra_gpio_soc tegra410_system_soc = { + .num_ports = ARRAY_SIZE(tegra410_system_ports), + .ports = tegra410_system_ports, + .name = "tegra410-gpio-system", + .num_irqs_per_bank = 8, + .instance = 0, +}; + static const struct of_device_id tegra186_gpio_of_match[] = { { .compatible = "nvidia,tegra186-gpio", @@ -1302,6 +1374,8 @@ static const struct acpi_device_id tegra186_gpio_acpi_match[] = { { .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc }, { .id = "NVDA0508", .driver_data = (kernel_ulong_t)&tegra241_main_soc }, { .id = "NVDA0608", .driver_data = (kernel_ulong_t)&tegra241_aon_soc }, + { .id = "NVDA0708", .driver_data = (kernel_ulong_t)&tegra410_compute_soc }, + { .id = "NVDA0808", .driver_data = (kernel_ulong_t)&tegra410_system_soc }, {} }; MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match); -- 2.43.0