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Fri, 10 Oct 2025 08:20:03 -0700 From: Vishwaroop A To: Mark Brown , Thierry Reding , Jonathan Hunter , "Sowjanya Komatineni" , Laxman Dewangan , , CC: Vishwaroop A , , , Subject: [PATCH v1 0/2] spi: tegra210-quad: Improve timeout handling under high system load Date: Fri, 10 Oct 2025 15:19:59 +0000 Message-ID: <20251010152001.2399799-1-va@nvidia.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D2:EE_|DS0PR12MB7969:EE_ X-MS-Office365-Filtering-Correlation-Id: 6fd9c31f-785e-49a2-d2b4-08de081089e2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?KAHup9s+QdOz3BNyy8pEyBzAYoI63b/xQuhZ+gcYiTfuouOh0iL/nVkTIroh?= =?us-ascii?Q?dZPXokz8TqFKqb6mTxZj5tjNvY35fQVsibqQW9lcrTXBL1D4ZpRBjouXNp8I?= =?us-ascii?Q?NPlq90b9jJBG1zeClFXXcnDev2WiCbCAEaw94YxC9QAfUji/TNvNaKq0rQep?= =?us-ascii?Q?6PaWtPxdF9HkXNh+G02e2frGjljz60QQANYePAzWb+FuKtUSeujsw2Ps63XA?= =?us-ascii?Q?vUWSEN4WVRRKPqHtp+msUG9oZxkeQ3KcjJWi7CZNonzwiyIDIUfJxpdl4FR3?= =?us-ascii?Q?6DgNkNVrbNl2PcRlMrE2bncQsOUR4fEe365zjZpV6TtWC6ggX5KwM3V5j2ux?= =?us-ascii?Q?HnxOvi2YI4iAUYjP9f98ADeZBrRuKk9kfRHoYFUFkWh2m53T1vf3556Mo/LI?= =?us-ascii?Q?V3p1wxfV2me/cCWNJrQJH3Xj1Nr65q4zKfU2B7wL2tf4hfsLZ52PTNmzln47?= =?us-ascii?Q?zFSIMUf994kI4V4MMgvX1IO9WLbSIpkACQJHZf0NTE+xVRYrf7Qxk+TBIxUZ?= =?us-ascii?Q?GBqRYlBGpBBkh8qUCHR8dKYYPw6ZsGFKkoI0Z7UP2CstENmEkxgKm6U/TkDr?= =?us-ascii?Q?+CrHcF36BwAcM77blbX2A8AuVTn0fc//GJs9KLH+IBEr+aa/ohtcUHTipo48?= =?us-ascii?Q?nKXXo7LLzRi7FiboeVPysg2L8sfXIHScZJXzDSdgIcdn8IdGlKPOQT8+arQJ?= =?us-ascii?Q?Ye27FJ1IHDDYEuQVWzmItZwI7MlZf37+d/BeSgyckG4kZGTX8lgKgTj8A7IT?= =?us-ascii?Q?IPJUrOKq27eXmg3pg2w+3THJumUO0Ae9qkXd6f4052cmKk+BttfC3vZzhoOB?= =?us-ascii?Q?KnL6HK1RRqoscKdiJuTucGUBmAqAHnaEJHtXiWbMWs62855Gw4LyCHmjtxJN?= =?us-ascii?Q?zBnqWzcSh3JwoHLfTK4lBXxkiX2k7l8/ypO6EVyxXOzH+TXeACd2jeycX6CB?= =?us-ascii?Q?dHoWjxz7u2gdEpmc/XS6kESDrpX+gzLLRCdMttFCvE73aaEzYtSkmA718fHV?= =?us-ascii?Q?5AJVjvIb+tGHTcNjv/w7D5zUSVW3OncOXGzOFMX63i1VxgOm8ooeHdJCOP+y?= =?us-ascii?Q?2vRife9cQKmkBNDqOGVj83rlZHt+ky8+GJdtYKvmB1oD8DiW+rqeQ4YERaVc?= =?us-ascii?Q?oV2Lh0YaOcILqFNGyR0IB61N3SfQRcKAF84fHP0uL384lYeNd70OFGpztFmC?= =?us-ascii?Q?s52HBpzhQrdS5ZYgmg6xgCdpn2d8y5eBL5DhxK5GgLpbMpdAwlsldllBJctW?= =?us-ascii?Q?HJXUVAJNnFFaOzNYJAGj2qUlLnsMa3mRbucCmH0fZxBkI1DSqfj6Y9RFOCIE?= =?us-ascii?Q?VUHuSNw0vuV9QPcGmxMvBSjX6+gmRBXJ9DnlkfSU/5HsEFsbzeuC5QdbLGF+?= =?us-ascii?Q?RsmkSBlI+qyxuNoF7UeM2MmJ8P2ni1XDYitXBb/132xjo0LfHOsjhHKtktor?= =?us-ascii?Q?BBM4iHBLivOirZyMRXzCTNdnynzDbFF4Uy7cWfZ6oMBiPj/f9AkSpj6Aa1oH?= =?us-ascii?Q?8SZMq7sKEZkXMOzCLmFgZHCjFINLYaxvR6p4TR6VjxaqUyrX5ppcxtW5ZJkW?= =?us-ascii?Q?m7JlyJKxAmWyVUM+dJ4=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2025 15:20:25.7716 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6fd9c31f-785e-49a2-d2b4-08de081089e2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7969 Hi, This patch series addresses timeout handling issues in the Tegra QSPI driver that occur under high system load conditions. We've observed that when CPUs are saturated (due to error injection, RAS firmware activity, or general CPU contention), QSPI interrupt handlers can be delayed, causing spurious transfer failures even though the hardware completed the operation successfully. Patch 1 fixes a stale pointer issue by ensuring curr_xfer is cleared on timeout and checked when the IRQ thread finally runs. It also ensures interrupts are properly cleared on failure paths. Patch 2 adds hardware status checking on timeout. Before failing a transfer, the driver now reads QSPI_TRANS_STATUS to verify if the hardware actually completed the operation. If so, it manually invokes the completion handler instead of failing the transfer. This distinguishes genuine hardware timeouts from delayed/lost interrupts. These changes have been tested in production environments under various high load scenarios including RAS testing and CPU saturation workloads. Testing: - Verified normal operation under light load - Tested under heavy CPU load with concurrent workloads - Validated with RAS firmware activity and error injection - Confirmed no regressions in existing timeout behavior Thierry Reding (1): spi: tegra210-quad: Fix timeout handling Vishwaroop A (1): spi: tegra210-quad: Check hardware status on timeout drivers/spi/spi-tegra210-quad.c | 195 ++++++++++++++++++++++++++------ 1 file changed, 138 insertions(+), 57 deletions(-) -- 2.34.1