From: Anshuman Khandual <anshuman.khandual@arm.com>
To: linux-kernel@vger.kernel.org
Cc: Anshuman Khandual <anshuman.khandual@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>,
Mark Brown <broonie@kernel.org>,
Ryan Roberts <ryan.roberts@arm.com>,
kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org
Subject: [PATCH V6 3/3] KVM: arm64: Move inside all required TCR_XXX macros
Date: Mon, 13 Oct 2025 10:59:45 +0530 [thread overview]
Message-ID: <20251013052945.2197190-4-anshuman.khandual@arm.com> (raw)
In-Reply-To: <20251013052945.2197190-1-anshuman.khandual@arm.com>
Move all required TCR_XXX macros into KVM header (asm/kvm_arm.h) for their
continued usage in KVM.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: kvmarm@lists.linux.dev
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
arch/arm64/include/asm/kvm_arm.h | 45 ++++++++++++++++++++++++++
arch/arm64/include/asm/pgtable-hwdef.h | 45 --------------------------
2 files changed, 45 insertions(+), 45 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index 1da290aeedce..0b2cfb13299b 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -107,6 +107,51 @@
#define MPAMHCR_HOST_FLAGS 0
+#define TCR_T0SZ_MASK TCR_EL1_T0SZ_MASK
+#define TCR_T1SZ_MASK TCR_EL1_T1SZ_MASK
+
+#define TCR_EPD0_MASK TCR_EL1_EPD0_MASK
+#define TCR_EPD1_MASK TCR_EL1_EPD1_MASK
+
+#define TCR_IRGN0_MASK TCR_EL1_IRGN0_MASK
+#define TCR_IRGN0_WBWA (TCR_EL1_IRGN0_WBWA << TCR_EL1_IRGN0_SHIFT)
+
+#define TCR_ORGN0_MASK TCR_EL1_ORGN0_MASK
+#define TCR_ORGN0_WBWA (TCR_EL1_ORGN0_WBWA << TCR_EL1_ORGN0_SHIFT)
+
+#define TCR_SH0_MASK TCR_EL1_SH0_MASK
+#define TCR_SH0_INNER (TCR_EL1_SH0_INNER << TCR_EL1_SH0_SHIFT)
+
+#define TCR_SH1_MASK TCR_EL1_SH1_MASK
+
+#define TCR_TG0_SHIFT TCR_EL1_TG0_SHIFT
+#define TCR_TG0_MASK TCR_EL1_TG0_MASK
+#define TCR_TG0_4K (TCR_EL1_TG0_4K << TCR_EL1_TG0_SHIFT)
+#define TCR_TG0_64K (TCR_EL1_TG0_64K << TCR_EL1_TG0_SHIFT)
+#define TCR_TG0_16K (TCR_EL1_TG0_16K << TCR_EL1_TG0_SHIFT)
+
+#define TCR_TG1_SHIFT TCR_EL1_TG1_SHIFT
+#define TCR_TG1_MASK TCR_EL1_TG1_MASK
+#define TCR_TG1_16K (TCR_EL1_TG1_16K << TCR_EL1_TG1_SHIFT)
+#define TCR_TG1_4K (TCR_EL1_TG1_4K << TCR_EL1_TG1_SHIFT)
+#define TCR_TG1_64K (TCR_EL1_TG1_64K << TCR_EL1_TG1_SHIFT)
+
+#define TCR_IPS_SHIFT TCR_EL1_IPS_SHIFT
+#define TCR_IPS_MASK TCR_EL1_IPS_MASK
+#define TCR_A1 TCR_EL1_A1
+#define TCR_ASID16 TCR_EL1_AS
+#define TCR_TBI0 TCR_EL1_TBI0
+#define TCR_TBI1 TCR_EL1_TBI1
+#define TCR_HA TCR_EL1_HA
+#define TCR_HD TCR_EL1_HD
+#define TCR_HPD0 TCR_EL1_HPD0
+#define TCR_HPD1 TCR_EL1_HPD1
+#define TCR_TBID0 TCR_EL1_TBID0
+#define TCR_TBID1 TCR_EL1_TBID1
+#define TCR_E0PD0 TCR_EL1_E0PD0
+#define TCR_E0PD1 TCR_EL1_E0PD1
+#define TCR_DS TCR_EL1_DS
+
/* TCR_EL2 Registers bits */
#define TCR_EL2_DS (1UL << 32)
#define TCR_EL2_RES1 ((1U << 31) | (1 << 23))
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index d49180bb7cb3..5059abda78d8 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -231,51 +231,6 @@
#define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_EL1_T0SZ_SHIFT)
#define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_EL1_T1SZ_SHIFT)
-#define TCR_T0SZ_MASK TCR_EL1_T0SZ_MASK
-#define TCR_T1SZ_MASK TCR_EL1_T1SZ_MASK
-
-#define TCR_EPD0_MASK TCR_EL1_EPD0_MASK
-#define TCR_EPD1_MASK TCR_EL1_EPD1_MASK
-
-#define TCR_IRGN0_MASK TCR_EL1_IRGN0_MASK
-#define TCR_IRGN0_WBWA (TCR_EL1_IRGN0_WBWA << TCR_EL1_IRGN0_SHIFT)
-
-#define TCR_ORGN0_MASK TCR_EL1_ORGN0_MASK
-#define TCR_ORGN0_WBWA (TCR_EL1_ORGN0_WBWA << TCR_EL1_ORGN0_SHIFT)
-
-#define TCR_SH0_MASK TCR_EL1_SH0_MASK
-#define TCR_SH0_INNER (TCR_EL1_SH0_INNER << TCR_EL1_SH0_SHIFT)
-
-#define TCR_SH1_MASK TCR_EL1_SH1_MASK
-
-#define TCR_TG0_SHIFT TCR_EL1_TG0_SHIFT
-#define TCR_TG0_MASK TCR_EL1_TG0_MASK
-#define TCR_TG0_4K (TCR_EL1_TG0_4K << TCR_EL1_TG0_SHIFT)
-#define TCR_TG0_64K (TCR_EL1_TG0_64K << TCR_EL1_TG0_SHIFT)
-#define TCR_TG0_16K (TCR_EL1_TG0_16K << TCR_EL1_TG0_SHIFT)
-
-#define TCR_TG1_SHIFT TCR_EL1_TG1_SHIFT
-#define TCR_TG1_MASK TCR_EL1_TG1_MASK
-#define TCR_TG1_16K (TCR_EL1_TG1_16K << TCR_EL1_TG1_SHIFT)
-#define TCR_TG1_4K (TCR_EL1_TG1_4K << TCR_EL1_TG1_SHIFT)
-#define TCR_TG1_64K (TCR_EL1_TG1_64K << TCR_EL1_TG1_SHIFT)
-
-#define TCR_IPS_SHIFT TCR_EL1_IPS_SHIFT
-#define TCR_IPS_MASK TCR_EL1_IPS_MASK
-#define TCR_A1 TCR_EL1_A1
-#define TCR_ASID16 TCR_EL1_AS
-#define TCR_TBI0 TCR_EL1_TBI0
-#define TCR_TBI1 TCR_EL1_TBI1
-#define TCR_HA TCR_EL1_HA
-#define TCR_HD TCR_EL1_HD
-#define TCR_HPD0 TCR_EL1_HPD0
-#define TCR_HPD1 TCR_EL1_HPD1
-#define TCR_TBID0 TCR_EL1_TBID0
-#define TCR_TBID1 TCR_EL1_TBID1
-#define TCR_E0PD0 TCR_EL1_E0PD0
-#define TCR_E0PD1 TCR_EL1_E0PD1
-#define TCR_DS TCR_EL1_DS
-
/*
* TTBR.
*/
--
2.25.1
next prev parent reply other threads:[~2025-10-13 5:30 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-13 5:29 [PATCH V6 0/3] arm64/sysreg: Clean up TCR_EL1 field macros Anshuman Khandual
2025-10-13 5:29 ` [PATCH V6 1/3] tools: header: arm64: Replace TCR_NFD[0|1] with TCR_EL1_NFD[0|1] Anshuman Khandual
2025-11-03 17:31 ` Catalin Marinas
2025-11-03 18:03 ` Leo Yan
2025-11-13 9:09 ` Anshuman Khandual
2025-10-13 5:29 ` [PATCH V6 2/3] arm64/sysreg: Replace TCR_EL1 field macros Anshuman Khandual
2025-10-13 5:29 ` Anshuman Khandual [this message]
2025-11-13 18:59 ` (subset) [PATCH V6 0/3] arm64/sysreg: Clean up " Catalin Marinas
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