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From: Conor Dooley <conor@kernel.org>
To: Vivian Wang <wangruikang@iscas.ac.cn>
Cc: Lucas Zampieri <lzampier@redhat.com>,
	linux-kernel@vger.kernel.org,
	Charles Mirabile <cmirabil@redhat.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Samuel Holland <samuel.holland@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>,
	Vivian Wang <dramforever@live.com>,
	linux-riscv@lists.infradead.org,
	Zhang Xincheng <zhangxincheng@ultrarisc.com>
Subject: Re: [PATCH v2 3/3] irqchip/plic: add support for UltraRISC DP1000 PLIC
Date: Tue, 14 Oct 2025 18:47:26 +0100	[thread overview]
Message-ID: <20251014-coma-zeppelin-56256bf7e3e6@spud> (raw)
In-Reply-To: <6b7c3c90-d3bd-4d75-9cc0-74d3945fbdfd@iscas.ac.cn>

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On Tue, Oct 14, 2025 at 05:14:17PM +0800, Vivian Wang wrote:
> Hi Conor,
> 
> On 10/14/25 02:30, Conor Dooley wrote:
> > On Mon, Oct 13, 2025 at 12:15:38PM +0100, Lucas Zampieri wrote:
> >> From: Charles Mirabile <cmirabil@redhat.com>
> >>
> >> Add a new compatible for the plic found in UltraRISC DP1000 with a quirk to
> >> work around a known hardware bug with IRQ claiming.
> >>
> >> When claiming an interrupt on the DP1000 PLIC all other interrupts must be
> >> disabled before the claim register is accessed to prevent incorrect
> >> handling of the interrupt.
> >>
> >> When the PLIC_QUIRK_CLAIM_REGISTER is present, during plic_handle_irq
> >> the enable state of all interrupts is saved and then all interrupts
> >> except for the first pending one are disabled before reading the claim
> >> register. The interrupts are then restored before further processing of
> >> the claimed interrupt continues.
> >>
> >> The driver matches on "ultrarisc,cp100-plic" to apply the quirk to all
> >> SoCs using UR-CP100 cores, regardless of the specific SoC implementation.
> > Why is that? I expect that you're doing that intentionally given the
> > ultrarisc employee listed as a co-developer, but with only one SoC using
> > this IP core it seems possible that this bug in the hardware could be
> > fixed for other SoCs that are built using this IP core.
> > Is there a plan to, for example, change the core version to UR-CP101
> > when the bug is fixed?
> 
> I originally proposed to match on ultrarisc,cp100-plic under the
> assumption that it would be the case.
> 
> Furthermore, it is my understanding that if the bug is fixed in, say,
> UR-DP1001, then the PLIC node can simply be
> 
>     compatible = "ultrarisc,dp1001-plic", "sifive,plic-1.0.0";
> 
> I meant my reply that I had assumed this bug was associated with the
> UR-CP100 core, but I should have stated so more clearly. 

Ah ye, very true, could be done that way if there's a changed version
that's compliant.

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  parent reply	other threads:[~2025-10-14 17:47 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-13 11:15 [PATCH v2 0/3] Add UltraRISC DP1000 PLIC support Lucas Zampieri
2025-10-13 11:15 ` [PATCH v2 1/3] dt-bindings: vendor-prefixes: add UltraRISC Lucas Zampieri
2025-10-13 11:15 ` [PATCH v2 2/3] dt-bindings: interrupt-controller: add UltraRISC DP1000 PLIC Lucas Zampieri
2025-10-13 18:25   ` Conor Dooley
2025-10-13 11:15 ` [PATCH v2 3/3] irqchip/plic: add support for " Lucas Zampieri
2025-10-13 18:30   ` Conor Dooley
2025-10-14  9:14     ` Vivian Wang
2025-10-14 14:35       ` Lucas Zampieri
2025-10-14 17:47       ` Conor Dooley [this message]
2025-10-13 19:00   ` Samuel Holland
2025-10-13 21:03     ` Charles Mirabile
2025-10-13 21:58       ` Samuel Holland
2025-10-13 21:24     ` Bo Gan
2025-10-13 22:04       ` Samuel Holland

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