From: Wen Yang <wen.yang@linux.dev>
To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jon Hunter <jonathanh@nvidia.com>
Cc: stable@vger.kernel.org, linux-kernel@vger.kernel.org,
Pierre Gondois <pierre.gondois@arm.com>,
Thierry Reding <treding@nvidia.com>,
Wen Yang <wen.yang@linux.dev>
Subject: [PATCH 6.1 10/10] arm64: tegra: Update cache properties
Date: Tue, 21 Oct 2025 01:36:24 +0800 [thread overview]
Message-ID: <20251020173624.20228-11-wen.yang@linux.dev> (raw)
In-Reply-To: <20251020173624.20228-1-wen.yang@linux.dev>
From: Pierre Gondois <pierre.gondois@arm.com>
[ Upstream commit 27f1568b1d5fe35014074f92717b250afbe67031 ]
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Wen Yang <wen.yang@linux.dev>
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 15 +++++++++++
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 1 +
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 33 ++++++++++++++++++++++++
3 files changed, 49 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 41f3a7e188d0..ed2a534dcfd6 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -3029,36 +3029,51 @@ core1 {
};
l2c_0: l2-cache0 {
+ compatible = "cache";
+ cache-unified;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
+ cache-level = <2>;
next-level-cache = <&l3c>;
};
l2c_1: l2-cache1 {
+ compatible = "cache";
+ cache-unified;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
+ cache-level = <2>;
next-level-cache = <&l3c>;
};
l2c_2: l2-cache2 {
+ compatible = "cache";
+ cache-unified;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
+ cache-level = <2>;
next-level-cache = <&l3c>;
};
l2c_3: l2-cache3 {
+ compatible = "cache";
+ cache-unified;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
+ cache-level = <2>;
next-level-cache = <&l3c>;
};
l3c: l3-cache {
+ compatible = "cache";
+ cache-unified;
cache-size = <4194304>;
cache-line-size = <64>;
+ cache-level = <3>;
cache-sets = <4096>;
};
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 724e87450605..9474b0da0a3e 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -2005,6 +2005,7 @@ CPU_SLEEP: cpu-sleep {
L2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 876c73a00a54..e09a4fd8364c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -2907,117 +2907,150 @@ core3 {
};
l2c0_0: l2-cache00 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c0>;
};
l2c0_1: l2-cache01 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c0>;
};
l2c0_2: l2-cache02 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c0>;
};
l2c0_3: l2-cache03 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c0>;
};
l2c1_0: l2-cache10 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c1>;
};
l2c1_1: l2-cache11 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c1>;
};
l2c1_2: l2-cache12 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c1>;
};
l2c1_3: l2-cache13 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c1>;
};
l2c2_0: l2-cache20 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c2>;
};
l2c2_1: l2-cache21 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c2>;
};
l2c2_2: l2-cache22 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c2>;
};
l2c2_3: l2-cache23 {
+ compatible = "cache";
cache-size = <262144>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
+ cache-level = <2>;
next-level-cache = <&l3c2>;
};
l3c0: l3-cache0 {
+ compatible = "cache";
+ cache-unified;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
+ cache-level = <3>;
};
l3c1: l3-cache1 {
+ compatible = "cache";
+ cache-unified;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
+ cache-level = <3>;
};
l3c2: l3-cache2 {
+ compatible = "cache";
+ cache-unified;
cache-size = <2097152>;
cache-line-size = <64>;
cache-sets = <2048>;
+ cache-level = <3>;
};
};
--
2.25.1
prev parent reply other threads:[~2025-10-20 17:38 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-20 17:36 [PATCH 6.1 v2 00/10] fix invalid sleeping in detect_cache_attributes() Wen Yang
2025-10-20 17:36 ` [PATCH 6.1 01/10] cacheinfo: Use RISC-V's init_cache_level() as generic OF implementation Wen Yang
2025-10-20 17:36 ` [PATCH 6.1 02/10] cacheinfo: Return error code in init_of_cache_level() Wen Yang
2025-10-20 17:36 ` [PATCH 6.1 03/10] cacheinfo: Check 'cache-unified' property to count cache leaves Wen Yang
2025-10-20 17:36 ` [PATCH 6.1 04/10] ACPI: PPTT: Remove acpi_find_cache_levels() Wen Yang
2025-10-20 17:36 ` [PATCH 6.1 05/10] ACPI: PPTT: Update acpi_find_last_cache_level() to acpi_get_cache_info() Wen Yang
2025-10-20 17:36 ` [PATCH 6.1 06/10] arch_topology: Build cacheinfo from primary CPU Wen Yang
2025-10-20 17:36 ` [PATCH 6.1 07/10] cacheinfo: Initialize variables in fetch_cache_info() Wen Yang
2025-10-20 17:36 ` [PATCH 6.1 08/10] cacheinfo: Fix LLC is not exported through sysfs Wen Yang
2025-10-20 17:36 ` [PATCH 6.1 09/10] drivers: base: cacheinfo: Update cpu_map_populated during CPU Hotplug Wen Yang
2025-10-20 17:36 ` Wen Yang [this message]
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