From: Jason Gunthorpe <jgg@nvidia.com>
To: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Cc: nicolinc@nvidia.com, linux-kernel@vger.kernel.org,
robin.murphy@arm.com, will@kernel.org, joro@8bytes.org,
kevin.tian@intel.com, jsnitsel@redhat.com, vasant.hegde@amd.com,
iommu@lists.linux.dev, santosh.shukla@amd.com,
sairaj.arunkodilkar@amd.com, jon.grimm@amd.com,
prashanthpra@google.com, wvw@google.com, wnliu@google.com,
gptran@google.com, kpsingh@google.com, joao.m.martins@oracle.com,
alejandro.j.jimenez@oracle.com
Subject: Re: [PATCH v4 15/16] iommu/amd: Refactor logic to program the host page table in DTE
Date: Thu, 23 Oct 2025 10:08:33 -0300 [thread overview]
Message-ID: <20251023130833.GF262900@nvidia.com> (raw)
In-Reply-To: <20251021014324.5837-16-suravee.suthikulpanit@amd.com>
On Tue, Oct 21, 2025 at 01:43:23AM +0000, Suravee Suthikulpanit wrote:
> @@ -2088,37 +2104,28 @@ static void set_dte_entry(struct amd_iommu *iommu,
> else
> domid = domain->id;
>
> /*
> * When SNP is enabled, we can only support TV=1 with non-zero domain ID.
> * This is prevented by the SNP-enable and IOMMU_DOMAIN_IDENTITY check in
> * do_iommu_domain_alloc().
> */
> WARN_ON(amd_iommu_snp_en && (domid == 0));
>
> + amd_iommu_make_clear_dte(dev_data, &new);
>
> + old_domid = READ_ONCE(dte->data[1]) & DTE_DOMID_MASK;
This old_domid stuff doesn't make any sense. I think the commit that
added it is bonkers: 36b7200f67df ("iommu/amd: Flush old domains in kdump kernel")
The problem is that the dom ids that are present in the re-used DTE
table have to be reserved from the domain id alloctor at boot.
If the kdump kernel tries to create new DTEs it MUST NOT re-use any
IDs that are actively being using in DTEs already or you get data
corruption. Randomly flushing IDs is just getting lucky..
Not for this series, but something to think about.
> + if (gcr3_info && gcr3_info->gcr3_tbl)
> + set_dte_gcr3_table(dev_data, &new);
> + else if (domain->iop.mode != PAGE_MODE_NONE)
> + amd_iommu_set_dte_v1(dev_data, domain, &new);
>
> + /* Note: The IR, IW, TV, DOMID are needed for both v1 and gcr3 table */
> + new.data[0] |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_TV;
> + new.data[1] |= FIELD_PREP(DTE_DOMID_MASK, domid);
>
> + if (dev_data->ats_enabled)
> + new.data[1] |= DTE_FLAG_IOTLB;
These three should be merged into the two functions so they stand
alone. These sets have to be made in the next patch, doesn't make
sense to open code them in callers.
Like this, it is simple and readable. It directly answers the question
'what bits are set when the driver creates this kind of DTE'
static void set_dte_gcr3_table(struct amd_iommu *iommu,
struct iommu_dev_data *dev_data,
struct dev_table_entry *target)
{
struct gcr3_tbl_info *gcr3_info = &dev_data->gcr3_info;
u64 gcr3 = iommu_virt_to_phys(gcr3_info->gcr3_tbl);
target->data[0] |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_TV |
DTE_FLAG_GV | FIELD_PREP(DTE_GLX, gcr3_info->glx) |
FIELD_PREP(DTE_GCR3_14_12, gcr3 >> 12) |
(dev_data->ats_enabled ? DTE_FLAG_IOTLB : 0) |
(pdom_is_v2_pgtbl_mode(dev_data->domain) ?
target->data[0] |= DTE_FLAG_GIOV :
0);
target->data[1] |= FIELD_PREP(DTE_GCR3_30_15, gcr3 >> 15) |
FIELD_PREP(DTE_GCR3_51_31, gcr3 >> 31) |
FIELD_PREP(DTE_DOMID_MASK, dev_data->gcr3_info.domid);
/* Guest page table can only support 4 and 5 levels */
if (amd_iommu_gpt_level == PAGE_MODE_5_LEVEL)
target->data[2] |= FIELD_PREP(DTE_GPT_LEVEL_MASK, GUEST_PGTABLE_5_LEVEL);
else
target->data[2] |= FIELD_PREP(DTE_GPT_LEVEL_MASK, GUEST_PGTABLE_4_LEVEL);
}
void amd_iommu_set_dte_v1(struct iommu_dev_data *dev_data,
struct protection_domain *domain,
struct dev_table_entry *new)
{
u64 htrp = iommu_virt_to_phys(domain->iop.root);
new->data[0] |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_TV |
FIELD_PREP(DTE_MODE_MASK, domain->iop.mode) |
FIELD_PREP(DTE_HOST_TRP, htrp >> 12) |
(dev_data->ats_enabled ? DTE_FLAG_IOTLB : 0) |
(domain->dirty_tracking ? DTE_FLAG_HAD : 0);
new.data[1] |= FIELD_PREP(DTE_DOMID_MASK, domain->id);
}
(It is nice to sort the fields by the spec order, I didn't do that)
Looks like an identity one is needed too:
void set_dte_identity(struct dev_table_entry *new)
{
new->data[0] |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_TV |
(dev_data->ats_enabled ? DTE_FLAG_IOTLB : 0);
}
Then the whole function is pretty much just:
amd_iommu_make_clear_dte(dev_data, &new);
if (gcr3_info && gcr3_info->gcr3_tbl)
set_dte_gcr3_table(dev_data, &new);
else if (domain->domain.type == IOMMU_DOMAIN_IDENTITY)
set_dte_identity(&new)
else if (domain->domain.type == IOMMU_DOMAIN_PAGING && io.mode == V1)
amd_iommu_set_dte_v1(dev_data, domain, &new);
else
WARN_ON(true);
?
(though how does IDENTITY on a device with a PASID installed work?)
Jason
next prev parent reply other threads:[~2025-10-23 13:08 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-21 1:43 [PATCH v4 00/16] iommu/amd: Introduce Nested Translation support Suravee Suthikulpanit
2025-10-21 1:43 ` [PATCH v4 01/16] iommu/amd: Rename DEV_DOMID_MASK to DTE_DOMID_MASK Suravee Suthikulpanit
2025-11-08 17:25 ` Vasant Hegde
2025-10-21 1:43 ` [PATCH v4 02/16] iommu/amd: Make amd_iommu_pdom_id_alloc() non-static Suravee Suthikulpanit
2025-11-08 17:24 ` Vasant Hegde
2025-10-21 1:43 ` [PATCH v4 03/16] iommu/amd: Make amd_iommu_pdom_id_free() non-static Suravee Suthikulpanit
2025-11-08 17:26 ` Vasant Hegde
2025-10-21 1:43 ` [PATCH v4 04/16] iommu/amd: Make amd_iommu_device_flush_dte() non-static Suravee Suthikulpanit
2025-11-08 17:27 ` Vasant Hegde
2025-10-21 1:43 ` [PATCH v4 05/16] iommu/amd: Make amd_iommu_update_dte256() non-static Suravee Suthikulpanit
2025-11-08 17:27 ` Vasant Hegde
2025-10-21 1:43 ` [PATCH v4 06/16] iommu/amd: Make amd_iommu_make_clear_dte() non-static inline Suravee Suthikulpanit
2025-11-08 17:27 ` Vasant Hegde
2025-10-21 1:43 ` [PATCH v4 07/16] iommu/amd: Make amd_iommu_completion_wait() non-static Suravee Suthikulpanit
2025-11-08 17:32 ` Vasant Hegde
2025-10-21 1:43 ` [PATCH v4 08/16] iommufd: Introduce data struct for AMD nested domain allocation Suravee Suthikulpanit
2025-11-08 17:30 ` Vasant Hegde
2025-10-21 1:43 ` [PATCH v4 09/16] iommu/amd: Always enable GCR3TRPMode when supported Suravee Suthikulpanit
2025-10-23 2:24 ` Nicolin Chen
2025-11-08 17:39 ` Vasant Hegde
2025-11-11 13:59 ` Suthikulpanit, Suravee
2025-10-21 1:43 ` [PATCH v4 10/16] iommu/amd: Add support for nest parent domain allocation Suravee Suthikulpanit
2025-10-23 2:27 ` Nicolin Chen
2025-10-23 20:08 ` Suthikulpanit, Suravee
2025-10-21 1:43 ` [PATCH v4 11/16] iommu/amd: Introduce struct amd_iommu_viommu Suravee Suthikulpanit
2025-10-22 20:00 ` Jason Gunthorpe
2025-10-23 2:33 ` Nicolin Chen
2025-10-21 1:43 ` [PATCH v4 12/16] iommu/amd: Add support for nested domain allocation Suravee Suthikulpanit
2025-10-22 20:01 ` Jason Gunthorpe
2025-10-21 1:43 ` [PATCH v4 13/16] iommu/amd: Track host Domain ID mapping for each guest Domain ID Suravee Suthikulpanit
2025-10-22 20:08 ` Jason Gunthorpe
2025-11-05 10:50 ` Suthikulpanit, Suravee
2025-11-05 13:35 ` Jason Gunthorpe
2025-10-21 1:43 ` [PATCH v4 14/16] iommu/amd: Refactor persistent DTE bits programming into amd_iommu_make_clear_dte() Suravee Suthikulpanit
2025-10-23 2:49 ` Nicolin Chen
2025-10-21 1:43 ` [PATCH v4 15/16] iommu/amd: Refactor logic to program the host page table in DTE Suravee Suthikulpanit
2025-10-23 13:08 ` Jason Gunthorpe [this message]
2025-11-08 17:26 ` Vasant Hegde
2025-11-08 23:03 ` Jason Gunthorpe
2025-11-12 18:40 ` Suthikulpanit, Suravee
2025-11-17 18:08 ` Jason Gunthorpe
2025-10-21 1:43 ` [PATCH v4 16/16] iommu/amd: Add support for nested domain attach/detach Suravee Suthikulpanit
2025-10-23 13:17 ` Jason Gunthorpe
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