From: Michal Pecio <michal.pecio@gmail.com>
To: Yazen Ghannam <yazen.ghannam@amd.com>
Cc: Shyam-sundar.S-k@amd.com, bhelgaas@google.com,
hdegoede@redhat.com, ilpo.jarvinen@linux.intel.com,
jdelvare@suse.com, linux-edac@vger.kernel.org,
linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org, linux@roeck-us.net,
mario.limonciello@amd.com, naveenkrishna.chatradhi@amd.com,
platform-driver-x86@vger.kernel.org, suma.hegde@amd.com,
tony.luck@intel.com, x86@kernel.org
Subject: Re: [PATCH v3 06/12] x86/amd_nb: Use topology info to get AMD node count
Date: Thu, 23 Oct 2025 18:31:54 +0200 [thread overview]
Message-ID: <20251023183154.1e807af6.michal.pecio@gmail.com> (raw)
In-Reply-To: <20251023160906.GA730672@yaz-khff2.amd.com>
[-- Attachment #1: Type: text/plain, Size: 1689 bytes --]
On Thu, 23 Oct 2025 12:09:06 -0400, Yazen Ghannam wrote:
> On Thu, Oct 23, 2025 at 05:01:07PM +0200, Michal Pecio wrote:
> > On Thu, 23 Oct 2025 09:59:35 -0400, Yazen Ghannam wrote:
> > > Thanks Michal.
> > >
> > > I don't see anything obviously wrong.
> >
> > Which code is responsible for setting up those bitmaps which
> > are counted by topology_init_possible_cpus()?
> >
> > I guess I could add some printks there and reboot.
> >
>
> The kernel seems to think there are 6 CPUs on your system:
>
> [ 0.072059] CPU topo: Allowing 4 present CPUs plus 2 hotplug CPUs
I thought this is because I have NR_CPUS set to 6, as this config
originally came from the X6 machine, but I am not sure.
>
> We don't seem them enabled, but they may still get APIC IDs. If so, then
> the IDs would be beyond the core shift of 2.
>
> APIC IDs b'0 00 -> CPU0 on logical package 0
> b'0 01 -> CPU1 on logical package 0
> b'0 10 -> CPU2 on logical package 0
> b'0 11 -> CPU3 on logical package 0
> b'1 00 -> CPU0 on logical package 1
> b'1 01 -> CPU1 on logical package 1
>
>
> Please try booting with "possible_cpus=4".
OK, will try it next time I'm rebooting.
> The "number of possible CPUs" comes from the ACPI Multiple APIC
> Description Table (MADT). This has the signature "APIC".
>
> Can you please provide the disassembly of this table?
Interesting, it looks like there are indeed 6 LAPICs there.
BIOS bug? Attaching apic.dsl.
> Can you please share the dmesg output from that system? And the ACPI
> table too?
Will try later but I don't recall any anomalies there.
I remember checking the topology output and it made sense:
1 package, 1 die, 6 cores, 6 threads.
[-- Attachment #2: apic.dsl --]
[-- Type: text/x-dsl, Size: 5143 bytes --]
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20211217 (64-bit version)
* Copyright (c) 2000 - 2021 Intel Corporation
*
* Disassembly of apic.dat, Thu Oct 23 18:19:16 2025
*
* ACPI Data Table [APIC]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue (in hex)
*/
[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
[004h 0004 4] Table Length : 0000007C
[008h 0008 1] Revision : 01
[009h 0009 1] Checksum : F5
[00Ah 0010 6] Oem ID : "080912"
[010h 0016 8] Oem Table ID : "APIC1703"
[018h 0024 4] Oem Revision : 20120809
[01Ch 0028 4] Asl Compiler ID : "MSFT"
[020h 0032 4] Asl Compiler Revision : 00000097
[024h 0036 4] Local Apic Address : FEE00000
[028h 0040 4] Flags (decoded below) : 00000001
PC-AT Compatibility : 1
[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
[02Dh 0045 1] Length : 08
[02Eh 0046 1] Processor ID : 01
[02Fh 0047 1] Local Apic ID : 00
[030h 0048 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Runtime Online Capable : 0
[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
[035h 0053 1] Length : 08
[036h 0054 1] Processor ID : 02
[037h 0055 1] Local Apic ID : 01
[038h 0056 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Runtime Online Capable : 0
[03Ch 0060 1] Subtable Type : 00 [Processor Local APIC]
[03Dh 0061 1] Length : 08
[03Eh 0062 1] Processor ID : 03
[03Fh 0063 1] Local Apic ID : 02
[040h 0064 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Runtime Online Capable : 0
[044h 0068 1] Subtable Type : 00 [Processor Local APIC]
[045h 0069 1] Length : 08
[046h 0070 1] Processor ID : 04
[047h 0071 1] Local Apic ID : 03
[048h 0072 4] Flags (decoded below) : 00000001
Processor Enabled : 1
Runtime Online Capable : 0
[04Ch 0076 1] Subtable Type : 00 [Processor Local APIC]
[04Dh 0077 1] Length : 08
[04Eh 0078 1] Processor ID : 05
[04Fh 0079 1] Local Apic ID : 84
[050h 0080 4] Flags (decoded below) : 00000000
Processor Enabled : 0
Runtime Online Capable : 0
[054h 0084 1] Subtable Type : 00 [Processor Local APIC]
[055h 0085 1] Length : 08
[056h 0086 1] Processor ID : 06
[057h 0087 1] Local Apic ID : 85
[058h 0088 4] Flags (decoded below) : 00000000
Processor Enabled : 0
Runtime Online Capable : 0
[05Ch 0092 1] Subtable Type : 01 [I/O APIC]
[05Dh 0093 1] Length : 0C
[05Eh 0094 1] I/O Apic ID : 04
[05Fh 0095 1] Reserved : 00
[060h 0096 4] Address : FEC00000
[064h 0100 4] Interrupt : 00000000
[068h 0104 1] Subtable Type : 02 [Interrupt Source Override]
[069h 0105 1] Length : 0A
[06Ah 0106 1] Bus : 00
[06Bh 0107 1] Source : 00
[06Ch 0108 4] Interrupt : 00000002
[070h 0112 2] Flags (decoded below) : 0000
Polarity : 0
Trigger Mode : 0
[072h 0114 1] Subtable Type : 02 [Interrupt Source Override]
[073h 0115 1] Length : 0A
[074h 0116 1] Bus : 00
[075h 0117 1] Source : 09
[076h 0118 4] Interrupt : 00000009
[07Ah 0122 2] Flags (decoded below) : 000F
Polarity : 3
Trigger Mode : 3
Raw Table Data: Length 124 (0x7C)
0000: 41 50 49 43 7C 00 00 00 01 F5 30 38 30 39 31 32 // APIC|.....080912
0010: 41 50 49 43 31 37 30 33 09 08 12 20 4D 53 46 54 // APIC1703... MSFT
0020: 97 00 00 00 00 00 E0 FE 01 00 00 00 00 08 01 00 // ................
0030: 01 00 00 00 00 08 02 01 01 00 00 00 00 08 03 02 // ................
0040: 01 00 00 00 00 08 04 03 01 00 00 00 00 08 05 84 // ................
0050: 00 00 00 00 00 08 06 85 00 00 00 00 01 0C 04 00 // ................
0060: 00 00 C0 FE 00 00 00 00 02 0A 00 00 02 00 00 00 // ................
0070: 00 00 02 0A 00 09 09 00 00 00 0F 00 // ............
next prev parent reply other threads:[~2025-10-23 16:32 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-07 22:28 [PATCH v3 00/12] AMD NB and SMN rework Yazen Ghannam
2025-01-07 22:28 ` [PATCH v3 01/12] x86/amd_nb: Restrict init function to AMD-based systems Yazen Ghannam
2025-01-07 22:28 ` [PATCH v3 02/12] x86/amd_nb: Clean up early_is_amd_nb() Yazen Ghannam
2025-01-07 22:28 ` [PATCH v3 03/12] x86: Start moving AMD node functionality out of AMD_NB Yazen Ghannam
2025-01-07 22:28 ` [PATCH v3 04/12] x86/amd_nb: Simplify function 4 search Yazen Ghannam
2025-01-07 22:28 ` [PATCH v3 05/12] x86/amd_nb: Simplify root device search Yazen Ghannam
2025-01-07 22:28 ` [PATCH v3 06/12] x86/amd_nb: Use topology info to get AMD node count Yazen Ghannam
2025-01-09 9:15 ` [tip: x86/misc] " tip-bot2 for Yazen Ghannam
2025-10-21 23:16 ` [PATCH v3 06/12] " Michal Pecio
2025-10-22 13:39 ` Yazen Ghannam
2025-10-22 15:38 ` Michal Pecio
2025-10-22 16:04 ` Guenter Roeck
2025-10-22 16:09 ` Yazen Ghannam
2025-10-22 16:18 ` Michal Pecio
2025-10-23 13:59 ` Yazen Ghannam
2025-10-23 15:01 ` Michal Pecio
2025-10-23 16:09 ` Yazen Ghannam
2025-10-23 16:22 ` Mario Limonciello
2025-10-23 17:06 ` Michal Pecio
2025-10-23 17:12 ` Mario Limonciello
2025-10-23 18:25 ` Yazen Ghannam
2025-10-23 21:43 ` Mario Limonciello
2025-10-23 16:31 ` Michal Pecio [this message]
2025-10-23 18:15 ` Yazen Ghannam
2025-10-23 18:25 ` Michal Pecio
2025-10-23 19:04 ` Yazen Ghannam
2025-10-23 19:09 ` Yazen Ghannam
2025-10-24 8:48 ` Michal Pecio
2025-10-24 13:42 ` Yazen Ghannam
2025-01-07 22:28 ` [PATCH v3 07/12] x86/amd_nb: Simplify function 3 search Yazen Ghannam
2025-01-09 9:15 ` [tip: x86/misc] " tip-bot2 for Yazen Ghannam
2025-01-07 22:28 ` [PATCH v3 08/12] x86/amd_nb, hwmon: (k10temp): Simplify amd_pci_dev_to_node_id() Yazen Ghannam
2025-01-07 22:28 ` [PATCH v3 09/12] x86/amd_nb: Move SMN access code to a new amd_node driver Yazen Ghannam
2025-01-08 5:30 ` Shyam Sundar S K
2025-01-08 8:56 ` Borislav Petkov
2025-01-07 22:28 ` [PATCH v3 10/12] x86/amd_node: Update __amd_smn_rw() error paths Yazen Ghannam
2025-01-07 22:28 ` [PATCH v3 11/12] x86/amd_node: Remove dependency on AMD_NB Yazen Ghannam
2025-01-07 22:28 ` [PATCH v3 12/12] x86/amd_node: Use defines for SMN register offsets Yazen Ghannam
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