From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC1842D249B; Thu, 30 Oct 2025 06:02:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761804124; cv=none; b=bmqLXmd/fZHK5MAbGU9FvXGc99+TiZ+soroBNk6lrpYL1YmbZFBaC+6Vns4Bwt7UBOSUryzG7wwzk+yJqIK9++PVgWY4j1i1gkAQzldfwXM22IgSSLlfMeY7NyhQzkSbiMiAhSCI0hTRxr+Lp0otDuePIn8lA183IlENWSk7Egw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761804124; c=relaxed/simple; bh=GRxMIlDn6SVB1IudUbhDRzYBuaV2Phtn4+2PyroXTf8=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; b=Ed+Wp9wfdI4fCXorV8eaS3nZu3+kMNzzipJzitcKFzkKkADvazQb/rQ49xE5iVw5HY//YzBmAWVR+/FPN1njM6z4vFbD7ZRSh7EjCN9BP52o0MPko2mBUREAyI4mOdbSwyP40JBzphQG93MOcWmbTPaDhiuYeJv6QKoc5bRmdcs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 30 Oct 2025 14:01:55 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 30 Oct 2025 14:01:55 +0800 From: Ryan Chen To: ryan_chen , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , , Kevin Chen , , , , Subject: [PATCH v6 0/1] Update correct AST2700 interrupt controller binding Date: Thu, 30 Oct 2025 14:01:54 +0800 Message-ID: <20251030060155.2342604-1-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Update the AST2700 interrupt controller binding to match the actual hardware and the irq-aspeed-intc driver behavior. v6: - aspeed,ast2700-intc.yaml update interrupt-cells, interrupts. v5: - Adds two new YAML bindings: - aspeed,ast2700-intc0.yaml - aspeed,ast2700-intc1.yaml - irq-aspeed-intc.c - add aspeed,ast2700-intc0-ic, aspeed,ast2700-intc0-ic compatible. v4: - aspeed,ast2700-intc.yaml - Clarify the relationship between INTC0/INTC1 parent nodes, the aspeed,ast2700-intc-ic child nodes, and the GIC. - Add a block diagram and DT examples showing the cascaded wiring (GIC <- INTC0 <- INTC1 children). - Mirrors the datasheet-described topology and register map, including the separation of INTC0/INTC1 regions. - Lets DT unambiguously express first-level (GIC parent) and cascaded second-level (INTC0 parent) interrupt controllers via examples that use `interrupts` for INTC0 children and `interrupts-extended` for INTC1 children routed into INTC0. - irq-ast2700-intc.c - Drop all string decoding and human readable tables. Debugfs now dumps raw routing/protection registers only. - Split into a separate source file and made it modular - If the compatible not match ast2700-intc0/1, bail out return -ENODEV. v3: - aspeed,ast2700-intc.yaml - Clarify the relationship between INTC0/INTC1 parent nodes, the aspeed,ast2700-intc-ic child nodes, and the GIC. - Add a block diagram and DT examples showing the cascaded wiring (GIC <- INTC0 <- INTC1 children). - Mirrors the datasheet-described topology and register map, including the separation of INTC0/INTC1 regions and their routing/protection registers. - Lets DT unambiguously express first-level (GIC parent) and cascaded second-level (INTC0 parent) interrupt controllers via examples that use `interrupts` for INTC0 children and `interrupts-extended` for INTC1 children routed into INTC0. - irq-aspeed-intc.c - separate c file from irq-aspeed-intc.c - make m v2: - fix dt bindingcheck Ryan Chen (1): dt-bindings: interrupt-controller: aspeed,ast2700: correct #interrupt-cells and interrupts count .../interrupt-controller/aspeed,ast2700-intc.yaml | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) -- 2.34.1