* [PATCH v2 00/13] Add RZ/G3E RSCI support
@ 2025-10-30 17:55 Biju
2025-10-30 17:55 ` [PATCH v2 01/13] dt-bindings: serial: renesas,rsci: Document RZ/G3E support Biju
` (13 more replies)
0 siblings, 14 replies; 19+ messages in thread
From: Biju @ 2025-10-30 17:55 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, Lad Prabhakar, linux-kernel, linux-serial, devicetree,
linux-renesas-soc, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Add RZ/G3E RSCI support for FIFO and non-FIFO mode. RSCI IP found on
RZ/G3E SoC is similar to one on RZ/T2H, but has 32-stage fifo. RZ/G3E has
6 clocks (5 module clocks + 1 external clock) compared to 3 clocks
(2 module clocks + 1 external clock) on RZ/T2H, and it has multiple
resets. Add support for the hardware flow control.
This patch series depend upon [1]
[1] https://lore.kernel.org/all/20251029082101.92156-1-biju.das.jz@bp.renesas.com/
v1->v2:
* Updated commit message for patch#1,#3,#9
* Added resets:false for non RZ/G3E SoCs in bindings.
* Increased line limit for error messages to 100-column limit for patch#3
* Updated multiline comment to fit into single line.
* Updated set_termios() for getting baud_rate()
Biju Das (13):
dt-bindings: serial: renesas,rsci: Document RZ/G3E support
serial: rsci: Drop rsci_clear_CFC()
serial: sh-sci: Drop extra lines
serial: rsci: Drop unused macro DCR
serial: rsci: Drop unused TDR register
serial: sh-sci: Use devm_reset_control_array_get_exclusive()
serial: sh-sci: Add RSCI_PORT_{SCI,SCIF} port IDs
serial: sh-sci: Add sci_is_rsci_type()
serial: sh-sci: Add support for RZ/G3E RSCI clks
serial: sh-sci: Make sci_scbrr_calc() public
serial: sh-sci: Add finish_console_write() callback
serial: sh-sci: Add support for RZ/G3E RSCI SCIF
serial: sh-sci: Add support for RZ/G3E RSCI SCI
.../bindings/serial/renesas,rsci.yaml | 85 +++-
drivers/tty/serial/rsci.c | 412 +++++++++++++++---
drivers/tty/serial/rsci.h | 2 +
drivers/tty/serial/sh-sci-common.h | 9 +
drivers/tty/serial/sh-sci.c | 67 ++-
5 files changed, 492 insertions(+), 83 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 01/13] dt-bindings: serial: renesas,rsci: Document RZ/G3E support
2025-10-30 17:55 [PATCH v2 00/13] Add RZ/G3E RSCI support Biju
@ 2025-10-30 17:55 ` Biju
2025-10-31 0:00 ` Rob Herring
2025-10-30 17:55 ` [PATCH v2 02/13] serial: rsci: Drop rsci_clear_CFC() Biju
` (12 subsequent siblings)
13 siblings, 1 reply; 19+ messages in thread
From: Biju @ 2025-10-30 17:55 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, Lad Prabhakar, linux-kernel, linux-serial, devicetree,
linux-renesas-soc, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Add documentation for the serial communication interface (RSCI) found on
the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC is identical
to that on the RZ/T2H (R9A09G077) SoC, but it has a 32-stage FIFO compared
to 16 on RZ/T2H. It supports both FIFO and non-FIFO mode operation. RZ/G3E
has 6 clocks(5 module clocks + 1 external clock) compared to 3 clocks
(2 module clocks + 1 external clock) on RZ/T2H, and it has multiple resets.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* Updated commit message
* Added resets:false for non RZ/G3E SoCs.
---
.../bindings/serial/renesas,rsci.yaml | 85 ++++++++++++++++---
1 file changed, 74 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
index 6b1f827a335b..1c2ed4cd58fd 100644
--- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
@@ -10,17 +10,16 @@ maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
-allOf:
- - $ref: serial.yaml#
-
properties:
compatible:
oneOf:
- - items:
- - const: renesas,r9a09g087-rsci # RZ/N2H
- - const: renesas,r9a09g077-rsci # RZ/T2H
+ - enum:
+ - renesas,r9a09g047-rsci # RZ/G3E non FIFO mode
+ - renesas,r9a09g047-rscif # RZ/G3E FIFO mode
+ - renesas,r9a09g077-rsci # RZ/T2H
- items:
+ - const: renesas,r9a09g087-rsci # RZ/N2H
- const: renesas,r9a09g077-rsci # RZ/T2H
reg:
@@ -42,14 +41,40 @@ properties:
clocks:
minItems: 2
- maxItems: 3
+ maxItems: 6
clock-names:
- minItems: 2
+ oneOf:
+ - items:
+ - const: operation
+ - const: bus
+ - items:
+ - const: operation
+ - const: bus
+ - const: sck # optional external clock input
+ - items:
+ - const: bus
+ - const: tclk
+ - const: tclk_div64
+ - const: tclk_div16
+ - const: tclk_div4
+ - items:
+ - const: bus
+ - const: tclk
+ - const: tclk_div64
+ - const: tclk_div16
+ - const: tclk_div4
+ - const: sck # optional external clock input
+
+ resets:
+ items:
+ - description: Input for resetting the APB clock
+ - description: Input for resetting TCLK
+
+ reset-names:
items:
- - const: operation
- - const: bus
- - const: sck # optional external clock input
+ - const: presetn
+ - const: tresetn
power-domains:
maxItems: 1
@@ -62,6 +87,44 @@ required:
- clock-names
- power-domains
+allOf:
+ - $ref: serial.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g077-rsci
+ then:
+ properties:
+ clocks:
+ maxItems: 3
+
+ clock-names:
+ maxItems: 3
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,r9a09g047-rsci
+ - renesas,r9a09g047-rscif
+ then:
+ properties:
+ clocks:
+ minItems: 5
+
+ clock-names:
+ minItems: 5
+
+ required:
+ - resets
+ - reset-names
+ else:
+ properties:
+ resets: false
+
unevaluatedProperties: false
examples:
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 02/13] serial: rsci: Drop rsci_clear_CFC()
2025-10-30 17:55 [PATCH v2 00/13] Add RZ/G3E RSCI support Biju
2025-10-30 17:55 ` [PATCH v2 01/13] dt-bindings: serial: renesas,rsci: Document RZ/G3E support Biju
@ 2025-10-30 17:55 ` Biju
2025-10-30 17:55 ` [PATCH v2 03/13] serial: sh-sci: Drop extra lines Biju
` (11 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Biju @ 2025-10-30 17:55 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: Biju Das, Wolfram Sang, Lad Prabhakar, Geert Uytterhoeven,
linux-kernel, linux-serial, Biju Das, linux-renesas-soc
From: Biju Das <biju.das.jz@bp.renesas.com>
Drop rsci_clear_CFC() by reusing rsci_clear_SCxSR() as the contents of
both functions are the same.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* No change.
---
drivers/tty/serial/rsci.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/tty/serial/rsci.c b/drivers/tty/serial/rsci.c
index 3e1f4b3c4e59..504361ed5ecc 100644
--- a/drivers/tty/serial/rsci.c
+++ b/drivers/tty/serial/rsci.c
@@ -199,11 +199,6 @@ static unsigned int rsci_get_mctrl(struct uart_port *port)
return 0;
}
-static void rsci_clear_CFC(struct uart_port *port, unsigned int mask)
-{
- rsci_serial_out(port, CFCLR, mask);
-}
-
static void rsci_start_tx(struct uart_port *port)
{
struct sci_port *sp = to_sci_port(port);
@@ -275,7 +270,7 @@ static void rsci_transmit_chars(struct uart_port *port)
break;
}
- rsci_clear_CFC(port, CFCLR_TDREC);
+ rsci_clear_SCxSR(port, CFCLR_TDREC);
rsci_serial_out(port, TDR, c);
port->icount.tx++;
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 03/13] serial: sh-sci: Drop extra lines
2025-10-30 17:55 [PATCH v2 00/13] Add RZ/G3E RSCI support Biju
2025-10-30 17:55 ` [PATCH v2 01/13] dt-bindings: serial: renesas,rsci: Document RZ/G3E support Biju
2025-10-30 17:55 ` [PATCH v2 02/13] serial: rsci: Drop rsci_clear_CFC() Biju
@ 2025-10-30 17:55 ` Biju
2025-10-30 17:55 ` [PATCH v2 04/13] serial: rsci: Drop unused macro DCR Biju
` (10 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Biju @ 2025-10-30 17:55 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: Biju Das, Wolfram Sang, Lad Prabhakar, Geert Uytterhoeven,
linux-kernel, linux-serial, Biju Das, linux-renesas-soc
From: Biju Das <biju.das.jz@bp.renesas.com>
Shorten the number lines in sci_init_clocks() by fitting the error
messages within an 100-character length limit.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* Updated commit message 80-character->100-character.
* Increased line limit for error messages to 100-column limit.
---
drivers/tty/serial/sh-sci.c | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index b33894d0273b..e9345f898224 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -3008,11 +3008,8 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
return PTR_ERR(clk);
if (!clk && sci_port->type == SCI_PORT_RSCI &&
- (i == SCI_FCK || i == SCI_BRG_INT)) {
- return dev_err_probe(dev, -ENODEV,
- "failed to get %s\n",
- name);
- }
+ (i == SCI_FCK || i == SCI_BRG_INT))
+ return dev_err_probe(dev, -ENODEV, "failed to get %s\n", name);
if (!clk && i == SCI_FCK) {
/*
@@ -3022,16 +3019,14 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
*/
clk = devm_clk_get(dev, "peripheral_clk");
if (IS_ERR(clk))
- return dev_err_probe(dev, PTR_ERR(clk),
- "failed to get %s\n",
+ return dev_err_probe(dev, PTR_ERR(clk), "failed to get %s\n",
name);
}
if (!clk)
dev_dbg(dev, "failed to get %s\n", name);
else
- dev_dbg(dev, "clk %s is %pC rate %lu\n", name,
- clk, clk_get_rate(clk));
+ dev_dbg(dev, "clk %s is %pC rate %lu\n", name, clk, clk_get_rate(clk));
sci_port->clks[i] = clk;
}
return 0;
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 04/13] serial: rsci: Drop unused macro DCR
2025-10-30 17:55 [PATCH v2 00/13] Add RZ/G3E RSCI support Biju
` (2 preceding siblings ...)
2025-10-30 17:55 ` [PATCH v2 03/13] serial: sh-sci: Drop extra lines Biju
@ 2025-10-30 17:55 ` Biju
2025-10-30 17:55 ` [PATCH v2 05/13] serial: rsci: Drop unused TDR register Biju
` (9 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Biju @ 2025-10-30 17:55 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: Biju Das, Wolfram Sang, Lad Prabhakar, Geert Uytterhoeven,
linux-kernel, linux-serial, Biju Das, linux-renesas-soc
From: Biju Das <biju.das.jz@bp.renesas.com>
Drop unused macro DCR and its bit definition.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* No change.
---
drivers/tty/serial/rsci.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/tty/serial/rsci.c b/drivers/tty/serial/rsci.c
index 504361ed5ecc..470b5701cd67 100644
--- a/drivers/tty/serial/rsci.c
+++ b/drivers/tty/serial/rsci.c
@@ -24,7 +24,6 @@ MODULE_IMPORT_NS("SH_SCI");
#define CCR3 0x14
#define CCR4 0x18
#define FCR 0x24
-#define DCR 0x30
#define CSR 0x48
#define FRSR 0x50
#define FTSR 0x54
@@ -119,8 +118,6 @@ MODULE_IMPORT_NS("SH_SCI");
/* FFCLR (FIFO Flag CLear Register) */
#define FFCLR_DRC BIT(0) /* DR Clear */
-#define DCR_DEPOL BIT(0)
-
static u32 rsci_serial_in(struct uart_port *p, int offset)
{
return readl(p->membase + offset);
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 05/13] serial: rsci: Drop unused TDR register
2025-10-30 17:55 [PATCH v2 00/13] Add RZ/G3E RSCI support Biju
` (3 preceding siblings ...)
2025-10-30 17:55 ` [PATCH v2 04/13] serial: rsci: Drop unused macro DCR Biju
@ 2025-10-30 17:55 ` Biju
2025-10-30 17:55 ` [PATCH v2 06/13] serial: sh-sci: Use devm_reset_control_array_get_exclusive() Biju
` (8 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Biju @ 2025-10-30 17:55 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: Biju Das, Wolfram Sang, Lad Prabhakar, Geert Uytterhoeven,
linux-kernel, linux-serial, Biju Das, linux-renesas-soc
From: Biju Das <biju.das.jz@bp.renesas.com>
Drop the unused TDR register-related macros.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* No change.
---
drivers/tty/serial/rsci.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/drivers/tty/serial/rsci.c b/drivers/tty/serial/rsci.c
index 470b5701cd67..ade5ee479e99 100644
--- a/drivers/tty/serial/rsci.c
+++ b/drivers/tty/serial/rsci.c
@@ -35,12 +35,6 @@ MODULE_IMPORT_NS("SH_SCI");
#define RDR_FPER BIT(11) /* FIFO Parity Error */
#define RDR_RDAT_MSK GENMASK(8, 0)
-/* TDR (Transmit Data Register) */
-#define TDR_MPBT BIT(9) /* Multiprocessor Transfer */
-#define TDR_TDAT_9BIT_LSHIFT 0
-#define TDR_TDAT_9BIT_VAL 0x1FF
-#define TDR_TDAT_9BIT_MSK (TDR_TDAT_9BIT_VAL << TDR_TDAT_9BIT_LSHIFT)
-
/* CCR0 (Common Control Register 0) */
#define CCR0_SSE BIT(24) /* SSn# Pin Function Enable */
#define CCR0_TEIE BIT(21) /* Transmit End Interrupt Enable */
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 06/13] serial: sh-sci: Use devm_reset_control_array_get_exclusive()
2025-10-30 17:55 [PATCH v2 00/13] Add RZ/G3E RSCI support Biju
` (4 preceding siblings ...)
2025-10-30 17:55 ` [PATCH v2 05/13] serial: rsci: Drop unused TDR register Biju
@ 2025-10-30 17:55 ` Biju
2025-10-30 17:55 ` [PATCH v2 07/13] serial: sh-sci: Add RSCI_PORT_{SCI,SCIF} port IDs Biju
` (7 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Biju @ 2025-10-30 17:55 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: Biju Das, Wolfram Sang, Lad Prabhakar, Geert Uytterhoeven,
linux-kernel, linux-serial, Biju Das, linux-renesas-soc
From: Biju Das <biju.das.jz@bp.renesas.com>
Replace devm_*_get_exclusive()->devm_*_array_get_exclusive() to support
existing SoCs along with RZ/G3E as RZ/G3E has 2 resets.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* No change.
---
drivers/tty/serial/sh-sci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index e9345f898224..d07424caeeab 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -3533,7 +3533,7 @@ static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
data = of_device_get_match_data(&pdev->dev);
- rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
+ rstc = devm_reset_control_array_get_optional_exclusive(&pdev->dev);
if (IS_ERR(rstc))
return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc),
"failed to get reset ctrl\n"));
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 07/13] serial: sh-sci: Add RSCI_PORT_{SCI,SCIF} port IDs
2025-10-30 17:55 [PATCH v2 00/13] Add RZ/G3E RSCI support Biju
` (5 preceding siblings ...)
2025-10-30 17:55 ` [PATCH v2 06/13] serial: sh-sci: Use devm_reset_control_array_get_exclusive() Biju
@ 2025-10-30 17:55 ` Biju
2025-10-30 17:55 ` [PATCH v2 08/13] serial: sh-sci: Add sci_is_rsci_type() Biju
` (6 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Biju @ 2025-10-30 17:55 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: Biju Das, Wolfram Sang, Lad Prabhakar, Geert Uytterhoeven,
linux-kernel, linux-serial, Biju Das, linux-renesas-soc
From: Biju Das <biju.das.jz@bp.renesas.com>
RZ/G3E RSCI tx/rx supports both FIFO and non-FIFO mode. It has 32-stage
FIFO. Add RSCI_PORT_SCI port ID for non-FIFO mode and RSCI_PORT_SCIF port
ID for FIFO mode. Update the rx_trigger for both these modes.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* No change.
---
drivers/tty/serial/sh-sci-common.h | 2 ++
drivers/tty/serial/sh-sci.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/drivers/tty/serial/sh-sci-common.h b/drivers/tty/serial/sh-sci-common.h
index bcdb41ddc15d..ef1d94ae8b5c 100644
--- a/drivers/tty/serial/sh-sci-common.h
+++ b/drivers/tty/serial/sh-sci-common.h
@@ -8,6 +8,8 @@
/* Private port IDs */
enum SCI_PORT_TYPE {
SCI_PORT_RSCI = BIT(7) | 0,
+ RSCI_PORT_SCI = BIT(7) | 1,
+ RSCI_PORT_SCIF = BIT(7) | 2,
};
enum SCI_CLKS {
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index d07424caeeab..6f396e1151d8 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -3149,6 +3149,9 @@ static int sci_init_single(struct platform_device *dev,
case SCI_PORT_RSCI:
sci_port->rx_trigger = 15;
break;
+ case RSCI_PORT_SCIF:
+ sci_port->rx_trigger = 32;
+ break;
default:
sci_port->rx_trigger = 1;
break;
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 08/13] serial: sh-sci: Add sci_is_rsci_type()
2025-10-30 17:55 [PATCH v2 00/13] Add RZ/G3E RSCI support Biju
` (6 preceding siblings ...)
2025-10-30 17:55 ` [PATCH v2 07/13] serial: sh-sci: Add RSCI_PORT_{SCI,SCIF} port IDs Biju
@ 2025-10-30 17:55 ` Biju
2025-10-30 17:55 ` [PATCH v2 09/13] serial: sh-sci: Add support for RZ/G3E RSCI clks Biju
` (5 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Biju @ 2025-10-30 17:55 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: Biju Das, Wolfram Sang, Lad Prabhakar, Geert Uytterhoeven,
linux-kernel, linux-serial, Biju Das, linux-renesas-soc
From: Biju Das <biju.das.jz@bp.renesas.com>
Add sci_is_rsci_type() for RSCI port type. This will simplify the code
when the support added for RSCI_PORT_{SCI,SCIF} private PORT type.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* No change.
---
drivers/tty/serial/sh-sci.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 6f396e1151d8..7cc2b622e270 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -1008,6 +1008,11 @@ static int sci_handle_errors(struct uart_port *port)
return copied;
}
+static bool sci_is_rsci_type(u8 type)
+{
+ return (type == SCI_PORT_RSCI || type == RSCI_PORT_SCI || type == RSCI_PORT_SCIF);
+}
+
static int sci_handle_fifo_overrun(struct uart_port *port)
{
struct tty_port *tport = &port->state->port;
@@ -1016,7 +1021,7 @@ static int sci_handle_fifo_overrun(struct uart_port *port)
int copied = 0;
u32 status;
- if (s->type != SCI_PORT_RSCI) {
+ if (!sci_is_rsci_type(s->type)) {
reg = sci_getreg(port, s->params->overrun_reg);
if (!reg->size)
return 0;
@@ -1024,7 +1029,7 @@ static int sci_handle_fifo_overrun(struct uart_port *port)
status = s->ops->read_reg(port, s->params->overrun_reg);
if (status & s->params->overrun_mask) {
- if (s->type == SCI_PORT_RSCI) {
+ if (sci_is_rsci_type(s->type)) {
s->ops->clear_SCxSR(port, s->params->param_bits->overrun_clr);
} else {
status &= ~s->params->overrun_mask;
@@ -1837,7 +1842,7 @@ static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr)
unsigned long flags;
u32 ctrl;
- if (s->type != PORT_SCI && s->type != SCI_PORT_RSCI)
+ if (s->type != PORT_SCI && !sci_is_rsci_type(s->type))
return sci_tx_interrupt(irq, ptr);
uart_port_lock_irqsave(port, &flags);
@@ -3112,7 +3117,7 @@ static int sci_init_single(struct platform_device *dev,
* The fourth interrupt on SCI and RSCI port is transmit end interrupt, so
* shuffle the interrupts.
*/
- if (p->type == PORT_SCI || p->type == SCI_PORT_RSCI)
+ if (p->type == PORT_SCI || sci_is_rsci_type(p->type))
swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]);
/* The SCI generates several interrupts. They can be muxed together or
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 09/13] serial: sh-sci: Add support for RZ/G3E RSCI clks
2025-10-30 17:55 [PATCH v2 00/13] Add RZ/G3E RSCI support Biju
` (7 preceding siblings ...)
2025-10-30 17:55 ` [PATCH v2 08/13] serial: sh-sci: Add sci_is_rsci_type() Biju
@ 2025-10-30 17:55 ` Biju
2025-10-30 17:55 ` [PATCH v2 10/13] serial: sh-sci: Make sci_scbrr_calc() public Biju
` (4 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Biju @ 2025-10-30 17:55 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: Biju Das, Wolfram Sang, Lad Prabhakar, Geert Uytterhoeven,
linux-kernel, linux-serial, Biju Das, linux-renesas-soc
From: Biju Das <biju.das.jz@bp.renesas.com>
RZ/G3E RSCI has 6 clocks (5 module clocks + 1 external clock). Add
support for the module clocks.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* Updated commit description.
---
drivers/tty/serial/sh-sci-common.h | 3 +++
drivers/tty/serial/sh-sci.c | 12 ++++++++++++
2 files changed, 15 insertions(+)
diff --git a/drivers/tty/serial/sh-sci-common.h b/drivers/tty/serial/sh-sci-common.h
index ef1d94ae8b5c..f730ff9add60 100644
--- a/drivers/tty/serial/sh-sci-common.h
+++ b/drivers/tty/serial/sh-sci-common.h
@@ -17,6 +17,9 @@ enum SCI_CLKS {
SCI_SCK, /* Optional External Clock */
SCI_BRG_INT, /* Optional BRG Internal Clock Source */
SCI_SCIF_CLK, /* Optional BRG External Clock Source */
+ SCI_FCK_DIV64, /* Optional Functional Clock frequency-divided by 64 */
+ SCI_FCK_DIV16, /* Optional Functional Clock frequency-divided by 16 */
+ SCI_FCK_DIV4, /* Optional Functional Clock frequency-divided by 4 */
SCI_NUM_CLKS
};
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 7cc2b622e270..67eba7feea9f 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -2994,6 +2994,9 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
[SCI_SCK] = "sck",
[SCI_BRG_INT] = "brg_int",
[SCI_SCIF_CLK] = "scif_clk",
+ [SCI_FCK_DIV64] = "tclk_div64",
+ [SCI_FCK_DIV16] = "tclk_div16",
+ [SCI_FCK_DIV4] = "tclk_div4",
};
struct clk *clk;
unsigned int i;
@@ -3003,6 +3006,9 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
} else if (sci_port->type == SCI_PORT_RSCI) {
clk_names[SCI_FCK] = "operation";
clk_names[SCI_BRG_INT] = "bus";
+ } else if (sci_port->type == RSCI_PORT_SCI || sci_port->type == RSCI_PORT_SCIF) {
+ clk_names[SCI_FCK] = "tclk";
+ clk_names[SCI_BRG_INT] = "bus";
}
for (i = 0; i < SCI_NUM_CLKS; i++) {
@@ -3016,6 +3022,12 @@ static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
(i == SCI_FCK || i == SCI_BRG_INT))
return dev_err_probe(dev, -ENODEV, "failed to get %s\n", name);
+ if (!clk && (sci_port->type == RSCI_PORT_SCI ||
+ sci_port->type == RSCI_PORT_SCIF) &&
+ (i == SCI_FCK || i == SCI_BRG_INT || i == SCI_FCK_DIV64 ||
+ i == SCI_FCK_DIV16 || i == SCI_FCK_DIV4))
+ return dev_err_probe(dev, -ENODEV, "failed to get %s\n", name);
+
if (!clk && i == SCI_FCK) {
/*
* Not all SH platforms declare a clock lookup entry
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 10/13] serial: sh-sci: Make sci_scbrr_calc() public
2025-10-30 17:55 [PATCH v2 00/13] Add RZ/G3E RSCI support Biju
` (8 preceding siblings ...)
2025-10-30 17:55 ` [PATCH v2 09/13] serial: sh-sci: Add support for RZ/G3E RSCI clks Biju
@ 2025-10-30 17:55 ` Biju
2025-10-30 17:55 ` [PATCH v2 11/13] serial: sh-sci: Add finish_console_write() callback Biju
` (3 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Biju @ 2025-10-30 17:55 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: Biju Das, Wolfram Sang, Lad Prabhakar, Geert Uytterhoeven,
linux-kernel, linux-serial, Biju Das, linux-renesas-soc
From: Biju Das <biju.das.jz@bp.renesas.com>
Make the function sci_scbrr_calc() public for code reuse to support RZ/G3E
RSCI IP.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* No change.
---
drivers/tty/serial/sh-sci-common.h | 3 +++
drivers/tty/serial/sh-sci.c | 6 +++---
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/tty/serial/sh-sci-common.h b/drivers/tty/serial/sh-sci-common.h
index f730ff9add60..a3f4a76cdecb 100644
--- a/drivers/tty/serial/sh-sci-common.h
+++ b/drivers/tty/serial/sh-sci-common.h
@@ -171,6 +171,9 @@ void sci_port_enable(struct sci_port *sci_port);
int sci_startup(struct uart_port *port);
void sci_shutdown(struct uart_port *port);
+int sci_scbrr_calc(struct sci_port *s, unsigned int bps, unsigned int *brr,
+ unsigned int *srr, unsigned int *cks);
+
#define min_sr(_port) ffs((_port)->sampling_rate_mask)
#define max_sr(_port) fls((_port)->sampling_rate_mask)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 67eba7feea9f..ca4915c1e2e6 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -2395,9 +2395,8 @@ static int sci_brg_calc(struct sci_port *s, unsigned int bps,
}
/* calculate sample rate, BRR, and clock select */
-static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
- unsigned int *brr, unsigned int *srr,
- unsigned int *cks)
+int sci_scbrr_calc(struct sci_port *s, unsigned int bps, unsigned int *brr,
+ unsigned int *srr, unsigned int *cks)
{
unsigned long freq = s->clk_rates[SCI_FCK];
unsigned int sr, br, prediv, scrate, c;
@@ -2461,6 +2460,7 @@ static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
min_err, *brr, *srr + 1, *cks);
return min_err;
}
+EXPORT_SYMBOL_NS_GPL(sci_scbrr_calc, "SH_SCI");
static void sci_reset(struct uart_port *port)
{
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 11/13] serial: sh-sci: Add finish_console_write() callback
2025-10-30 17:55 [PATCH v2 00/13] Add RZ/G3E RSCI support Biju
` (9 preceding siblings ...)
2025-10-30 17:55 ` [PATCH v2 10/13] serial: sh-sci: Make sci_scbrr_calc() public Biju
@ 2025-10-30 17:55 ` Biju
2025-10-30 17:55 ` [PATCH v2 12/13] serial: sh-sci: Add support for RZ/G3E RSCI SCIF Biju
` (2 subsequent siblings)
13 siblings, 0 replies; 19+ messages in thread
From: Biju @ 2025-10-30 17:55 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: Biju Das, Wolfram Sang, Lad Prabhakar, Geert Uytterhoeven,
linux-kernel, linux-serial, Biju Das, linux-renesas-soc
From: Biju Das <biju.das.jz@bp.renesas.com>
Add finish_console_write() callback as RZ/G3E RSCI IP needs special
handling compared to other SoCs.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* No change.
---
drivers/tty/serial/sh-sci-common.h | 1 +
drivers/tty/serial/sh-sci.c | 5 ++++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/sh-sci-common.h b/drivers/tty/serial/sh-sci-common.h
index a3f4a76cdecb..2e97aad390d9 100644
--- a/drivers/tty/serial/sh-sci-common.h
+++ b/drivers/tty/serial/sh-sci-common.h
@@ -95,6 +95,7 @@ struct sci_port_ops {
void (*shutdown_complete)(struct uart_port *port);
void (*prepare_console_write)(struct uart_port *port, u32 ctrl);
+ void (*finish_console_write)(struct uart_port *port, u32 ctrl);
void (*console_save)(struct uart_port *port);
void (*console_restore)(struct uart_port *port);
size_t (*suspend_regs_size)(void);
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index ca4915c1e2e6..fac83dace27c 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -3259,7 +3259,10 @@ static void serial_console_write(struct console *co, const char *s,
cpu_relax();
/* restore the SCSCR */
- sci_port->ops->write_reg(port, regs->control, ctrl);
+ if (sci_port->ops->finish_console_write)
+ sci_port->ops->finish_console_write(port, ctrl);
+ else
+ sci_port->ops->write_reg(port, regs->control, ctrl);
if (locked)
uart_port_unlock_irqrestore(port, flags);
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 12/13] serial: sh-sci: Add support for RZ/G3E RSCI SCIF
2025-10-30 17:55 [PATCH v2 00/13] Add RZ/G3E RSCI support Biju
` (10 preceding siblings ...)
2025-10-30 17:55 ` [PATCH v2 11/13] serial: sh-sci: Add finish_console_write() callback Biju
@ 2025-10-30 17:55 ` Biju
2025-10-30 17:55 ` [PATCH v2 13/13] serial: sh-sci: Add support for RZ/G3E RSCI SCI Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Jiri Slaby <jirislaby@kernel.org> Biju
2025-10-30 17:59 ` [PATCH v2 00/13] Add RZ/G3E RSCI support Biju Das
13 siblings, 0 replies; 19+ messages in thread
From: Biju @ 2025-10-30 17:55 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby
Cc: Biju Das, Wolfram Sang, Lad Prabhakar, Geert Uytterhoeven,
linux-kernel, linux-serial, Biju Das, linux-renesas-soc
From: Biju Das <biju.das.jz@bp.renesas.com>
Add support for RZ/G3E RSCI SCIF(a.k.a FIFO mode). RSCI IP found on the
RZ/G3E SoC is similar to RZ/T2H, but it has a 32-stage FIFO. it has 6
clocks(5 module clocks + 1 external clock) instead of 3 clocks(2 module
clocks + 1 external clock) on T2H and has multiple resets. Add support
for the hardware flow control.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* Updated commit description.
* Updated multiline comment to fit into single line.
* Updated set_termios() for getting baud_rate()
---
drivers/tty/serial/rsci.c | 282 ++++++++++++++++++++++++++++++++++--
drivers/tty/serial/rsci.h | 1 +
drivers/tty/serial/sh-sci.c | 9 +-
3 files changed, 281 insertions(+), 11 deletions(-)
diff --git a/drivers/tty/serial/rsci.c b/drivers/tty/serial/rsci.c
index ade5ee479e99..a3e216c05b76 100644
--- a/drivers/tty/serial/rsci.c
+++ b/drivers/tty/serial/rsci.c
@@ -11,6 +11,8 @@
#include <linux/serial_core.h>
#include <linux/serial_sci.h>
#include <linux/tty_flip.h>
+
+#include "serial_mctrl_gpio.h"
#include "rsci.h"
MODULE_IMPORT_NS("SH_SCI");
@@ -59,6 +61,41 @@ MODULE_IMPORT_NS("SH_SCI");
#define CCR1_CTSPEN BIT(1) /* CTS External Pin Enable */
#define CCR1_CTSE BIT(0) /* CTS Enable */
+/* CCR2 (Common Control Register 2) */
+#define CCR2_INIT 0xFF000004
+#define CCR2_CKS_TCLK (0) /* TCLK clock */
+#define CCR2_CKS_TCLK_DIV4 BIT(20) /* TCLK/4 clock */
+#define CCR2_CKS_TCLK_DIV16 BIT(21) /* TCLK16 clock */
+#define CCR2_CKS_TCLK_DIV64 (BIT(21) | BIT(20)) /* TCLK/64 clock */
+#define CCR2_BRME BIT(16) /* Bitrate Modulation Enable */
+#define CCR2_ABCSE BIT(6) /* Asynchronous Mode Extended Base Clock Select */
+#define CCR2_ABCS BIT(5) /* Asynchronous Mode Base Clock Select */
+#define CCR2_BGDM BIT(4) /* Baud Rate Generator Double-Speed Mode Select */
+
+/* CCR3 (Common Control Register 3) */
+#define CCR3_INIT 0x1203
+#define CCR3_BLK BIT(29) /* Block Transfer Mode */
+#define CCR3_GM BIT(28) /* GSM Mode */
+#define CCR3_CKE1 BIT(25) /* Clock Enable 1 */
+#define CCR3_CKE0 BIT(24) /* Clock Enable 0 */
+#define CCR3_DEN BIT(21) /* Driver Enabled */
+#define CCR3_FM BIT(20) /* FIFO Mode Select */
+#define CCR3_MP BIT(19) /* Multi-Processor Mode */
+#define CCR3_MOD_ASYNC 0 /* Asynchronous mode (Multi-processor mode) */
+#define CCR3_MOD_IRDA BIT(16) /* Smart card interface mode */
+#define CCR3_MOD_CLK_SYNC BIT(17) /* Clock synchronous mode */
+#define CCR3_MOD_SPI (BIT(17) | BIT(16)) /* Simple SPI mode */
+#define CCR3_MOD_I2C BIT(18) /* Simple I2C mode */
+#define CCR3_RXDESEL BIT(15) /* Asynchronous Start Bit Edge Detection Select */
+#define CCR3_STP BIT(14) /* Stop bit Length */
+#define CCR3_SINV BIT(13) /* Transmitted/Received Data Invert */
+#define CCR3_LSBF BIT(12) /* LSB First select */
+#define CCR3_CHR1 BIT(9) /* Character Length */
+#define CCR3_CHR0 BIT(8) /* Character Length */
+#define CCR3_BPEN BIT(7) /* Synchronizer Bypass Enable */
+#define CCR3_CPOL BIT(1) /* Clock Polarity Select */
+#define CCR3_CPHA BIT(0) /* Clock Phase Select */
+
/* FCR (FIFO Control Register) */
#define FCR_RFRST BIT(23) /* Receive FIFO Data Register Reset */
#define FCR_TFRST BIT(15) /* Transmit FIFO Data Register Reset */
@@ -142,21 +179,160 @@ static void rsci_start_rx(struct uart_port *port)
rsci_serial_out(port, CCR0, ctrl);
}
+static void rsci_enable_ms(struct uart_port *port)
+{
+ mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
+}
+
+static void rsci_init_pins(struct uart_port *port, unsigned int cflag)
+{
+ struct sci_port *s = to_sci_port(port);
+
+ /* Use port-specific handler if provided */
+ if (s->cfg->ops && s->cfg->ops->init_pins) {
+ s->cfg->ops->init_pins(port, cflag);
+ return;
+ }
+
+ if (!s->has_rtscts)
+ return;
+
+ if (s->autorts)
+ rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) |
+ CCR1_CTSE | CCR1_CTSPEN);
+}
+
+static int rsci_scif_set_rtrg(struct uart_port *port, int rx_trig)
+{
+ unsigned int bits;
+
+ if (rx_trig >= port->fifosize)
+ rx_trig = port->fifosize - 1;
+ else if (rx_trig < 1)
+ rx_trig = 1;
+
+ bits = rx_trig << 16;
+ rsci_serial_out(port, FCR, (rsci_serial_in(port, FCR) & ~FCR_RTRG4_0) | bits);
+
+ return rx_trig;
+}
+
static void rsci_set_termios(struct uart_port *port, struct ktermios *termios,
const struct ktermios *old)
{
+ unsigned int ccr2_val = CCR2_INIT, ccr3_val = CCR3_INIT;
+ unsigned int ccr0_val = 0, ccr1_val = 0, ccr4_val = 0;
+ unsigned int brr1 = 255, cks1 = 0, srr1 = 15;
struct sci_port *s = to_sci_port(port);
+ unsigned int brr = 255, cks = 0;
+ int min_err = INT_MAX, err;
+ unsigned long max_freq = 0;
+ unsigned int baud, i;
unsigned long flags;
+ unsigned int ctrl;
+ int best_clk = -1;
+
+ if ((termios->c_cflag & CSIZE) == CS7) {
+ ccr3_val |= CCR3_CHR0;
+ } else {
+ termios->c_cflag &= ~CSIZE;
+ termios->c_cflag |= CS8;
+ }
+
+ if (termios->c_cflag & PARENB)
+ ccr1_val |= CCR1_PE;
+
+ if (termios->c_cflag & PARODD)
+ ccr1_val |= (CCR1_PE | CCR1_PM);
+
+ if (termios->c_cflag & CSTOPB)
+ ccr3_val |= CCR3_STP;
+
+ /* Enable noise filter function */
+ ccr1_val |= CCR1_NFEN;
+
+ /*
+ * earlyprintk comes here early on with port->uartclk set to zero.
+ * the clock framework is not up and running at this point so here
+ * we assume that 115200 is the maximum baud rate. please note that
+ * the baud rate is not programmed during earlyprintk - it is assumed
+ * that the previous boot loader has enabled required clocks and
+ * setup the baud rate generator hardware for us already.
+ */
+ if (!port->uartclk) {
+ max_freq = 115200;
+ } else {
+ for (i = 0; i < SCI_NUM_CLKS; i++)
+ max_freq = max(max_freq, s->clk_rates[i]);
+
+ max_freq /= min_sr(s);
+ }
+
+ baud = uart_get_baud_rate(port, termios, old, 0, max_freq);
+ if (!baud)
+ goto done;
+
+ /* Divided Functional Clock using standard Bit Rate Register */
+ err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
+ if (abs(err) < abs(min_err)) {
+ best_clk = SCI_FCK;
+ ccr0_val = 0;
+ min_err = err;
+ brr = brr1;
+ cks = cks1;
+ }
+
+done:
+ if (best_clk >= 0)
+ dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
+ s->clks[best_clk], baud, min_err);
sci_port_enable(s);
uart_port_lock_irqsave(port, &flags);
- /* For now, only RX enabling is supported */
- if (termios->c_cflag & CREAD)
+ uart_update_timeout(port, termios->c_cflag, baud);
+
+ rsci_serial_out(port, CCR0, ccr0_val);
+
+ ccr3_val |= CCR3_FM;
+ rsci_serial_out(port, CCR3, ccr3_val);
+
+ ccr2_val |= (cks << 20) | (brr << 8);
+ rsci_serial_out(port, CCR2, ccr2_val);
+
+ rsci_serial_out(port, CCR1, ccr1_val);
+ rsci_serial_out(port, CCR4, ccr4_val);
+
+ ctrl = rsci_serial_in(port, FCR);
+ ctrl |= (FCR_RFRST | FCR_TFRST);
+ rsci_serial_out(port, FCR, ctrl);
+
+ if (s->rx_trigger > 1)
+ rsci_scif_set_rtrg(port, s->rx_trigger);
+
+ port->status &= ~UPSTAT_AUTOCTS;
+ s->autorts = false;
+
+ if ((port->flags & UPF_HARD_FLOW) && (termios->c_cflag & CRTSCTS)) {
+ port->status |= UPSTAT_AUTOCTS;
+ s->autorts = true;
+ }
+
+ rsci_init_pins(port, termios->c_cflag);
+ rsci_serial_out(port, CFCLR, CFCLR_CLRFLAG);
+ rsci_serial_out(port, FFCLR, FFCLR_DRC);
+
+ ccr0_val |= CCR0_RE;
+ rsci_serial_out(port, CCR0, ccr0_val);
+
+ if ((termios->c_cflag & CREAD) != 0)
rsci_start_rx(port);
uart_port_unlock_irqrestore(port, flags);
sci_port_disable(s);
+
+ if (UART_ENABLE_MS(port, termios->c_cflag))
+ rsci_enable_ms(port);
}
static int rsci_txfill(struct uart_port *port)
@@ -181,13 +357,34 @@ static unsigned int rsci_tx_empty(struct uart_port *port)
static void rsci_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
- /* Not supported yet */
+ if (mctrl & TIOCM_LOOP) {
+ /* Standard loopback mode */
+ rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) | CCR1_SPLP);
+ }
}
static unsigned int rsci_get_mctrl(struct uart_port *port)
{
- /* Not supported yet */
- return 0;
+ struct sci_port *s = to_sci_port(port);
+ struct mctrl_gpios *gpios = s->gpios;
+ unsigned int mctrl = 0;
+
+ mctrl_gpio_get(gpios, &mctrl);
+
+ /*
+ * CTS/RTS is handled in hardware when supported, while nothing
+ * else is wired up.
+ */
+ if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))
+ mctrl |= TIOCM_CTS;
+
+ if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
+ mctrl |= TIOCM_DSR;
+
+ if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
+ mctrl |= TIOCM_CAR;
+
+ return mctrl;
}
static void rsci_start_tx(struct uart_port *port)
@@ -312,7 +509,8 @@ static void rsci_receive_chars(struct uart_port *port)
continue;
}
- /* Store data and status.
+ /*
+ * Store data and status.
* Non FIFO mode is not supported
*/
if (rdat & RDR_FFER) {
@@ -346,6 +544,28 @@ static void rsci_receive_chars(struct uart_port *port)
}
}
+static void rsci_break_ctl(struct uart_port *port, int break_state)
+{
+ unsigned short ccr0_val, ccr1_val;
+ unsigned long flags;
+
+ uart_port_lock_irqsave(port, &flags);
+ ccr1_val = rsci_serial_in(port, CCR1);
+ ccr0_val = rsci_serial_in(port, CCR0);
+
+ if (break_state == -1) {
+ ccr1_val = (ccr1_val | CCR1_SPB2IO) & ~CCR1_SPB2DT;
+ ccr0_val &= ~CCR0_TE;
+ } else {
+ ccr1_val = (ccr1_val | CCR1_SPB2DT) & ~CCR1_SPB2IO;
+ ccr0_val |= CCR0_TE;
+ }
+
+ rsci_serial_out(port, CCR1, ccr1_val);
+ rsci_serial_out(port, CCR0, ccr0_val);
+ uart_port_unlock_irqrestore(port, flags);
+}
+
static void rsci_poll_put_char(struct uart_port *port, unsigned char c)
{
u32 status;
@@ -367,14 +587,30 @@ static void rsci_poll_put_char(struct uart_port *port, unsigned char c)
static void rsci_prepare_console_write(struct uart_port *port, u32 ctrl)
{
struct sci_port *s = to_sci_port(port);
- u32 ctrl_temp =
- s->params->param_bits->rxtx_enable | CCR0_TIE |
- s->hscif_tot;
+ u32 ctrl_temp = s->params->param_bits->rxtx_enable;
+
+ if (s->type == SCI_PORT_RSCI)
+ ctrl_temp |= CCR0_TIE | s->hscif_tot;
+
rsci_serial_out(port, CCR0, ctrl_temp);
}
+static void rsci_finish_console_write(struct uart_port *port, u32 ctrl)
+{
+ rsci_serial_out(port, CCR0, ctrl & ~CCR0_TE);
+ cpu_relax();
+ rsci_serial_out(port, CCR0, ctrl);
+}
+
static const char *rsci_type(struct uart_port *port)
{
+ struct sci_port *s = to_sci_port(port);
+
+ switch (s->type) {
+ case RSCI_PORT_SCIF:
+ return "scif";
+ }
+
return "rsci";
}
@@ -414,6 +650,17 @@ static const struct sci_port_params rsci_port_params = {
.common_regs = &rsci_common_regs,
};
+static const struct sci_port_params rsci_rzg3e_scif_port_params = {
+ .fifosize = 32,
+ .overrun_reg = CSR,
+ .overrun_mask = CSR_ORER,
+ .sampling_rate_mask = SCI_SR(32),
+ .error_mask = RSCI_DEFAULT_ERROR_MASK,
+ .error_clear = RSCI_ERROR_CLEAR,
+ .param_bits = &rsci_port_param_bits,
+ .common_regs = &rsci_common_regs,
+};
+
static const struct uart_ops rsci_uart_ops = {
.tx_empty = rsci_tx_empty,
.set_mctrl = rsci_set_mctrl,
@@ -421,6 +668,8 @@ static const struct uart_ops rsci_uart_ops = {
.start_tx = rsci_start_tx,
.stop_tx = rsci_stop_tx,
.stop_rx = rsci_stop_rx,
+ .enable_ms = rsci_enable_ms,
+ .break_ctl = rsci_break_ctl,
.startup = sci_startup,
.shutdown = sci_shutdown,
.set_termios = rsci_set_termios,
@@ -440,6 +689,7 @@ static const struct sci_port_ops rsci_port_ops = {
.receive_chars = rsci_receive_chars,
.poll_put_char = rsci_poll_put_char,
.prepare_console_write = rsci_prepare_console_write,
+ .finish_console_write = rsci_finish_console_write,
.suspend_regs_size = rsci_suspend_regs_size,
.shutdown_complete = rsci_shutdown_complete,
};
@@ -451,6 +701,13 @@ struct sci_of_data of_sci_rsci_data = {
.params = &rsci_port_params,
};
+struct sci_of_data of_rsci_scif_data = {
+ .type = RSCI_PORT_SCIF,
+ .ops = &rsci_port_ops,
+ .uart_ops = &rsci_uart_ops,
+ .params = &rsci_rzg3e_scif_port_params,
+};
+
#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
static int __init rsci_early_console_setup(struct earlycon_device *device,
@@ -459,6 +716,13 @@ static int __init rsci_early_console_setup(struct earlycon_device *device,
return scix_early_console_setup(device, &of_sci_rsci_data);
}
+static int __init rsci_rzg3e_scif_early_console_setup(struct earlycon_device *device,
+ const char *opt)
+{
+ return scix_early_console_setup(device, &of_rsci_scif_data);
+}
+
+OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g047-rscif", rsci_rzg3e_scif_early_console_setup);
OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g077-rsci", rsci_early_console_setup);
#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
diff --git a/drivers/tty/serial/rsci.h b/drivers/tty/serial/rsci.h
index 2af3f28b465a..ba255f58c088 100644
--- a/drivers/tty/serial/rsci.h
+++ b/drivers/tty/serial/rsci.h
@@ -6,5 +6,6 @@
#include "sh-sci-common.h"
extern struct sci_of_data of_sci_rsci_data;
+extern struct sci_of_data of_rsci_scif_data;
#endif /* __RSCI_H__ */
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index fac83dace27c..85b89c1ebf15 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -3397,7 +3397,7 @@ static void sci_remove(struct platform_device *dev)
if (s->port.fifosize > 1)
device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF ||
- type == SCI_PORT_RSCI)
+ type == SCI_PORT_RSCI || type == RSCI_PORT_SCIF)
device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
}
@@ -3492,6 +3492,10 @@ static const struct of_device_id of_sci_match[] __maybe_unused = {
.data = &of_sci_scif_rzv2h,
},
#ifdef CONFIG_SERIAL_RSCI
+ {
+ .compatible = "renesas,r9a09g047-rscif",
+ .data = &of_rsci_scif_data,
+ },
{
.compatible = "renesas,r9a09g077-rsci",
.data = &of_sci_rsci_data,
@@ -3759,7 +3763,8 @@ static int sci_probe(struct platform_device *dev)
return ret;
}
if (sp->type == PORT_SCIFA || sp->type == PORT_SCIFB ||
- sp->type == PORT_HSCIF || sp->type == SCI_PORT_RSCI) {
+ sp->type == PORT_HSCIF || sp->type == SCI_PORT_RSCI ||
+ sp->type == RSCI_PORT_SCIF) {
ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
if (ret) {
if (sp->port.fifosize > 1) {
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 13/13] serial: sh-sci: Add support for RZ/G3E RSCI SCI Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Jiri Slaby <jirislaby@kernel.org>
2025-10-30 17:55 [PATCH v2 00/13] Add RZ/G3E RSCI support Biju
` (11 preceding siblings ...)
2025-10-30 17:55 ` [PATCH v2 12/13] serial: sh-sci: Add support for RZ/G3E RSCI SCIF Biju
@ 2025-10-30 17:55 ` Biju
2025-10-30 17:59 ` [PATCH v2 00/13] Add RZ/G3E RSCI support Biju Das
13 siblings, 0 replies; 19+ messages in thread
From: Biju @ 2025-10-30 17:55 UTC (permalink / raw)
Cc: Biju Das, Wolfram Sang, Lad Prabhakar, Geert Uytterhoeven,
linux-kernel, linux-serial, Biju Das, linux-renesas-soc
From: Biju Das <biju.das.jz@bp.renesas.com>
Add support for RZ/G3E RSCI SCI(a.k.a non FIFO mode).
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* No change.
---
drivers/tty/serial/rsci.c | 138 +++++++++++++++++++++++++-----------
drivers/tty/serial/rsci.h | 1 +
drivers/tty/serial/sh-sci.c | 4 ++
3 files changed, 103 insertions(+), 40 deletions(-)
diff --git a/drivers/tty/serial/rsci.c b/drivers/tty/serial/rsci.c
index a3e216c05b76..43a381e5eace 100644
--- a/drivers/tty/serial/rsci.c
+++ b/drivers/tty/serial/rsci.c
@@ -161,8 +161,11 @@ static void rsci_serial_out(struct uart_port *p, int offset, int value)
static void rsci_clear_DRxC(struct uart_port *port)
{
+ struct sci_port *s = to_sci_port(port);
+
rsci_serial_out(port, CFCLR, CFCLR_RDRFC);
- rsci_serial_out(port, FFCLR, FFCLR_DRC);
+ if (s->type != RSCI_PORT_SCI)
+ rsci_serial_out(port, FFCLR, FFCLR_DRC);
}
static void rsci_clear_SCxSR(struct uart_port *port, unsigned int mask)
@@ -229,7 +232,6 @@ static void rsci_set_termios(struct uart_port *port, struct ktermios *termios,
unsigned long max_freq = 0;
unsigned int baud, i;
unsigned long flags;
- unsigned int ctrl;
int best_clk = -1;
if ((termios->c_cflag & CSIZE) == CS7) {
@@ -294,7 +296,11 @@ static void rsci_set_termios(struct uart_port *port, struct ktermios *termios,
rsci_serial_out(port, CCR0, ccr0_val);
- ccr3_val |= CCR3_FM;
+ if (s->type == RSCI_PORT_SCI)
+ ccr3_val |= CCR3_RXDESEL;
+ else
+ ccr3_val |= CCR3_FM;
+
rsci_serial_out(port, CCR3, ccr3_val);
ccr2_val |= (cks << 20) | (brr << 8);
@@ -303,12 +309,16 @@ static void rsci_set_termios(struct uart_port *port, struct ktermios *termios,
rsci_serial_out(port, CCR1, ccr1_val);
rsci_serial_out(port, CCR4, ccr4_val);
- ctrl = rsci_serial_in(port, FCR);
- ctrl |= (FCR_RFRST | FCR_TFRST);
- rsci_serial_out(port, FCR, ctrl);
+ if (s->type != RSCI_PORT_SCI) {
+ unsigned int ctrl;
- if (s->rx_trigger > 1)
- rsci_scif_set_rtrg(port, s->rx_trigger);
+ ctrl = rsci_serial_in(port, FCR);
+ ctrl |= (FCR_RFRST | FCR_TFRST);
+ rsci_serial_out(port, FCR, ctrl);
+
+ if (s->rx_trigger > 1)
+ rsci_scif_set_rtrg(port, s->rx_trigger);
+ }
port->status &= ~UPSTAT_AUTOCTS;
s->autorts = false;
@@ -320,7 +330,8 @@ static void rsci_set_termios(struct uart_port *port, struct ktermios *termios,
rsci_init_pins(port, termios->c_cflag);
rsci_serial_out(port, CFCLR, CFCLR_CLRFLAG);
- rsci_serial_out(port, FFCLR, FFCLR_DRC);
+ if (s->type != RSCI_PORT_SCI)
+ rsci_serial_out(port, FFCLR, FFCLR_DRC);
ccr0_val |= CCR0_RE;
rsci_serial_out(port, CCR0, ccr0_val);
@@ -337,12 +348,23 @@ static void rsci_set_termios(struct uart_port *port, struct ktermios *termios,
static int rsci_txfill(struct uart_port *port)
{
- return rsci_serial_in(port, FTSR);
+ struct sci_port *s = to_sci_port(port);
+
+ if (s->type == RSCI_PORT_SCI)
+ return !(rsci_serial_in(port, CSR) & CSR_TDRE);
+ else
+ return rsci_serial_in(port, FTSR);
}
static int rsci_rxfill(struct uart_port *port)
{
- u32 val = rsci_serial_in(port, FRSR);
+ struct sci_port *s = to_sci_port(port);
+ u32 val;
+
+ if (s->type == RSCI_PORT_SCI)
+ return (rsci_serial_in(port, CSR) & CSR_RDRF) != 0;
+
+ val = rsci_serial_in(port, FRSR);
return FIELD_GET(FRSR_R5_0, val);
}
@@ -357,7 +379,9 @@ static unsigned int rsci_tx_empty(struct uart_port *port)
static void rsci_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
- if (mctrl & TIOCM_LOOP) {
+ struct sci_port *s = to_sci_port(port);
+
+ if ((mctrl & TIOCM_LOOP) && s->type != RSCI_PORT_SCI) {
/* Standard loopback mode */
rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) | CCR1_SPLP);
}
@@ -478,12 +502,13 @@ static void rsci_transmit_chars(struct uart_port *port)
static void rsci_receive_chars(struct uart_port *port)
{
struct tty_port *tport = &port->state->port;
+ struct sci_port *s = to_sci_port(port);
u32 rdat, status, frsr_status = 0;
int i, count, copied = 0;
unsigned char flag;
status = rsci_serial_in(port, CSR);
- frsr_status = rsci_serial_in(port, FRSR);
+ frsr_status = (s->type == RSCI_PORT_SCI) ? 0 : rsci_serial_in(port, FRSR);
if (!(status & CSR_RDRF) && !(frsr_status & FRSR_DR))
return;
@@ -496,34 +521,40 @@ static void rsci_receive_chars(struct uart_port *port)
if (count == 0)
break;
- for (i = 0; i < count; i++) {
- char c;
-
- rdat = rsci_serial_in(port, RDR);
- /* 9-bits data is not supported yet */
- c = rdat & RDR_RDAT_MSK;
-
- if (uart_handle_sysrq_char(port, c)) {
- count--;
- i--;
- continue;
- }
-
- /*
- * Store data and status.
- * Non FIFO mode is not supported
- */
- if (rdat & RDR_FFER) {
- flag = TTY_FRAME;
- port->icount.frame++;
- } else if (rdat & RDR_FPER) {
- flag = TTY_PARITY;
- port->icount.parity++;
- } else {
- flag = TTY_NORMAL;
+ if (s->type == RSCI_PORT_SCI) {
+ char c = rsci_serial_in(port, RDR) & RDR_RDAT_MSK;
+
+ if (uart_handle_sysrq_char(port, c))
+ count = 0;
+ else
+ tty_insert_flip_char(tport, c, TTY_NORMAL);
+ } else {
+ for (i = 0; i < count; i++) {
+ char c;
+
+ rdat = rsci_serial_in(port, RDR);
+ /* 9-bits data is not supported yet */
+ c = rdat & RDR_RDAT_MSK;
+
+ if (uart_handle_sysrq_char(port, c)) {
+ count--;
+ i--;
+ continue;
+ }
+
+ /* Store data and status */
+ if (rdat & RDR_FFER) {
+ flag = TTY_FRAME;
+ port->icount.frame++;
+ } else if (rdat & RDR_FPER) {
+ flag = TTY_PARITY;
+ port->icount.parity++;
+ } else {
+ flag = TTY_NORMAL;
+ }
+
+ tty_insert_flip_char(tport, c, flag);
}
-
- tty_insert_flip_char(tport, c, flag);
}
rsci_serial_in(port, CSR); /* dummy read */
@@ -607,6 +638,8 @@ static const char *rsci_type(struct uart_port *port)
struct sci_port *s = to_sci_port(port);
switch (s->type) {
+ case RSCI_PORT_SCI:
+ return "sci";
case RSCI_PORT_SCIF:
return "scif";
}
@@ -650,6 +683,17 @@ static const struct sci_port_params rsci_port_params = {
.common_regs = &rsci_common_regs,
};
+static const struct sci_port_params rsci_rzg3e_sci_port_params = {
+ .fifosize = 1,
+ .overrun_reg = CSR,
+ .overrun_mask = CSR_ORER,
+ .sampling_rate_mask = SCI_SR(32),
+ .error_mask = RSCI_DEFAULT_ERROR_MASK,
+ .error_clear = RSCI_ERROR_CLEAR,
+ .param_bits = &rsci_port_param_bits,
+ .common_regs = &rsci_common_regs,
+};
+
static const struct sci_port_params rsci_rzg3e_scif_port_params = {
.fifosize = 32,
.overrun_reg = CSR,
@@ -701,6 +745,13 @@ struct sci_of_data of_sci_rsci_data = {
.params = &rsci_port_params,
};
+struct sci_of_data of_rsci_sci_data = {
+ .type = RSCI_PORT_SCI,
+ .ops = &rsci_port_ops,
+ .uart_ops = &rsci_uart_ops,
+ .params = &rsci_rzg3e_sci_port_params,
+};
+
struct sci_of_data of_rsci_scif_data = {
.type = RSCI_PORT_SCIF,
.ops = &rsci_port_ops,
@@ -716,12 +767,19 @@ static int __init rsci_early_console_setup(struct earlycon_device *device,
return scix_early_console_setup(device, &of_sci_rsci_data);
}
+static int __init rsci_rzg3e_sci_early_console_setup(struct earlycon_device *device,
+ const char *opt)
+{
+ return scix_early_console_setup(device, &of_rsci_sci_data);
+}
+
static int __init rsci_rzg3e_scif_early_console_setup(struct earlycon_device *device,
const char *opt)
{
return scix_early_console_setup(device, &of_rsci_scif_data);
}
+OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g047-rsci", rsci_rzg3e_sci_early_console_setup);
OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g047-rscif", rsci_rzg3e_scif_early_console_setup);
OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g077-rsci", rsci_early_console_setup);
diff --git a/drivers/tty/serial/rsci.h b/drivers/tty/serial/rsci.h
index ba255f58c088..df7a7edad7d4 100644
--- a/drivers/tty/serial/rsci.h
+++ b/drivers/tty/serial/rsci.h
@@ -6,6 +6,7 @@
#include "sh-sci-common.h"
extern struct sci_of_data of_sci_rsci_data;
+extern struct sci_of_data of_rsci_sci_data;
extern struct sci_of_data of_rsci_scif_data;
#endif /* __RSCI_H__ */
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 85b89c1ebf15..b7d9ea4091d2 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -3492,6 +3492,10 @@ static const struct of_device_id of_sci_match[] __maybe_unused = {
.data = &of_sci_scif_rzv2h,
},
#ifdef CONFIG_SERIAL_RSCI
+ {
+ .compatible = "renesas,r9a09g047-rsci",
+ .data = &of_rsci_sci_data,
+ },
{
.compatible = "renesas,r9a09g047-rscif",
.data = &of_rsci_scif_data,
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 01/13] dt-bindings: serial: renesas,rsci: Document RZ/G3E support
2025-10-30 17:57 Biju
@ 2025-10-30 17:57 ` Biju
2025-10-30 19:20 ` Conor Dooley
0 siblings, 1 reply; 19+ messages in thread
From: Biju @ 2025-10-30 17:57 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, Lad Prabhakar, linux-kernel, linux-serial, devicetree,
linux-renesas-soc, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Add documentation for the serial communication interface (RSCI) found on
the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC is identical
to that on the RZ/T2H (R9A09G077) SoC, but it has a 32-stage FIFO compared
to 16 on RZ/T2H. It supports both FIFO and non-FIFO mode operation. RZ/G3E
has 6 clocks(5 module clocks + 1 external clock) compared to 3 clocks
(2 module clocks + 1 external clock) on RZ/T2H, and it has multiple resets.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* Updated commit message
* Added resets:false for non RZ/G3E SoCs.
---
.../bindings/serial/renesas,rsci.yaml | 85 ++++++++++++++++---
1 file changed, 74 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
index 6b1f827a335b..1c2ed4cd58fd 100644
--- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
@@ -10,17 +10,16 @@ maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
-allOf:
- - $ref: serial.yaml#
-
properties:
compatible:
oneOf:
- - items:
- - const: renesas,r9a09g087-rsci # RZ/N2H
- - const: renesas,r9a09g077-rsci # RZ/T2H
+ - enum:
+ - renesas,r9a09g047-rsci # RZ/G3E non FIFO mode
+ - renesas,r9a09g047-rscif # RZ/G3E FIFO mode
+ - renesas,r9a09g077-rsci # RZ/T2H
- items:
+ - const: renesas,r9a09g087-rsci # RZ/N2H
- const: renesas,r9a09g077-rsci # RZ/T2H
reg:
@@ -42,14 +41,40 @@ properties:
clocks:
minItems: 2
- maxItems: 3
+ maxItems: 6
clock-names:
- minItems: 2
+ oneOf:
+ - items:
+ - const: operation
+ - const: bus
+ - items:
+ - const: operation
+ - const: bus
+ - const: sck # optional external clock input
+ - items:
+ - const: bus
+ - const: tclk
+ - const: tclk_div64
+ - const: tclk_div16
+ - const: tclk_div4
+ - items:
+ - const: bus
+ - const: tclk
+ - const: tclk_div64
+ - const: tclk_div16
+ - const: tclk_div4
+ - const: sck # optional external clock input
+
+ resets:
+ items:
+ - description: Input for resetting the APB clock
+ - description: Input for resetting TCLK
+
+ reset-names:
items:
- - const: operation
- - const: bus
- - const: sck # optional external clock input
+ - const: presetn
+ - const: tresetn
power-domains:
maxItems: 1
@@ -62,6 +87,44 @@ required:
- clock-names
- power-domains
+allOf:
+ - $ref: serial.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g077-rsci
+ then:
+ properties:
+ clocks:
+ maxItems: 3
+
+ clock-names:
+ maxItems: 3
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,r9a09g047-rsci
+ - renesas,r9a09g047-rscif
+ then:
+ properties:
+ clocks:
+ minItems: 5
+
+ clock-names:
+ minItems: 5
+
+ required:
+ - resets
+ - reset-names
+ else:
+ properties:
+ resets: false
+
unevaluatedProperties: false
examples:
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* RE: [PATCH v2 00/13] Add RZ/G3E RSCI support
2025-10-30 17:55 [PATCH v2 00/13] Add RZ/G3E RSCI support Biju
` (12 preceding siblings ...)
2025-10-30 17:55 ` [PATCH v2 13/13] serial: sh-sci: Add support for RZ/G3E RSCI SCI Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Jiri Slaby <jirislaby@kernel.org> Biju
@ 2025-10-30 17:59 ` Biju Das
13 siblings, 0 replies; 19+ messages in thread
From: Biju Das @ 2025-10-30 17:59 UTC (permalink / raw)
To: biju.das.au, Greg Kroah-Hartman, Jiri Slaby, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven,
magnus.damm
Cc: Prabhakar Mahadev Lad, linux-kernel@vger.kernel.org,
linux-serial@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, biju.das.au
Hi All,
There is some issue with last patch in the series. So, resending again.
Sorry for the noise.
Cheers,
Biju
> -----Original Message-----
> From: Biju <biju.das.au@gmail.com>
> Sent: 30 October 2025 17:55
> Subject: [PATCH v2 00/13] Add RZ/G3E RSCI support
>
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Add RZ/G3E RSCI support for FIFO and non-FIFO mode. RSCI IP found on RZ/G3E SoC is similar to one on
> RZ/T2H, but has 32-stage fifo. RZ/G3E has
> 6 clocks (5 module clocks + 1 external clock) compared to 3 clocks
> (2 module clocks + 1 external clock) on RZ/T2H, and it has multiple resets. Add support for the
> hardware flow control.
>
> This patch series depend upon [1]
> [1] https://lore.kernel.org/all/20251029082101.92156-1-biju.das.jz@bp.renesas.com/
>
> v1->v2:
> * Updated commit message for patch#1,#3,#9
> * Added resets:false for non RZ/G3E SoCs in bindings.
> * Increased line limit for error messages to 100-column limit for patch#3
> * Updated multiline comment to fit into single line.
> * Updated set_termios() for getting baud_rate()
>
> Biju Das (13):
> dt-bindings: serial: renesas,rsci: Document RZ/G3E support
> serial: rsci: Drop rsci_clear_CFC()
> serial: sh-sci: Drop extra lines
> serial: rsci: Drop unused macro DCR
> serial: rsci: Drop unused TDR register
> serial: sh-sci: Use devm_reset_control_array_get_exclusive()
> serial: sh-sci: Add RSCI_PORT_{SCI,SCIF} port IDs
> serial: sh-sci: Add sci_is_rsci_type()
> serial: sh-sci: Add support for RZ/G3E RSCI clks
> serial: sh-sci: Make sci_scbrr_calc() public
> serial: sh-sci: Add finish_console_write() callback
> serial: sh-sci: Add support for RZ/G3E RSCI SCIF
> serial: sh-sci: Add support for RZ/G3E RSCI SCI
>
> .../bindings/serial/renesas,rsci.yaml | 85 +++-
> drivers/tty/serial/rsci.c | 412 +++++++++++++++---
> drivers/tty/serial/rsci.h | 2 +
> drivers/tty/serial/sh-sci-common.h | 9 +
> drivers/tty/serial/sh-sci.c | 67 ++-
> 5 files changed, 492 insertions(+), 83 deletions(-)
>
> --
> 2.43.0
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v2 01/13] dt-bindings: serial: renesas,rsci: Document RZ/G3E support
2025-10-30 17:57 ` [PATCH v2 01/13] dt-bindings: serial: renesas,rsci: Document RZ/G3E support Biju
@ 2025-10-30 19:20 ` Conor Dooley
0 siblings, 0 replies; 19+ messages in thread
From: Conor Dooley @ 2025-10-30 19:20 UTC (permalink / raw)
To: Biju
Cc: Greg Kroah-Hartman, Jiri Slaby, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm, Biju Das,
Lad Prabhakar, linux-kernel, linux-serial, devicetree,
linux-renesas-soc
[-- Attachment #1: Type: text/plain, Size: 798 bytes --]
On Thu, Oct 30, 2025 at 05:57:49PM +0000, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Add documentation for the serial communication interface (RSCI) found on
> the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC is identical
> to that on the RZ/T2H (R9A09G077) SoC, but it has a 32-stage FIFO compared
> to 16 on RZ/T2H. It supports both FIFO and non-FIFO mode operation. RZ/G3E
> has 6 clocks(5 module clocks + 1 external clock) compared to 3 clocks
> (2 module clocks + 1 external clock) on RZ/T2H, and it has multiple resets.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v1->v2:
> * Updated commit message
> * Added resets:false for non RZ/G3E SoCs.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
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^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v2 01/13] dt-bindings: serial: renesas,rsci: Document RZ/G3E support
2025-10-30 17:55 ` [PATCH v2 01/13] dt-bindings: serial: renesas,rsci: Document RZ/G3E support Biju
@ 2025-10-31 0:00 ` Rob Herring
2025-11-13 15:26 ` Biju Das
0 siblings, 1 reply; 19+ messages in thread
From: Rob Herring @ 2025-10-31 0:00 UTC (permalink / raw)
To: Biju
Cc: Greg Kroah-Hartman, Jiri Slaby, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, Biju Das, Lad Prabhakar,
linux-kernel, linux-serial, devicetree, linux-renesas-soc
On Thu, Oct 30, 2025 at 05:55:05PM +0000, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Add documentation for the serial communication interface (RSCI) found on
> the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC is identical
> to that on the RZ/T2H (R9A09G077) SoC, but it has a 32-stage FIFO compared
> to 16 on RZ/T2H. It supports both FIFO and non-FIFO mode operation. RZ/G3E
> has 6 clocks(5 module clocks + 1 external clock) compared to 3 clocks
> (2 module clocks + 1 external clock) on RZ/T2H, and it has multiple resets.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v1->v2:
> * Updated commit message
> * Added resets:false for non RZ/G3E SoCs.
> ---
> .../bindings/serial/renesas,rsci.yaml | 85 ++++++++++++++++---
> 1 file changed, 74 insertions(+), 11 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> index 6b1f827a335b..1c2ed4cd58fd 100644
> --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> @@ -10,17 +10,16 @@ maintainers:
> - Geert Uytterhoeven <geert+renesas@glider.be>
> - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> -allOf:
> - - $ref: serial.yaml#
> -
> properties:
> compatible:
> oneOf:
> - - items:
> - - const: renesas,r9a09g087-rsci # RZ/N2H
> - - const: renesas,r9a09g077-rsci # RZ/T2H
> + - enum:
> + - renesas,r9a09g047-rsci # RZ/G3E non FIFO mode
> + - renesas,r9a09g047-rscif # RZ/G3E FIFO mode
> + - renesas,r9a09g077-rsci # RZ/T2H
>
> - items:
> + - const: renesas,r9a09g087-rsci # RZ/N2H
> - const: renesas,r9a09g077-rsci # RZ/T2H
>
> reg:
> @@ -42,14 +41,40 @@ properties:
>
> clocks:
> minItems: 2
> - maxItems: 3
> + maxItems: 6
>
> clock-names:
> - minItems: 2
> + oneOf:
> + - items:
> + - const: operation
> + - const: bus
> + - items:
> + - const: operation
> + - const: bus
> + - const: sck # optional external clock input
minItems: 2
And drop the 1st items list.
> + - items:
> + - const: bus
> + - const: tclk
> + - const: tclk_div64
> + - const: tclk_div16
> + - const: tclk_div4
> + - items:
> + - const: bus
> + - const: tclk
> + - const: tclk_div64
> + - const: tclk_div16
> + - const: tclk_div4
> + - const: sck # optional external clock input
minItems: 5
and drop the 3rd items list.
> +
> + resets:
> + items:
> + - description: Input for resetting the APB clock
> + - description: Input for resetting TCLK
> +
> + reset-names:
> items:
> - - const: operation
> - - const: bus
> - - const: sck # optional external clock input
> + - const: presetn
> + - const: tresetn
>
> power-domains:
> maxItems: 1
> @@ -62,6 +87,44 @@ required:
> - clock-names
> - power-domains
>
> +allOf:
> + - $ref: serial.yaml#
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,r9a09g077-rsci
> + then:
> + properties:
> + clocks:
> + maxItems: 3
> +
> + clock-names:
> + maxItems: 3
You need minItems and maxItems here as the range is 2-6 clocks.
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - renesas,r9a09g047-rsci
> + - renesas,r9a09g047-rscif
> + then:
> + properties:
> + clocks:
> + minItems: 5
> +
> + clock-names:
> + minItems: 5
And maxItems here in addition.
> +
> + required:
> + - resets
> + - reset-names
> + else:
> + properties:
> + resets: false
> +
> unevaluatedProperties: false
>
> examples:
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* RE: [PATCH v2 01/13] dt-bindings: serial: renesas,rsci: Document RZ/G3E support
2025-10-31 0:00 ` Rob Herring
@ 2025-11-13 15:26 ` Biju Das
0 siblings, 0 replies; 19+ messages in thread
From: Biju Das @ 2025-11-13 15:26 UTC (permalink / raw)
To: Rob Herring, biju.das.au
Cc: Greg Kroah-Hartman, Jiri Slaby, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, magnus.damm, Prabhakar Mahadev Lad,
linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Hi Rob,
Thanks for the feedback.
> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: 31 October 2025 00:00
> Subject: Re: [PATCH v2 01/13] dt-bindings: serial: renesas,rsci: Document RZ/G3E support
>
> On Thu, Oct 30, 2025 at 05:55:05PM +0000, Biju wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Add documentation for the serial communication interface (RSCI) found
> > on the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC is
> > identical to that on the RZ/T2H (R9A09G077) SoC, but it has a 32-stage
> > FIFO compared to 16 on RZ/T2H. It supports both FIFO and non-FIFO mode
> > operation. RZ/G3E has 6 clocks(5 module clocks + 1 external clock)
> > compared to 3 clocks
> > (2 module clocks + 1 external clock) on RZ/T2H, and it has multiple resets.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v1->v2:
> > * Updated commit message
> > * Added resets:false for non RZ/G3E SoCs.
> > ---
> > .../bindings/serial/renesas,rsci.yaml | 85 ++++++++++++++++---
> > 1 file changed, 74 insertions(+), 11 deletions(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> > b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> > index 6b1f827a335b..1c2ed4cd58fd 100644
> > --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> > +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> > @@ -10,17 +10,16 @@ maintainers:
> > - Geert Uytterhoeven <geert+renesas@glider.be>
> > - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > -allOf:
> > - - $ref: serial.yaml#
> > -
> > properties:
> > compatible:
> > oneOf:
> > - - items:
> > - - const: renesas,r9a09g087-rsci # RZ/N2H
> > - - const: renesas,r9a09g077-rsci # RZ/T2H
> > + - enum:
> > + - renesas,r9a09g047-rsci # RZ/G3E non FIFO mode
> > + - renesas,r9a09g047-rscif # RZ/G3E FIFO mode
> > + - renesas,r9a09g077-rsci # RZ/T2H
> >
> > - items:
> > + - const: renesas,r9a09g087-rsci # RZ/N2H
> > - const: renesas,r9a09g077-rsci # RZ/T2H
> >
> > reg:
> > @@ -42,14 +41,40 @@ properties:
> >
> > clocks:
> > minItems: 2
> > - maxItems: 3
> > + maxItems: 6
> >
> > clock-names:
> > - minItems: 2
> > + oneOf:
> > + - items:
> > + - const: operation
> > + - const: bus
> > + - items:
> > + - const: operation
> > + - const: bus
> > + - const: sck # optional external clock input
>
> minItems: 2
>
> And drop the 1st items list.
OK.
>
> > + - items:
> > + - const: bus
> > + - const: tclk
> > + - const: tclk_div64
> > + - const: tclk_div16
> > + - const: tclk_div4
> > + - items:
> > + - const: bus
> > + - const: tclk
> > + - const: tclk_div64
> > + - const: tclk_div16
> > + - const: tclk_div4
> > + - const: sck # optional external clock input
>
> minItems: 5
>
> and drop the 3rd items list.
OK.
>
> > +
> > + resets:
> > + items:
> > + - description: Input for resetting the APB clock
> > + - description: Input for resetting TCLK
> > +
> > + reset-names:
> > items:
> > - - const: operation
> > - - const: bus
> > - - const: sck # optional external clock input
> > + - const: presetn
> > + - const: tresetn
> >
> > power-domains:
> > maxItems: 1
> > @@ -62,6 +87,44 @@ required:
> > - clock-names
> > - power-domains
> >
> > +allOf:
> > + - $ref: serial.yaml#
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: renesas,r9a09g077-rsci
> > + then:
> > + properties:
> > + clocks:
> > + maxItems: 3
> > +
> > + clock-names:
> > + maxItems: 3
>
> You need minItems and maxItems here as the range is 2-6 clocks.
Ok.
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - renesas,r9a09g047-rsci
> > + - renesas,r9a09g047-rscif
> > + then:
> > + properties:
> > + clocks:
> > + minItems: 5
> > +
> > + clock-names:
> > + minItems: 5
>
> And maxItems here in addition.
OK. Will fix this in next version.
Cheers,
Biju
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2025-11-13 15:26 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-10-30 17:55 [PATCH v2 00/13] Add RZ/G3E RSCI support Biju
2025-10-30 17:55 ` [PATCH v2 01/13] dt-bindings: serial: renesas,rsci: Document RZ/G3E support Biju
2025-10-31 0:00 ` Rob Herring
2025-11-13 15:26 ` Biju Das
2025-10-30 17:55 ` [PATCH v2 02/13] serial: rsci: Drop rsci_clear_CFC() Biju
2025-10-30 17:55 ` [PATCH v2 03/13] serial: sh-sci: Drop extra lines Biju
2025-10-30 17:55 ` [PATCH v2 04/13] serial: rsci: Drop unused macro DCR Biju
2025-10-30 17:55 ` [PATCH v2 05/13] serial: rsci: Drop unused TDR register Biju
2025-10-30 17:55 ` [PATCH v2 06/13] serial: sh-sci: Use devm_reset_control_array_get_exclusive() Biju
2025-10-30 17:55 ` [PATCH v2 07/13] serial: sh-sci: Add RSCI_PORT_{SCI,SCIF} port IDs Biju
2025-10-30 17:55 ` [PATCH v2 08/13] serial: sh-sci: Add sci_is_rsci_type() Biju
2025-10-30 17:55 ` [PATCH v2 09/13] serial: sh-sci: Add support for RZ/G3E RSCI clks Biju
2025-10-30 17:55 ` [PATCH v2 10/13] serial: sh-sci: Make sci_scbrr_calc() public Biju
2025-10-30 17:55 ` [PATCH v2 11/13] serial: sh-sci: Add finish_console_write() callback Biju
2025-10-30 17:55 ` [PATCH v2 12/13] serial: sh-sci: Add support for RZ/G3E RSCI SCIF Biju
2025-10-30 17:55 ` [PATCH v2 13/13] serial: sh-sci: Add support for RZ/G3E RSCI SCI Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Jiri Slaby <jirislaby@kernel.org> Biju
2025-10-30 17:59 ` [PATCH v2 00/13] Add RZ/G3E RSCI support Biju Das
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2025-10-30 17:57 Biju
2025-10-30 17:57 ` [PATCH v2 01/13] dt-bindings: serial: renesas,rsci: Document RZ/G3E support Biju
2025-10-30 19:20 ` Conor Dooley
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